103 results about "Partial product" patented technology

The invention relates to the technical field of artificial intelligence and natural language processing, in particular to a KV cache compression and eviction lexical element recovery method and system for large language model reasoning, and the method comprises the steps: for a query vector of an ith lexical element calculated by a current Transform layer, calculating attention scores of the query vector and all key vectors; executing a V cache dynamic updating operation based on the attention score; and for the ith lexical element, after the V cache dynamic updating operation is completely completed, performing attention calculation by using the updated value vector set in the V cache storage pool and the pre-calculated attention score partial product P. According to the technical scheme, the technical problem that in the prior art, collaborative optimization of video memory occupancy and calculation efficiency is difficult is solved, and the method has the advantages that KV cache video memory occupancy is dynamically managed, the model reasoning quality is kept, and the calculation efficiency is improved.

The invention discloses a compressor based on a cascade full adder for multiplication and a partial product array compression method, which are used for solving the technical problem that the delay of a compression step is relatively high because most of the existing compressors carry out optimization calculation on an input partial product array based on the idea of a traditional Dada tree. The compressor comprises a first parallel 3-2 compressor circuit, a first parallel cascade 3-2 compressor circuit, a second parallel 3-2 compressor circuit, a second parallel cascade 3-2 compressor circuit and a serial 3-2 / 2-2 compressor circuit; the input partial product array is compressed through a first parallel 3-2 compressor circuit, a first parallel cascade 3-2 compressor circuit, a second parallel 3-2 compressor circuit and a second parallel cascade 3-2 compressor circuit, after a fourth initial compression result is obtained, a serial 3-2 / 2-2 compressor circuit is adopted for accumulation, and a target compression result is generated.

The invention discloses a high-speed fixed-point multiplication circuit. The multiplication circuit is mainly composed of a multiplier coding module, a partial product generation module, a partial product compression module and a traveling wave carry adder module. The multiplier coding module is composed of a radix-4-Booth coding algorithm and an opposite number generation module, and is used for carrying out three-bit block coding on input multiplication data and generating an opposite number of a multiplicand in advance. The partial product generation module generates a plurality of groups of partial products with symbol extension according to the multiplicand coded signal. And the partial product compression module adopts an improved Wallace compression structure to perform layered compression on the partial product. And the traveling wave carry adder module sums the two groups of results output by compression and outputs a multiplication result. According to the invention, multiplication accumulation series can be reduced, the switching times of invalid signals in the circuit can be reduced, and the longest delay path in an operation link can be shortened, so that fixed-point multiplication which is high in speed, low in power consumption and more favorable for a comprehensive tool in structure is realized.

A system and method for providing a tunable floating-point multiply-accumulate (MAC) unit are disclosed. The unit maintains full arithmetic precision while enabling dynamic elimination of ineffectual computation through operand decomposition and selective activation of partial product generation logic. The disclosed MAC unit is suitable for drop-in replacement in existing deep-learning accelerators and improves energy efficiency without requiring architectural changes.

The invention discloses a circuit for approximate floating point fusion dot product operation. The circuit comprises an extraction module used for extracting sign bits, mantissa bits and exponent bits from four single-precision floating point numbers; the symbol integration module is used for integrating symbol bits and correcting mantissa bits; the index comparison module is used for calculating two groups of dot product effective indexes according to the index bits and generating three control quantities; the first multiplication module is used for generating a first group of approximate partial products according to a correction mantissa digit corresponding to a first control quantity larger value; the second multiplication module is used for generating a second group of approximate partial products according to the correction mantissa digit corresponding to the smaller value of the first control quantity, and performing arithmetic displacement and adding symbol compensation bits according to the size of the second control quantity; the fusion compression module is used for performing fusion compression on the first group of approximate partial products, the second group of approximate partial products after arithmetic shift and the symbol compensation bits to obtain a sum sequence and a carry sequence; and the result output module is used for generating a dot product operation result in combination with the third control quantity.

The invention discloses an approximate multiplier, an operation method thereof, a processor and a chip, and belongs to the field of integrated circuits. The approximate multiplier comprises a high-order processing circuit, a low-order processing circuit, a high-low-order fusion circuit and an error compensation circuit, and the high-order processing circuit adopts a plurality of negative deviation approximate addition units, performs approximate addition on a high-order area of a partial product step by step and outputs an error signal; the low-order processing circuit adopts a positive deviation addition unit to process the low-order area to generate an intermediate result of positive deviation; the fusion circuit merges the high and low position results and outputs an initial multiplication result; the error compensation circuit compensates the result high order according to the error signal to offset the deviation. According to the approximate multiplier provided by the invention, the comprehensive performance of the multiplication unit in the aspects of area, power consumption and speed can be improved while the basic calculation precision is ensured.

A hardware module for performing dot product operations includes receiver circuitry receiving a first vector and a second vector, each comprising at least two elements of a binary encoded integer. Logic generates an array of partial products of N rows of bits for a dot product operation between the first vector and the second vector. Grouping circuitry groups bits of the elements of the second vector into a binary number, wherein each binary number is associated with a respective row of the N rows of bits, and selector circuitry selects a partial product value for each of the N rows of bits based on the binary number that is associated with the respective row, such that one partial product is generated per binary number. The hardware module also comprises adder circuitry configured to perform adding the N rows of bits together to compute an output associated with the dot product operation between the first and second vectors.

The present disclosure provides implementations of a filter suitable for use in quantum computing systems and other low-power, high-speed applications. In some aspects, a filter circuit includes a series-connected arrangement of unit delays and summers in an alternating pattern. The filter circuit further includes a plurality of coefficient multipliers, each having a respective output connected with one or more of the summers, and each including a multiplexing stage including one or more multiplexers addressed using one or more bits of a respective input coefficient vector. A first coefficient multiplier of the plurality of coefficient multipliers includes a partial product stage configured to provide a plurality of integer partial products of an input data vector to the multiplexing stages of the plurality of coefficient multipliers.

The application provides a kind of approximate precoding convolution operation method and system based on booth algorithm, comprising: step S1: multiplier and multiplicand input multiplier are separated by approximate precoding module to partial product, and the partial product related to the multiplicand after separation is input to addition tree module to complete compression, and the partial product related to the multiplicand after compression and the partial product related to the multiplier are added to obtain multiplier result;Step S2: the multiplier result is extended to sign bit, and the extended multiplier result is input into accumulation module to carry out shift and addition operation, and the shift addition operation result is carried out carry compensation.

The invention discloses a structured sparse matrix multiplier realized based on FPGA primitives, and belongs to the technical field of FPGA hardware acceleration and deep learning computing architecture. The multiplier is composed of a register area and a multiplication and addition area, and the core design thought is that a circuit is built in a customized mode by directly calling bottom layer physical resources based on FPGA primitives; the register area stores a dense matrix B and supports parallel reading of elements by utilizing the characteristic that LUT in an SLICEM can be configured to be double SRL16E; the multiplication and addition area refers to a partial product generation unit based on the 4-Booth algorithm and an improved GPC (4: 2) compressor structure, and efficient generation and rapid accumulation of partial products are achieved. According to the method, redundant loss caused by high-level HDL logic synthesis is avoided through precise physical resource binding of primitives, fine wiring constraint and structured sparse data characteristic adaptation.

The present disclosure relates to a multiplier, a multiply-accumulate circuit, and a convolution operation unit. The multiplier includes: one or more selection circuits, each of the one or more selection circuits respectively configured to select a target preset multiple of a first operand from a preset multiple of a first operand as a fourth operand according to a corresponding third operand, wherein the target preset multiple is equal to a value of the third operand; and a partial product summing circuit, each of one or more input terminals of the partial product summing circuit respectively connected to an output terminal of corresponding one of at least one or more selection circuits, wherein the partial product summing circuit is configured to calculate a partial product sum of one or more fourth operands from the one or more selection circuits.

Computer computing device with optimized cache memory for matrix calculation Computer computing device (100), comprising: - a computing unit (102); - a main memory (104); - a cache memory (106) comprising a computing circuit (108) for reduction operations between partial products from values ​​of a sparse matrix (118) and an input vector, and an output vector; in which the cache memory has a first N-way associative memory region (112) storing, with a first granularity of TD words, results of reduction operations carried out from partial products from a dense region (120) of the matrix, and a second fully associative or M-way associative memory region (114) storing, with a second granularity of TS words, results of reduction operations carried out from partial products from a sparse region (124) of the matrix. Figure for the abridged version: Fig. 1

The invention provides an in-memory calculation circuit for realizing high-speed multiplication. The in-memory calculation circuit comprises a dual-output Raidx-8Booth encoder array, an in-memory calculation array and a partial product post-processing module, the dual-output Raidx-8Booth encoder array comprises m rows and z columns of dual-output Raidx-8Booth encoders, the dual-output Raidx-8Booth encoders encode a multiplier I and generate a control signal, and the calculation array in the memory is controlled to generate an intermediate result expressed by redundant numbers; data carrying is reduced, and the throughput rate and the energy efficiency of the system are improved. Meanwhile, a redundant coding method is applied to an in-memory computing structure, which is beneficial for eliminating carry transfer in the traditional multiplication operation by using parallel processing and a mode of compressing partial products by using a carry-free addition tree.

Multiplier Circuit This description relates to a circuit configured to perform a multiplication operation between a first value and a second value, the first and second values ​​each comprising up to N pieces of bits respectively, the circuit comprising: - an NMUL number of multiplier subcircuits configured to generate first partial products, each first partial product corresponding to a multiplication between a piece from among the pieces of the first value and a piece from among the pieces of the second value; - an adding part configured to generate a first intermediate sum and first excess bit values, from the first partial products;and a parallel adder configured to generate a value corresponding to the product between the first and second values ​​from the first intermediate sum and the first integer bit generated by the first adder circuit and the second processing circuit. Figure for the abbreviation: Fig. 5;

The invention provides an approximate multiplier based on a field programmable gate array (FPGA), which comprises an asymmetric partial product generation module, a signal processing module and a signal processing module, and is characterized in that the asymmetric partial product generation module is used for processing a received N-bit multiplier and a received N-bit multiplicand to generate an asymmetric approximate partial product matrix of which the line number is halved; the single-step compression module is used for compressing the asymmetric approximate partial product matrix into two rows at one time; and the final summing module is used for summing the two rows of compressed data and outputting a final product. Through the collaborative design of asymmetric partial product generation and single-step compression, high-energy-efficiency and low-delay approximate multiplication is realized on an FPGA platform, and the method is suitable for application scenes such as resource-limited edge calculation and the like.

A method and apparatus for reducing computation time are disclosed herein which provides in at least one embodiment a computer-implemented method for reducing computation time, the computer-implemented method including the steps of: receiving one or more bits from a multiplier, generating a shift signal by using the one or more bits, performing a shift operation by n bits (where n is a natural number) based on the shift signal to obtain a partial product, and generating an output product by using the partial product and then outputting the output product.

The present invention discloses an approximate squarer, which includes an accurate Booth folding encoder and decoder circuit, an approximate Booth folding encoder and decoder circuit, an accurate partial product compression circuit, an approximate partial product compression circuit, and a carry-ripple adder circuit; the accurate Booth folding encoder and decoder divide the high n-k bits of the input operand into groups of three bits, generate the accurate partial products of part P and the accurate partial products of part C, and output them to the accurate partial product compression circuit; the approximate Booth folding encoder and decoder divide the low k bits of the input operand into groups of three bits, generate the approximate partial products of part P and the approximate partial products of part C, and output them to the approximate partial product compression circuit. The present invention can achieve lower power consumption and area, lower cost; and has a faster calculation speed, which is more advantageous for communication and machine learning applications.

This invention discloses a vector floating-point multiply-adder suitable for floating-point operations of various precisions, comprising a first operation module, a second operation module, a third operation module, and a fourth operation module. The first operation module includes a partial product generation module, a Wallace network, a first inversion module, an exponent alignment module, a mantissa compound right shifter, a sticky logic module, and an exception pre-judgment module. The second operation module includes a 3:2 CSA adder, a CPA adder, an increment circuit, a GRS logic module, and a sign pre-judgment module. The third operation module includes a second inversion module, a leading zero detection module, a trailing zero detection module, a normalized compound left shifter module, a normalization correction module, a rounding preprocessing module, a fast GRS solver module, and an exponent adjustment module. The fourth operation module includes a mantissa increment logic module, an exponent increment logic module, a sign judgment module, an exception judgment module, and a control logic output module. This invention balances computational speed and chip area, enabling parallel execution of floating-point multiply-add operations of various precisions.

The invention provides a floating-point number multiplier, a near memory computing circuit, a high-bandwidth magnetic computing chip system and electronic equipment, and relates to the technical field of circuits, and the floating-point number multiplier comprises a compression circuit and a partial product generation circuit; the floating-point number multiplier is used for realizing mantissa multiplication of a known floating-point number of a multiplier; the partial product generation circuit comprises: a one-out-of-four selector; the compression circuit comprises a compressor and a summator. The one-out-of-four selector is used for generating a partial product of a known multiplier and a multiplicand after NR4SD + coding; the compressor is used for carrying out parallel compression on the partial product output by the one-out-of-four selector; and the adder is used for accumulating the parallel compression results output by the compressor and outputting an accumulation result to finish mantissa multiplication of the known multiplier and the multiplicand. The storage efficiency can be improved, and the area and power consumption of a hardware circuit are reduced.

The present application provides a data processing system and method, an encoding unit, a processing unit, and a storage medium. The data processing system includes an encoding unit and a processing unit. The encoding unit is configured to: obtain data to be encoded; perform encoding processing on the data to be encoded to obtain first input data. The processing unit is configured to: perform partial product generation processing on the first input data and second input data to obtain a partial product result; perform accumulation processing on the partial product result to obtain a convolution result. Wherein, the data to be encoded is convolution kernel data, and the second input data is feature layer data; or, the data to be encoded is feature layer data, and the second input data is convolution kernel data. The technical solution provided by the present application reduces the internal processing logic and hardware complexity of the processing unit and improves the processing efficiency of the processing unit.

The invention relates to the technical field of integrated circuit design, in particular to a processing circuit architecture supporting multi-calculation precision dynamic switching, which comprises a control port module, a partial product generation module, a symbol compression module, an addition compression tree module and a final adder module. And single-cycle dynamic switching of various precisions is realized. The partial product generation module adopts a Booth coding algorithm to split an operation vector, and cooperates with boundary symbol selection logic to solve the problem of symbol expansion and auxiliary bit overlapping; the symbol compression module compresses the redundant extension bits through a preset coding mode; the addition compression tree module is formed by cascading multiple stages of compressors and inserting carry blocking logic; the final adder module is composed of a plurality of carry lookahead adders, and the output bit width is dynamically controlled through blocking logic. The architecture optimizes the parallel operation efficiency and the resource utilization rate, adapts to the deep learning training and reasoning full scene, and has the advantages of real-time performance and low power consumption.

The invention discloses a method for realizing multiplication operation based on an FPGA, computer equipment and a storage medium, and the method comprises the steps: traversing each multiplication unit in a circuit netlist, obtaining an input signal and an output signal of each multiplication unit, comparing the bit width of the input signal, and determining a multiplier signal; traversing the multiplier signal according to a sequence from low to high, wherein each continuous three-bit signal of the multiplier signal generates a corresponding coding logic unit; each continuous three-bit signal of the multiplier signal generates a corresponding partial product signal, and the partial product signal is stored in a partial product signal set C; performing iterative summation on the partial product signals in the partial product signal set C; carrying out traveling wave carry addition on partial product signals in the partial product signal set C; and deleting the multiplication unit in the circuit netlist. The multiplication units in the circuit netlist are processed through FPGA traversal, multiplication operation in the circuit is achieved, consumption of basic logic resources is reduced, and the application performance of the circuit is improved.

The invention belongs to the field of heterogeneous approximate calculation, and relates to a high-precision random calculation method based on a binary partial product and a multiplier. The high-precision random calculation method based on the binary partial product directly uses the weight of a bit corresponding to a binary number to generate a random bit stream. Bit streams are combined in a uniform distribution mode, phase and sum are carried out bit by bit, and all phase and results are added to obtain the random calculation multiplier with the optimal precision. According to the method, binary weights are combined, a shifting and splicing mode is used for replacing addition, partial product addition is used for achieving random calculation, and an approximate parallel counter is adopted for optimization. The multiplier provided by the invention fully combines the advantages of random calculation and binary calculation, the hardware cost is less than half of that of a binary multiplier, and the delay is lower. When the provided multiplier is applied to neural network reasoning, the precision of model loss can be almost ignored.

The invention provides a partial product decoupling-based dynamic precision approximate multiplication implementation method and a multiplier, and the multiplier comprises a significance evaluation unit which splits a first operand and a second operand into high digits and low digits, and correspondingly generates a first amplitude and a second amplitude; different precision instructions are generated based on the amplitudes and the threshold values; the dynamic precision unit performs zero setting processing on the second low digit based on the precision instruction to form an approximate number, and calculates a partial product of the first high digit and the approximate number; the accurate calculation unit accurately calculates products of the other three parts; and the final addition unit sums the products of the four parts according to the weight. The calculation unit can be used for constructing or optimizing a multiplication calculation array in a neural network hardware accelerator, is particularly suitable for scenes with dense fixed-point number operation such as convolution, and performs efficient approximate operation on the input fixed-point number through a data driving mechanism by utilizing the common sparsity and amplitude difference characteristics of neural network data, so that the calculation efficiency is improved. And self-adaptive management of power consumption is realized.

A modular multiplier includes a random number generator that generates a random number, a memory that stores at least one lookup table including results of pre-computed modular arithmetic, and a processor that obtains results of modular arithmetic on partial products defined by a product of a first polynomial corresponding to a first input and a second polynomial corresponding to a second input with reference to the at least one lookup table, and generates a result of modular arithmetic on a product of the first input and the second input based on addition arithmetic of the obtained results of the modular arithmetic. The processor randomly determines at least one of an order of the addition arithmetic or an acquisition order of modular arithmetic results on the partial products based on the random number generated by the random number generator.

The present description concerns a circuit configured to perform a multiplication between first and second values each comprising up to a number N of chunks of n bits, comprising: a number NMUL of multiplier sub-circuits configured to generate partial products corresponding to a multiplication between one chunk of the first value and one chunk of the second value; an adder part configured to generate an intermediate sum, corresponding to the addition of partial products of same significance, and excess bit values; an input crossbar circuit configured to select at least one chunk of the first value and at least one chunk of the second value and to provide them to one of the multiplier sub-circuits; a control unit configured to indicate which chunks to supply to which multiplier sub-circuit; and a parallel adder configured to generate a value corresponding to the product.

The invention discloses an in-memory multiply-accumulate and similarity calculation circuit based on dynamic logic, which is used for supporting the design of an in-memory calculation macro cell and an accelerator in a digital domain, and provides an in-memory calculation circuit architecture which supports a Booth coding rule for inputting similarity calculation. On the basis, a local input sharing calculation unit and a decoding and addition tree unit are designed, and element-by-element multiply-accumulate calculation and similarity calculation of fixed data are supported. Compared with a traditional multiply-accumulate circuit, the multiply-accumulate circuit disclosed by the invention adopts a calculation mode of firstly carrying out Booth coding on input data, then generating a multiply-accumulate partial product and finally carrying out decoding accumulation, and meanwhile, a partial product generation and similarity calculation circuit is designed based on dynamic logic, so that the partial product is multiplexed, and multiply-accumulate calculation is realized element by element with smaller calculation overhead; the face effect and the energy efficiency are both considered, and the comprehensive performance of the computing architecture and the circuit is improved.

A method of a neural network processor performing a multiplication operation and a neural network processor. In some embodiments, the method includes forming a first set of products and forming a second set of products. Forming the first set of products can include multiplying, in a first multiplier, a first activation value with a least significant subword and a most significant subword of a first weight to form a first partial product and a second partial product, and adding the first partial product and the second partial product. Forming the second set of products can include multiplying, in the first multiplier, a second activation value with a first subword and a second subword of a mantissa to form a third partial product and a fourth partial product, and adding the third partial product and the fourth partial product.

This invention provides an approximate 4-bit lookup table multiplier, relating to the field of integrated circuits, comprising: a conversion module, a first-stage multiplication module, and a second-stage multiplication module. During the multiplication process, for two compressed partial products with the same input, a 6-input, 2-output lookup table (LUT6_2) is used for simultaneous calculation. For three compressed partial products with the same input, the precision loss of each compressed partial product is calculated, and a 6-input, 2-output lookup table (LUT6_2) is used to simultaneously calculate the two compressed partial products with the smallest precision loss. The compressed partial product with the largest precision loss is calculated separately using a 6-input lookup table (LUT6). For compressed partial products with an input number exceeding the lookup table's input limit, and for unprocessed partial products, a partial carry-truncation method is used to calculate the product result. This invention can improve multiplier performance while reducing multiplier precision loss.

The present application discloses digital filtering using approximate summation of combinations of partial products. The digital filter and filtering method can employ truncation, internal rounding, and / or approximation in a summing circuit that combines a plurality of sets of bit products arranged according to bit weights. An illustrative digital filter includes a summing circuit coupled to a plurality of partial product circuits. Each partial product circuit is configured to combine bits of a filter coefficient with bits of a corresponding signal sample to produce a set of partial products. The summing circuit uses a CSA tree to produce a filter output that combines the partial products from the plurality of partial product circuits into bits of two addends. The CSA tree has addends for a plurality of channels, each associated with a corresponding bit weight. The adder in one or more of the channels associated with the least significant bit of the filter output is an approximate adder that sacrifices accuracy for simpler implementation. In the receiver shown, the filter is coupled to a decision element that derives a symbol decision sequence.