Split-path fused multiply-accumulate operation using first and second sub-operations

Abstract

A microprocessor executes a fused multiply-accumulate operation of a form +-A * B +- C by dividing the operation in first and second suboperations. The first suboperation selectively accumulates the partial products of A and B with or without C and generates an intermediate result vector and a plurality of calculation control indicators. The calculation control indicators indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The intermediate result vector, in combination with the plurality of calculation control indicators, provides sufficient information to generate a result indistinguishable from an infinitely precise calculation of the compound arithmetic operation whose result is reduced in significance to a target data size.

Description

[0001] related application [0002] This application claims the U.S. Patent No. 62 / 020,246 provisional application "Non-Atomic Split-Path Fused Multiply-Accumulate with Rounding cache" filed on July 2, 2014 and the U.S. Patent No. 62 / 020,246 filed on June 10, 2015 Priority of Provisional Application No. 62 / 173,808 "Non-Atomic Temporally-Split Fused Multiply-Accumulate Apparatus and Operation Using a Calculation Control Indicator Cache and Providing a Split-Path Heuristic for Performing a Fused FMA Operation and Generating a Standard Format Intermediate Result". The entirety of these priorities are incorporated into this application by reference. [0003] This application is also related to the following applications filed concurrently with this application: U.S. Application No. 14 / 748,870, entitled "Temporally SplitFused Multiply-Accumulate Operation"; U.S. Application No. 14 / 748,924, entitled "Calculation Control Indicator Cache"; U.S. Application No. 14 / 748,956, entitled "Cal...

AI Technical Summary

Problems solved by technology

However, this approach has many disadvantages

[0014] First, FMA hardware is more expensive and complex to set up than using separate add and multiply functional units

Second, when performing simple addition or multiplication operations, using FMA hardware has higher latency and generally consumes more power than using separate addition and multiplication functional units

This time delay is sometimes modeled as a delay due to "long wires"

Therefore, in order to reduce the impact of the indivisible FMA operation on instruction-level parallel processing, the additional functional blocks can provide quite limited improvement after considering the required chip size, power consumption and arithmetic operation delay.

[0016] Therefore, the best proposals and implementations will usually (but not always) provide correct results (corresponding to IEEE rounding and other specifications), sometimes provide higher instruction output (throughput), but obviously require additional Hardware circuitry increases setup cost and increases power consumption to perform simple multiply and add operations on complex FMA hardware

[0017] What modern FMA designs were intended to achieve has not yet been fully achieved

Images