59results about "Runtime instruction translation" patented technology

A method for updating a container in a container-based vehicle system includes: executing an application included in the container, the application configured to access at least one item included in the container to operate a service related to a vehicle, receiving, from a server, a container image of an update target based on determining an update of the container being needed, the container image including a set of items, storing the received container image of the update target in a system registry, generating a new container by combining a user data item that is generated in the container and the stored container image of the update target, and updating the container by using a container management table on the new container while executing the application. The application reflects the updated container based on items included in the updated container.

One embodiment provides a graphics processor comprising an instruction cache to store an instruction and a compute block configured to perform multiply-accumulate operations in response to execution of the instruction. The compute block includes a scheduler to schedule a plurality of threads for execution of the instruction and multiply-accumulate circuitry configured to execute the instruction via the plurality of threads, wherein the multiply-accumulate circuitry includes a plurality of functional units configured to process, in parallel via the plurality of threads, a corresponding plurality of matrix elements to multiply a first matrix and a second matrix, and to multiply the first matrix and the second matrix includes to multiply data elements in a row of the first matrix by corresponding data elements in a column of the second matrix to generate a plurality of products.

The application relates to a kind of automation control devices of test and control station based on editable script, including at least one script file, for defining the test and control task flow of test and control station in editable text form;Script analysis execution module is used for parsing script file and mapping to internal function for calling;At least one device control command execution module is used for controlling the test and control equipment in test and control station;Script server, by calling script analysis execution module and device control command execution module, carries out parallel control to test and control station according to preset execution mode multiple script tasks.The application also relates to a kind of automation control method of test and control station based on editable script.Can effectively improve the standardization, flexibility and scalability of spaceflight test and control station, to execute the tracking and control task of various spacecrafts with low cost flexibility, high efficiency.

A Multi-Purpose Dynamic Simulation and run-time Control platform includes a virtual process environment coupled to a physical process environment, where components / nodes of the virtual and physical process environments cooperate to dynamically perform run-time process control of an industrial process plant and / or simulations thereof. Virtual components may include virtual run-time nodes and / or simulated nodes. The MPDSC includes an I / O Switch which delivers I / O data between virtual and / or physical nodes, e.g., by using publish / subscribe mechanisms, thereby virtualizing physical I / O process data delivery. Nodes serviced by the I / O Switch may include respective component behavior modules that are unaware as to whether or not they are being utilized on a virtual or physical node. Simulations may be performed in real-time and even in conjunction with run-time operations of the plant, and / or simulations may be manipulated as desired (speed, values, administration, etc.). The platform simultaneously supports simulation and run-time operations and interactions / intersections therebetween.

Apparatuses, methods, and systems are disclosed for use-limited instructions cryptographically linked with data. A method includes reading a handle including a ciphertext of a key, an authentication tag, and additional authentication data; performing a first verification of the authentication tag against the ciphertext of the key and the additional authentication data to determine whether there is any modification to the ciphertext of the key or the additional authentication data; performing a second check on the current request against one or more restrictions specified by the additional authentication data; and decrypting the ciphertext of the key to regenerate the key wherein the key is regenerated only if the first check indicates no modification to the ciphertext of the key or additional authentication data and the second check indicates that the one or more restrictions are not violated by the current request.

The invention discloses an instruction generation method and device, equipment, a storage medium and a program product, and relates to the technical field of machine learning. The method comprises the following steps: acquiring a first natural language instruction, wherein the first natural language instruction is used for indicating to realize a first function through computer equipment; obtaining a function vector set, wherein the function vector set comprises function feature vectors corresponding to a plurality of performance functions respectively; recalling at least one candidate performance function meeting a correlation degree requirement from a function vector set based on a vector correlation degree between a first feature vector corresponding to the first natural language instruction and a plurality of function feature vectors; based on the first natural language instruction and the at least one candidate performance function, an equipment driving instruction is constructed, and the content of the equipment driving instruction comprises a target performance function in the at least one candidate performance function and a first parameter of the target performance function when the first function is achieved, the first parameter is a function parameter obtained based on analysis of the first natural language instruction.

Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

This invention proposes a micro-operation decomposition module, processor, and electronic device. A numbering update unit provides the current micro-operation number to an element quantity counting unit and an execution module. The element quantity counting unit determines the current micro-operation element quantity based on the current micro-operation number and the reference information corresponding to the target vector instruction. The execution module executes the corresponding micro-operation based on the current micro-operation number, the current micro-operation element quantity, and decoding information. Performing micro-operations before instruction execution avoids excessive pipeline delays caused by micro-operations, enabling rapid response to instruction changes, accurate completion of micro-operations, and improved instruction processing efficiency, thus meeting the demands of high-performance computing.

Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

A binary instruction translation method includes: receiving and decoding an instruction stream including instructions and pieces of instruction-information respectively corresponding to the instructions; determining whether the instructions in the instruction stream are translatable into a vector instruction stream based on the pieces of instruction-information; and based on a result of the determining, translate the instructions of the instruction stream to a vector instruction stream, the translating including translating at least some of the instructions of the instruction stream to vector instructions in a vector-specific instruction set by replacing scalar instructions of a first instruction set architecture (ISA) with functionally equivalent vector instructions of a vector-specific ISA.

Aspects of the disclosure include configuring a hierarchy of instructions resulting in execution on a quantum circuit, where the hierarchy of instructions comprise physical device operations, micro operations, qubit operations, and instruction set architecture (ISA) operations. Aspects include translating from the ISA operations to the qubit operations, from the qubit operations to the micro operations, and from the micro operations to the physical device operations. Aspects include causing execution of the physical device operations on the quantum circuit.

Techniques are disclosed involving fusing instruction pairs and executing corresponding fused instruction operations. A processor includes fusion detection circuitry to detect a pair of fetched instructions and fuse the instructions into a fused instruction operation, and execution circuitry to execute the fused instruction operation. In one embodiment, a first instruction is executable to perform an operation and a second instruction is executable to adjust a sign of a result of the operation. In another embodiment, the first instruction is executable to perform an operation and the second instruction is executable to find a maximum or minimum, as compared to a comparison operand, of a result of the operation. In another embodiment, the first instruction is executable to perform a vector operation and the second instruction is executable to read a first element of the vector result and overwrite one or more additional elements of the vector result.

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

The invention provides a micro-operation disassembling module, a processor and electronic equipment. A number updating unit provides a current micro-operation number for an element quantity counting unit and an execution module; an element quantity counting unit determines a current microoperation element quantity according to the current microoperation number and reference information corresponding to the target vector instruction; the execution module executes the corresponding micro-operation according to the current micro-operation number, the current micro-operation element quantity and the decoding information. According to the method, the micro-dismounting operation is performed before the instruction is executed, so that the situation that the pipeline delay is excessively increased due to the micro-dismounting operation is avoided, the instruction change is quickly responded, the micro-dismounting operation is accurately completed, the instruction processing efficiency is improved, and the high-performance calculation requirement can be met.

Systems and methods are disclosed for fusion with destructive instructions. For example, an integrated circuit (e.g., a processor) for executing instructions includes a fusion circuitry that is configured to detect a sequence of macro-ops stored in a processor pipeline of the processor core, the sequence of macro-ops including a first macro-op identifying a first register as a destination register followed by a second macro-op identifying the first register as both a source register and as a destination register, wherein one or more intervening macro-ops occur between the first macro-op and the second macro-op in the program order; determine a micro-op that is equivalent to the first macro-op followed by the second macro-op; and forward the micro-op to at least one of the one or more execution resource circuitries for execution. For example, the sequence of macro-ops may be detected in a vector dispatch stage of a processor pipeline.

The invention discloses a processor, a chip product, computer equipment and a tensor processing method, and relates to the technical field of processors. The processor comprises a tensor calculation engine and a target storage unit, wherein the tensor calculation engine comprises a tensor calculation unit and a first buffer area; the tensor calculation unit executes logical operation on the tensor data to obtain an operation result of a first sequence, and the operation result of the first sequence is in a first data format; the tensor calculation unit is also used for caching the operation result of the first sequence to the first buffer area; the tensor calculation unit is also used for converting the operation result of the first sequence cached in the first buffer area into an operation result of a second sequence according to a second data format; and storing the operation result of the second sorting to the target storage unit. In this way, inverse conversion does not need to be carried out after the tensor storage engine executes data format conversion, and the influence of the storage mode adopted by the operation result of the first sequence in the storage unit does not need to be considered.

The present application provides an instruction processing apparatus, an instruction execution method, a system on chip and a board card. The solution described in the present application may hide the heterogeneity of execution units by proposing a unified mixed-scale instruction, thereby improving programming efficiency and hardware utilization.

Aspects of the disclosure include configuring a hierarchy of instructions resulting in execution on a quantum circuit, where the hierarchy of instructions comprise physical device operations, micro operations, qubit operations, and instruction set architecture (ISA) operations. Aspects include translating from the ISA operations to the qubit operations, from the qubit operations to the micro operations, and from the micro operations to the physical device operations. Aspects include causing execution of the physical device operations on the quantum circuit.

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more of a plurality of heterogeneous processing elements, the instructions corresponding to a code segment to be processed by one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.

Systems, devices, computer-implemented methods, and tangible non-transitory computer readable media for performing multilayered generation and processing of computer instructions are provided. For example, a computing device may receive a request with instructions in a first computer language, parse the instructions in the first computer language, analyze the instructions in the first computer language in view of information describing structure of a first application, generate instructions in a second computer language different from the first computer language where the instructions in the second computer language are generated based on the instructions in the first computer language and the information describing structure of the first application, obtain a result from a second application where the result comprises information based on the instructions in the second computing language, and provide the result in response to the request comprising the instructions in the first computer language.

Systems, computer program products, and methods are described herein for mainframe resource utilization for batch cycle application integration. The invention generally involves extracting, organizing, and collating batch cycle processing data from various sources, executing data preparation steps, converting file formats, loading data into a designated storage location, generating a mainframe database table with coded date values for predefined batch run dates, and generating a batch job run library by scanning and replacing coded date values with respective date values for predefined batch run dates.

The present disclosure provides an instruction execution method and device, electronic equipment and storage medium, and relates to the technical field of computers. The method comprises: obtaining a CPU instruction set containing a plurality of central processing unit (CPU) instructions to be processed, and recording the instruction order of the CPU instructions in the CPU instruction set; integrating the CPU instructions in the CPU instruction set that meet a preset condition into memory instructions, while retaining the original CPU instructions, recording the integration order of the memory instructions, obtaining a memory instruction set, and the preset condition being that the CPU instructions meet the condition of being convertible into memory instructions; and executing the CPU instruction set and the memory instruction set in the CPU and the memory respectively according to the instruction order and the integration order. The present disclosure integrates part of the CPU instructions in the CPU instruction set into memory instructions to obtain a memory instruction set, and simultaneously executes the CPU instructions and the memory instructions according to the instruction order and the integration order, thereby improving the instruction execution efficiency.

The present invention relates to multi-core processor devices that use multi-threaded processing. Multi-core processors are provided that are configured to improve processing performance in certain computing scenarios. The multi-core processors include a plurality of processing cores that implement bucketed thread processing to execute multiple instruction threads in parallel while ensuring the effects of idle instructions or threads are minimized on the performance of the processor. The plurality of cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate cache coherency issues. The bucketed thread processing can minimize latency effects associated with the shared data cache. In some examples, the multi-core processor can also include a serial processor that is configured to execute single-threaded program code that can not produce satisfactory performance in a processing environment that employs bucketed thread processing.

An apparatus and method for performing integer based FP4 dot products. One embodiment of an apparatus comprises: one or more registers to store a plurality of source 4-bit floating-point data elements; decode circuitry to decode a 4-bit floating-point dot product instruction, the instruction having an opcode to indicate one or more 4-bit floating-point dot product operations to be performed and one or more fields indicate a plurality of pairs of the source 4-bit floating-point data elements on which to perform the one or more dot product operations; and execution circuitry to execute the 4-bit floating-point dot product instruction, the execution circuitry to convert the plurality of pairs of 4-bit floating-point data elements to a corresponding plurality of pairs of integer data elements to perform the dot product.

Embodiments of this application disclose an instruction translation method. The method includes: obtaining a return instruction of a function call instruction; obtaining a first address mapping result based on a second address indicated in the return instruction; storing the first address mapping result in a running stack space; and obtaining a first translation result of the return instruction, where the first translation result is a binary translation result of the return instruction, and the second translation result indicates to obtain, from a target location, an instruction indicated by the first address mapping result and execute the instruction. In this application, a running stack space of a source program is reused, thereby saving a storage space. In addition, an address of a return instruction does not need to be checked each time the return instruction is translated, thereby reducing overheads during translation and increasing program running efficiency.

The present disclosure provides a program processing method and device, equipment and storage medium, relates to the technical field of computers, in particular to running environment simulation technology and cloud service technology. The specific implementation scheme is: a slave component program obtains an application component call request of an application program and processes the application component call request, and generates a slave component call request; an instruction conversion engine obtains the slave component call request, converts the slave component call request into a host component call request; a host component program obtains the host component call request and processes the host component call request, and generates a first instruction execution request of a first operating system; and an operating system virtual program obtains the first instruction execution request, converts the first instruction execution request into a second instruction execution request of a second operating system supported by a second architecture instruction set and processes the second instruction execution request. According to the technology of the present disclosure, application program running based on a heterogeneous framework is realized.

The disclosure relates to systems, methods, and apparatus for heterogeneous computing. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more of a plurality of heterogeneous processing elements, the instructions corresponding to code fragments to be processed by the one or more of the plurality of heterogeneous processing elements, the instruction is a native instruction for at least one of one or more of the plurality of heterogeneous processing elements.

Systems, apparatuses, methods, and computer program products are disclosed for translating control instructions for a machine interface. An example method includes identifying a machine based on a machine identifier. The example method further includes selecting a machine-readable interface based on the machine identifier. The example method further includes generating control data comprising instructions to cause an executable action by the machine. The example method further includes causing execution of the control data by the machine. The example method may further include contacting an NFC sensor associated with the machine. The example method may further include scanning an indicia that is within a distance of the machine. The example method may further include generating request data indicating a user request to complete the executable action by the machine. The example method may further include generating the control data comprising instructions to navigate a user interface associated with the machine.

Embodiments of the present application provide a machine code instruction conversion method and device, electronic equipment and readable storage medium, and relate to the technical field of computers. The method comprises: obtaining a machine code instruction to be converted, wherein the machine code instruction can comprise an operation code, a first operand, a second operand, a third operand and an original immediate number; analyzing the machine code instruction to determine a target assembly instruction corresponding to the operation code and the second operand, register names corresponding to the first operand and the third operand respectively, and a target immediate number obtained after conversion based on the original immediate number; and obtaining an assembly code corresponding to the machine code instruction based on preset rule information combination of the obtained target assembly instruction, register names and target immediate number, which realizes convenient conversion of the machine code instruction into the assembly code, is conducive to further analysis of the assembly code by technical personnel, and effectively fills the technical gap of conversion of the machine code into the assembly code.