233results about "Runtime instruction translation" patented technology

The embodiment of the invention provides a cross-chip platform instruction conversion method, which comprises the following steps: collecting instruction set information of a source chip platform and a target chip platform, establishing an instruction feature analysis model, and calculating a semantic similarity matrix between instructions in a feature vector space by adopting a kernel function; training a multilayer graph attention neural network based on the semantic similarity matrix, mapping feature vectors of a source platform instruction and a target platform instruction to a shared embedding space, and performing iterative optimization on a mapping relation graph by applying a reinforcement learning method to obtain an instruction equivalent conversion rule; the instruction equivalent conversion rule is loaded in the instruction conversion engine, the input source platform instruction is decoded and analyzed, and a converted target platform instruction sequence is output to an instruction execution unit of a target chip platform; the resource overhead in the conversion process can be optimized, and the overall efficiency of the system is improved on the basis of ensuring the conversion correctness.

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

The invention discloses a spacecraft intelligent design method and system capable of autonomously learning, and belongs to the technical field of spacecraft design and simulation. The problems that in spacecraft design, natural language requirements are fuzzy and difficult to process, instruction generation is prone to ambiguity, linkage between simulation and design is not smooth, a design scheme lacks an effective iterative optimization mechanism, and traditional design is low in efficiency are solved. The method comprises the following steps: firstly, receiving a natural language demand, extracting key parameters to generate prompt words, inputting the prompt words into Design.AI, and generating a simulation instruction sequence; simulation is started through MCP Server conversion, if the result does not reach the standard, feedback correction is carried out, and iterative optimization is carried out. And repeating the steps until a design target is met, and generating a design report containing multiple items of content. Through natural language processing, real-time simulation, iterative optimization, knowledge accumulation and other technologies, the spacecraft design efficiency is greatly improved, the accuracy is enhanced, the threshold is lowered, and the flexibility is improved.

The embodiment of the invention provides a binary translation method, a binary translator, electronic equipment and a readable storage medium, and the method comprises the steps: calling a preset instruction if a current instruction is recognized as an indirect jump instruction; the instruction code of the preset instruction comprises a first operand and a second operand; the first operand points to the first register, and the second operand points to the second register; the target PC value is stored in the first register; the second register is used for storing a calculation result of the preset instruction; the preset instruction executes preset calculation logic to calculate a target index value corresponding to the target PC value in the hash table, and the target index value is written into a second register; the target index value is read from the second register, whether the target PC value hits the hash table or not is inquired through the target index value, and the next instruction is executed based on the inquiry result. According to the embodiment of the invention, the instruction translation number of the high-frequency instruction can be reduced, and the execution efficiency of the binary translator is improved.

The invention provides an in-memory computing AI accelerator design architecture based on an RISC-V architecture and a control method. The architecture comprises an RISC-V processor used for executing a general-purpose computing task and a control instruction; the in-memory computing accelerator is used for executing a computing task in an AI algorithm, is connected with the RISC-V processor and comprises a tensor processing unit and a vector processing unit; the in-memory computing accelerator further comprises a data rearrangement unit which is used for carrying out format conversion and rearrangement on the data before the data are transmitted to the tensor processing unit or the vector processing unit. And the data format management unit is used for defining and managing a unified data format in the in-memory computing accelerator. According to the invention, the calculation performance and the resource utilization rate of the AI algorithm can be improved, and meanwhile, the accuracy of data transmission and the parallelism of processing are ensured.

The embodiment of the invention discloses an instruction translation method and device, electronic equipment and a storage medium, and the method comprises the steps: receiving an instruction translation request, when the instruction translation request carries a target address of an original instruction, obtaining the target address in the instruction translation request, obtaining a first symbol table file, retrieving a target node in the tree data structure of the first symbol table file according to the target address, and reading symbol offset from the target node; retrieving a function number of the target address and a first line number of the original instruction from first symbol information of the first symbol table file according to the symbol offset; the first symbol dictionary is obtained according to the target address, the first function character of the original instruction is retrieved in the first symbol dictionary according to the function number, and the translation result of the original instruction is obtained based on the first function character and the first line number, so that the time complexity during instruction translation can be reduced, and the instruction translation efficiency is improved.

The invention discloses an automatic code vectorization optimization method and device and a medium, belongs to the technical field of high-performance computing, and aims at solving the problems that existing automatic code vectorization is inconvenient, the manual operation proportion is large, vectorization of irregular codes or codes with a load dependency relationship is difficult to support, and the vectorization efficiency is high. And improvement of calculation performance and reduction of energy consumption are not facilitated. The method comprises the steps of obtaining a scalar instruction diagram of a calculation task according to a calculation kernel of parallel calculation; performing protocol conversion processing on the scalar instruction diagram to obtain a protocol instruction diagram; according to the high-level organization structure of the instruction, grouping processing related to mapping vectors is carried out on the protocol instruction graph, and a grouping graph is obtained; based on the limited vector length of hardware, performing splitting matching processing on instruction vectors in the grouping graph to obtain a vector matching grouping graph; and executing configuration on each group of elements in the vector matching grouping graph to obtain a vector operation graph.

The present invention relates to a computer-implemented system for translating natural language instructions into precise input and output (I / O) commands. The innovative system integrates a computer vision module that captures and analyzes visual elements from a user interface with a high-performance language model that interprets the elements to generate contextually relevant action descriptions. The descriptions are refined by integrating specific screen coordinates, ensuring accuracy and precision in the resulting instructions. The refined instructions are then converted into actionable I / O commands, allowing intuitive interaction with the device through natural language input. The method significantly enhances human-computer interaction, especially for individuals with disabilities by enabling efficient control through natural language. It represents a significant advancement in artificial general intelligence by converting complex linguistic instructions into concrete system actions with broad potential applications across various technological fields.

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium, and the method comprises the steps: if a translated current instruction is a memory access instruction, querying whether a reusable target cache register exists in distributed cache registers; the memory access address of the translated memory access instruction is stored in the allocated cache register; the memory access address in the reusable target cache register is the same as the memory access address of the current instruction in high order; if the reusable target cache register exists, obtaining a target difference value; the target difference value is a difference value between a memory access address of the current instruction and a memory access address in the target cache register; and translating the current instruction into a target instruction according to the target difference value and the target cache register. According to the embodiment of the invention, the number of translated instructions can be reduced, the execution efficiency of the translator is improved, and the program running speed of the translator is improved.

Embodiments of the present disclosure provide a processor, an instruction processing method, and an electronic device including the processor. The processor includes a plurality of processor cores and an accelerator module, wherein each of the plurality of processor cores is configured to execute a first type of instruction; the accelerator module includes at least one accelerator engine configured to execute a second type of instruction different from the first type of instruction; the accelerator module is coupled with and shared by the plurality of processor cores, and each of the plurality of processor cores dispatches an object instruction belonging to the second type of instruction in an instruction stream processed by itself to the accelerator module for execution and receives an execution result message of the object instruction from the accelerator module. The processor can have higher accelerator module usage efficiency.

The invention discloses an instruction stream feature recognition-based instruction conversion memory access conflict optimization method, which comprises the following steps of: in a process of pre-executing an executable file in an ARM (Advanced RISC Machines) many-core system in a dynamic instruction conversion manner, determining shared memories among processes by adopting instruction stream analysis to form a first shared memory list, and on the basis, determining the memory access conflict among the processes; the executable file is loaded and executed again, the memory access type to-be-converted instruction with the memory address located in the first shared memory list is converted into an instruction sequence composed of a locking instruction sequence, a second ARM instruction sequence and an unlocking instruction sequence, and meanwhile conversion execution of the executable file is completed based on a cache consistency protocol. The memory access conflict of the x86 program on the ARM many-core system is obviously reduced, and powerful support is provided for realizing high-performance dynamic instruction conversion.

The invention relates to the field of programmable logic controller programming software, in particular to a method for converting a ladder diagram of a PLC into an instruction list, which comprises the following steps of: obtaining a mapped AOV diagram by adopting a mode of adding and deleting virtual nodes; generating a logic tree by adopting a series-parallel scanning method of dynamic priority; and after the logic tree structure is obtained, performing subsequent traversal on the logic tree according to the logic relationship described by the logic tree to generate an instruction table structure. Compared with the prior art, a complex ladder diagram is greatly simplified through a preprocessing mechanism, the scanning steps of continuous series connection or continuous parallel connection original parts can be reduced, unnecessary node scanning can be fully reduced through dynamic priority series-parallel connection scanning, and the scanning efficiency is greatly improved; in addition, the method can be widely applied to a complex ladder diagram program in the PLC, and the series-parallel scanning efficiency can be greatly improved.

A computing device receives an application start request for an application through a dispatching service. The computing device determines whether the application uses a first instruction set architecture (ISA) or a second ISA using the dispatching service. The computing device determines whether the application is compute-bound or non-compute-bound in response to determining that the application uses the second ISA. The computing device performs binary translation to convert instructions based on the second ISA from the application to instructions based on the first ISA in response to determining that the application is compute-bound. The computing device executes the instructions based on the first ISA on one or more cores supporting the first ISA.

Data flows and data processing modules are provided to fulfill the implementation of: contextualized data collection, scalable analytics, and machine learning operations quality assurance. These modules may be implemented as standalone components, and / or bundled as a group of coordinated microservices. The conversion of raw domain expertise and knowledge into data processors, analytics, and visualization modules for industry oriented Industrial Internet of Things (IIoT) solutions is streamlined.

Apparatus and method for signed and unsigned shift, round and saturate using different data element values. For example, one embodiment of an apparatus comprises a decoder to decode an instruction having fields for a first packed data source operand to provide a first source data element and a second source data element, a second packed data source operand or immediate to provide a first shift value and a second shift value corresponding to the first source data element and second source data element, respectively, and a packed data destination operand to indicate a first result value and a second result value corresponding to the first source data element and second source data element, and execution circuitry to execute the decoded instruction to: shift the first source data element by an amount based on the first shift value to generate a first shifted data element; shift the second source data element by an amount based on the second shift value to generate a second shifted data element; update a saturation indicator responsive to detecting a saturation condition resulting from the shift of the first and / or second source data elements; round and / or saturate the first and second shifted data elements in accordance with a specified rounding mode and the saturation indicator, respectively, to generate the first and second result data elements; and store the first result value and the second result value in a first data element location and a second data element location in a destination register.

Circuitry and methods for implementing one or more Keccak permutation instructions are described. In certain examples, a hardware processor (e.g., core) includes decoder circuitry to decode a first instruction into a decoded first instruction, the first instruction comprising identifiers of a first register to store a first word of Keccak state value, a second register to store a second word of Keccak state value and a third word of Keccak state value, and a third register to store a fourth word of Keccak state value and a fifth word of Keccak state value according to a SHA3 standard, and an opcode to indicate vector execution circuitry comprising a plurality of lanes is to use only a single lane of the plurality of lanes to perform a column parities operation of a theta step of a Keccak permutation according to the SHA3 standard to determine a computed parity value for an input of the first word of Keccak state value, the second word of Keccak state value, the third word of Keccak state value, the fourth word of Keccak state value, and the fifth word of Keccak state value, and store the computed parity value into an unused upper word of the first register; and the vector execution circuitry to execute the decoded first instruction according to the opcode.

There is provided an apparatus, method for data processing. The apparatus comprises post decode cracking circuitry responsive to receipt of decoded instructions from decode circuitry of a processing pipeline, to crack the decoded instructions into micro-operations to be processed by processing circuitry of the processing pipeline. The post decode cracking circuitry is responsive to receipt of a decoded instruction suitable for cracking into a plurality of micro-operations including at least one pair of micro-operations having a producer-consumer data dependency, to generate the plurality of micro-operations including a producer micro-operation and a consumer micro-operation, and to assign a transfer register to transfer data between the producer micro-operation and the consumer micro-operation.

Techniques for performing BF16 FMA in response to an instruction are described. In some examples, an instruction has fields for an opcode, an identification of location of a packed data source / destination operand (a first source), an identification of a location of a second packed data source operand, an identification of a location of a third packed data source operand, and an identification of location of a packed data source / destination operand, wherein the opcode is to indicate operand ordering and that execution circuitry is to, per data element position, perform a BF16 value fused multiply-accumulate operation using the first, second, and third source operands and store a result in a corresponding data element position of the source / destination operand.

The invention relates to a multivariate step read operation for accessing matrix operands. In one embodiment, a matrix processor includes a memory to store matrix operands and a strided read sequence, in which: the matrix operands are stored out of order in the memory; and the step read sequence includes a series of read operations that read the matrix operands from the memory in a correct order. The matrix processor further includes circuitry to: receive a first instruction to be executed by the matrix processor, where the first instruction to instruct the matrix processor to perform a first operation on a matrix operand; reading a matrix operand from a memory based on the stride read sequence; and executing the first instruction by performing a first operation on the matrix operand.

The present application relates to image processors and methods for processing images. A method of computing a warp result is disclosed that can include performing, for each target pixel in a set of target pixels, a warp computation process that includes receiving, by a first set of processing units in an array of processing units, a first weight and a second weight associated with the target pixel; receiving, by a second set of processing units in the array, values of neighboring source pixels associated with the target pixel; computing, by the second set, a warp result responsive to the values of the neighboring source pixels and the pair of weights; and providing the warp result to a memory module.

A method for updating a container in a container-based vehicle system includes: executing an application included in the container, the application configured to access at least one item included in the container to operate a service related to a vehicle, receiving, from a server, a container image of an update target based on determining an update of the container being needed, the container image including a set of items, storing the received container image of the update target in a system registry, generating a new container by combining a user data item that is generated in the container and the stored container image of the update target, and updating the container by using a container management table on the new container while executing the application. The application reflects the updated container based on items included in the updated container.

The embodiment of the invention discloses an SIMD (Single Instruction Multiple Data) instruction generation method, an SIMD instruction processing method and related equipment, which are used in the field of SIMD instruction generation in the field of chips. The method comprises the following steps: acquiring the length of each cyclic dimension of a first tensor calculation formula, and selecting information of a second SIMD instruction model matched with the first tensor calculation formula from information of multiple groups of first SIMD instruction models according to the length of each cyclic dimension of the first tensor calculation formula, and according to the length of the at least one cyclic dimension of the first tensor calculation formula and the second SIMD instruction model, generating a first SIMD instruction after conversion of the first tensor calculation formula. According to the method, the information of the second SIMD instruction model is selected from the information of the multiple groups of first SIMD instruction models according to the length of each cyclic dimension of the tensor calculation formula, and then the first SIMD instruction converted by the first tensor calculation formula is generated according to the second SIMD instruction model, so that the efficiency of the SIMD instruction generation process is greatly improved.

A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.

One embodiment provides a graphics processor comprising an instruction cache to store an instruction and a compute block configured to perform multiply-accumulate operations in response to execution of the instruction. The compute block includes a scheduler to schedule a plurality of threads for execution of the instruction and multiply-accumulate circuitry configured to execute the instruction via the plurality of threads, wherein the multiply-accumulate circuitry includes a plurality of functional units configured to process, in parallel via the plurality of threads, a corresponding plurality of matrix elements to multiply a first matrix and a second matrix, and to multiply the first matrix and the second matrix includes to multiply data elements in a row of the first matrix by corresponding data elements in a column of the second matrix to generate a plurality of products.

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.

The application relates to a kind of automation control devices of test and control station based on editable script, including at least one script file, for defining the test and control task flow of test and control station in editable text form;Script analysis execution module is used for parsing script file and mapping to internal function for calling;At least one device control command execution module is used for controlling the test and control equipment in test and control station;Script server, by calling script analysis execution module and device control command execution module, carries out parallel control to test and control station according to preset execution mode multiple script tasks.The application also relates to a kind of automation control method of test and control station based on editable script.Can effectively improve the standardization, flexibility and scalability of spaceflight test and control station, to execute the tracking and control task of various spacecrafts with low cost flexibility, high efficiency.

A Multi-Purpose Dynamic Simulation and run-time Control platform includes a virtual process environment coupled to a physical process environment, where components / nodes of the virtual and physical process environments cooperate to dynamically perform run-time process control of an industrial process plant and / or simulations thereof. Virtual components may include virtual run-time nodes and / or simulated nodes. The MPDSC includes an I / O Switch which delivers I / O data between virtual and / or physical nodes, e.g., by using publish / subscribe mechanisms, thereby virtualizing physical I / O process data delivery. Nodes serviced by the I / O Switch may include respective component behavior modules that are unaware as to whether or not they are being utilized on a virtual or physical node. Simulations may be performed in real-time and even in conjunction with run-time operations of the plant, and / or simulations may be manipulated as desired (speed, values, administration, etc.). The platform simultaneously supports simulation and run-time operations and interactions / intersections therebetween.

Systems, methods, and apparatuses relating to an instruction that allows a trusted execution environment to react to an asynchronous exit are described. In one embodiment, a hardware processor includes a register comprising a field, that when set, is to enable an architecturally protected execution environment for code in an architecturally protected enclave in memory, a decoder circuit to decode a single instruction comprising an opcode into a decoded instruction, the opcode to indicate an execution circuit is to invoke a handler to handle an asynchronous exit from execution of the code in the architecturally protected enclave and then resume execution of the code in the architecturally protected enclave from where the asynchronous exit occurred, and the execution circuit to respond to the decoded instruction as specified by the opcode.

The multi-purpose dynamic simulation and runtime control platform includes a virtual process environment coupled to a physical process environment, and components / nodes of the virtual and physical process environments cooperate to dynamically perform runtime process control of an industrial process plant and / or its simulation. The virtual components may include virtual runtime nodes and / or simulation nodes. The MPDSC includes an I / O switch that virtualizes physical I / O process data transfer, for example, by using a publish / subscribe mechanism to transfer I / O data between virtual nodes and / or physical nodes. The nodes served by the I / O switch may include corresponding component behavior modules that are unaware of whether they are utilized on a virtual or physical node. The simulation can be performed in real time and even in conjunction with the runtime operation of the plant, and / or the simulation can be operated as needed (speed, numerical values, management, etc.). The platform supports both simulation and runtime operations and the interactions / intersections between them.

Techniques for converting half-precision floating-point to 8-bit floating-point are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction having a first field to identify a first source single instruction, multiple data, SIMD, register, a second field to identify a second source SIMD register, and a third field to identify a destination SIMD register, the first source SIMD register to store a first plurality of half-precision floating-point data elements, the second source SIMD register to store a second plurality of half-precision floating-point data elements; and execution circuitry to perform operations corresponding to the single instruction, including to: convert the first plurality of half-precision floating-point data elements to a first plurality of 8-bit floating-point data elements; convert the second plurality of half-precision floating-point data elements to a second plurality of 8-bit floating-point data elements; and store the first and second pluralities of 8-bit floating-point data elements in corresponding data element positions of the destination SIMD register.