107results about "Runtime instruction translation" patented technology

The invention discloses a spacecraft intelligent design method and system capable of autonomously learning, and belongs to the technical field of spacecraft design and simulation. The problems that in spacecraft design, natural language requirements are fuzzy and difficult to process, instruction generation is prone to ambiguity, linkage between simulation and design is not smooth, a design scheme lacks an effective iterative optimization mechanism, and traditional design is low in efficiency are solved. The method comprises the following steps: firstly, receiving a natural language demand, extracting key parameters to generate prompt words, inputting the prompt words into Design.AI, and generating a simulation instruction sequence; simulation is started through MCP Server conversion, if the result does not reach the standard, feedback correction is carried out, and iterative optimization is carried out. And repeating the steps until a design target is met, and generating a design report containing multiple items of content. Through natural language processing, real-time simulation, iterative optimization, knowledge accumulation and other technologies, the spacecraft design efficiency is greatly improved, the accuracy is enhanced, the threshold is lowered, and the flexibility is improved.

Embodiments of the present disclosure provide a processor, an instruction processing method, and an electronic device including the processor. The processor includes a plurality of processor cores and an accelerator module, wherein each of the plurality of processor cores is configured to execute a first type of instruction; the accelerator module includes at least one accelerator engine configured to execute a second type of instruction different from the first type of instruction; the accelerator module is coupled with and shared by the plurality of processor cores, and each of the plurality of processor cores dispatches an object instruction belonging to the second type of instruction in an instruction stream processed by itself to the accelerator module for execution and receives an execution result message of the object instruction from the accelerator module. The processor can have higher accelerator module usage efficiency.

Apparatus and method for signed and unsigned shift, round and saturate using different data element values. For example, one embodiment of an apparatus comprises a decoder to decode an instruction having fields for a first packed data source operand to provide a first source data element and a second source data element, a second packed data source operand or immediate to provide a first shift value and a second shift value corresponding to the first source data element and second source data element, respectively, and a packed data destination operand to indicate a first result value and a second result value corresponding to the first source data element and second source data element, and execution circuitry to execute the decoded instruction to: shift the first source data element by an amount based on the first shift value to generate a first shifted data element; shift the second source data element by an amount based on the second shift value to generate a second shifted data element; update a saturation indicator responsive to detecting a saturation condition resulting from the shift of the first and / or second source data elements; round and / or saturate the first and second shifted data elements in accordance with a specified rounding mode and the saturation indicator, respectively, to generate the first and second result data elements; and store the first result value and the second result value in a first data element location and a second data element location in a destination register.

The present application relates to image processors and methods for processing images. A method of computing a warp result is disclosed that can include performing, for each target pixel in a set of target pixels, a warp computation process that includes receiving, by a first set of processing units in an array of processing units, a first weight and a second weight associated with the target pixel; receiving, by a second set of processing units in the array, values of neighboring source pixels associated with the target pixel; computing, by the second set, a warp result responsive to the values of the neighboring source pixels and the pair of weights; and providing the warp result to a memory module.

A method for updating a container in a container-based vehicle system includes: executing an application included in the container, the application configured to access at least one item included in the container to operate a service related to a vehicle, receiving, from a server, a container image of an update target based on determining an update of the container being needed, the container image including a set of items, storing the received container image of the update target in a system registry, generating a new container by combining a user data item that is generated in the container and the stored container image of the update target, and updating the container by using a container management table on the new container while executing the application. The application reflects the updated container based on items included in the updated container.

One embodiment provides a graphics processor comprising an instruction cache to store an instruction and a compute block configured to perform multiply-accumulate operations in response to execution of the instruction. The compute block includes a scheduler to schedule a plurality of threads for execution of the instruction and multiply-accumulate circuitry configured to execute the instruction via the plurality of threads, wherein the multiply-accumulate circuitry includes a plurality of functional units configured to process, in parallel via the plurality of threads, a corresponding plurality of matrix elements to multiply a first matrix and a second matrix, and to multiply the first matrix and the second matrix includes to multiply data elements in a row of the first matrix by corresponding data elements in a column of the second matrix to generate a plurality of products.

The application relates to a kind of automation control devices of test and control station based on editable script, including at least one script file, for defining the test and control task flow of test and control station in editable text form;Script analysis execution module is used for parsing script file and mapping to internal function for calling;At least one device control command execution module is used for controlling the test and control equipment in test and control station;Script server, by calling script analysis execution module and device control command execution module, carries out parallel control to test and control station according to preset execution mode multiple script tasks.The application also relates to a kind of automation control method of test and control station based on editable script.Can effectively improve the standardization, flexibility and scalability of spaceflight test and control station, to execute the tracking and control task of various spacecrafts with low cost flexibility, high efficiency.

A Multi-Purpose Dynamic Simulation and run-time Control platform includes a virtual process environment coupled to a physical process environment, where components / nodes of the virtual and physical process environments cooperate to dynamically perform run-time process control of an industrial process plant and / or simulations thereof. Virtual components may include virtual run-time nodes and / or simulated nodes. The MPDSC includes an I / O Switch which delivers I / O data between virtual and / or physical nodes, e.g., by using publish / subscribe mechanisms, thereby virtualizing physical I / O process data delivery. Nodes serviced by the I / O Switch may include respective component behavior modules that are unaware as to whether or not they are being utilized on a virtual or physical node. Simulations may be performed in real-time and even in conjunction with run-time operations of the plant, and / or simulations may be manipulated as desired (speed, values, administration, etc.). The platform simultaneously supports simulation and run-time operations and interactions / intersections therebetween.

Apparatuses, methods, and systems are disclosed for use-limited instructions cryptographically linked with data. A method includes reading a handle including a ciphertext of a key, an authentication tag, and additional authentication data; performing a first verification of the authentication tag against the ciphertext of the key and the additional authentication data to determine whether there is any modification to the ciphertext of the key or the additional authentication data; performing a second check on the current request against one or more restrictions specified by the additional authentication data; and decrypting the ciphertext of the key to regenerate the key wherein the key is regenerated only if the first check indicates no modification to the ciphertext of the key or additional authentication data and the second check indicates that the one or more restrictions are not violated by the current request.

The embodiment of the invention provides an automatic operation method, computing equipment and a storage medium. Wherein a natural language description instruction is obtained, the natural language description instruction relates to a target element in a target page and a target interaction operation, then a data object corresponding to the target page is determined, and prompt information is generated according to the natural language description instruction and element information of at least one interactive element in the data object. The prompt information can instruct the artificial intelligence model to recognize a target page element and a target interaction operation related to the natural language description instruction, query a data object to determine element information of the target page element, and generate a target language structured instruction in combination with the element information; and enabling the automatic engine to execute the target language structured instruction so as to execute the target interaction operation aiming at the target element in the target page. According to the technical scheme provided by the embodiment of the invention, the target language structured instruction development efficiency can be improved, so that the automatic operation efficiency for the page is improved.

The invention provides a ConfigMap format disorder processing method and device based on cloud edge collaboration, a medium and equipment. The method comprises the following steps of: increasing sub-commands corresponding to different processing ranges and different processing modes by utilizing the custom characteristic of a kubectl plug-in; wherein the processing range comprises format disordered contents in all ConfigMap resources and format disordered contents in ConfigMap resources with specified namespace and specified name; the processing mode comprises checking after the temporary format is repaired, repairing the format, and storing the repaired ConfigMap resource in a preset database; and when the processing demand of ConfigMap format disorder exists, according to the sub-command corresponding to the processing demand, processing the format disorder content in the ConfigMap resource in the corresponding processing range according to the corresponding processing mode. According to the invention, the readability requirement can be met.

The invention discloses dedicated fixed function hardware for efficient convolution. One embodiment provides a computing device to perform machine learning operations, the device comprising a decode unit to decode a single instruction into a decoded instruction to perform one or more machine learning operations, where the decoded instruction is a single instruction to perform one or more machine learning operations. The decode unit is to request a scheduler to schedule the one or more machine learning operations to one of the array of programmable computing units and the fixed function computing units based on parameters of the one or more machine learning operations.

A method of activating a new device in a vehicle based on a container includes: detecting the new device mounted in the vehicle using an interface implemented in the vehicle, identifying the detected new device, transmitting, to a server, (i) a request for a container for controlling an execution of the identified new device and (ii) information obtained by one or more sensors implemented in the vehicle, receiving, from the server, a container package including at least one container that is retrieved in the server in response to the request for the container, and controlling the execution of the new device by activating the at least one container.

The invention discloses an instruction generation method and device, equipment, a storage medium and a program product, and relates to the technical field of machine learning. The method comprises the following steps: acquiring a first natural language instruction, wherein the first natural language instruction is used for indicating to realize a first function through computer equipment; obtaining a function vector set, wherein the function vector set comprises function feature vectors corresponding to a plurality of performance functions respectively; recalling at least one candidate performance function meeting a correlation degree requirement from a function vector set based on a vector correlation degree between a first feature vector corresponding to the first natural language instruction and a plurality of function feature vectors; based on the first natural language instruction and the at least one candidate performance function, an equipment driving instruction is constructed, and the content of the equipment driving instruction comprises a target performance function in the at least one candidate performance function and a first parameter of the target performance function when the first function is achieved, the first parameter is a function parameter obtained based on analysis of the first natural language instruction.

Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

This invention proposes a micro-operation decomposition module, processor, and electronic device. A numbering update unit provides the current micro-operation number to an element quantity counting unit and an execution module. The element quantity counting unit determines the current micro-operation element quantity based on the current micro-operation number and the reference information corresponding to the target vector instruction. The execution module executes the corresponding micro-operation based on the current micro-operation number, the current micro-operation element quantity, and decoding information. Performing micro-operations before instruction execution avoids excessive pipeline delays caused by micro-operations, enabling rapid response to instruction changes, accurate completion of micro-operations, and improved instruction processing efficiency, thus meeting the demands of high-performance computing.

Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

A binary instruction translation method includes: receiving and decoding an instruction stream including instructions and pieces of instruction-information respectively corresponding to the instructions; determining whether the instructions in the instruction stream are translatable into a vector instruction stream based on the pieces of instruction-information; and based on a result of the determining, translate the instructions of the instruction stream to a vector instruction stream, the translating including translating at least some of the instructions of the instruction stream to vector instructions in a vector-specific instruction set by replacing scalar instructions of a first instruction set architecture (ISA) with functionally equivalent vector instructions of a vector-specific ISA.

This invention discloses a method, apparatus, device, and medium for dynamic library mapping execution in binary translation, comprising: translating and executing the instructions of an x86 executable program; determining whether it is a dynamic library function call instruction; if it is a dynamic library function call instruction, parsing the call instruction to obtain the called function; using the called function as a lookup index key to query a pre-established dynamic library mapping allocator to obtain a first value and a second value corresponding to the function in the RISC-V dynamic library; determining the starting address of the RISC-V dynamic library in memory, and using the first value as an offset value to calculate the absolute address of the function in memory; determining the parameter address of the function based on the second value; performing calculations on the function using the parameter address and the absolute address, and returning the calculation result. This reduces the system overhead during the translation process.

Aspects of the disclosure include configuring a hierarchy of instructions resulting in execution on a quantum circuit, where the hierarchy of instructions comprise physical device operations, micro operations, qubit operations, and instruction set architecture (ISA) operations. Aspects include translating from the ISA operations to the qubit operations, from the qubit operations to the micro operations, and from the micro operations to the physical device operations. Aspects include causing execution of the physical device operations on the quantum circuit.

Techniques are disclosed involving fusing instruction pairs and executing corresponding fused instruction operations. A processor includes fusion detection circuitry to detect a pair of fetched instructions and fuse the instructions into a fused instruction operation, and execution circuitry to execute the fused instruction operation. In one embodiment, a first instruction is executable to perform an operation and a second instruction is executable to adjust a sign of a result of the operation. In another embodiment, the first instruction is executable to perform an operation and the second instruction is executable to find a maximum or minimum, as compared to a comparison operand, of a result of the operation. In another embodiment, the first instruction is executable to perform a vector operation and the second instruction is executable to read a first element of the vector result and overwrite one or more additional elements of the vector result.

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

The invention provides a micro-operation disassembling module, a processor and electronic equipment. A number updating unit provides a current micro-operation number for an element quantity counting unit and an execution module; an element quantity counting unit determines a current microoperation element quantity according to the current microoperation number and reference information corresponding to the target vector instruction; the execution module executes the corresponding micro-operation according to the current micro-operation number, the current micro-operation element quantity and the decoding information. According to the method, the micro-dismounting operation is performed before the instruction is executed, so that the situation that the pipeline delay is excessively increased due to the micro-dismounting operation is avoided, the instruction change is quickly responded, the micro-dismounting operation is accurately completed, the instruction processing efficiency is improved, and the high-performance calculation requirement can be met.

Systems and methods are disclosed for fusion with destructive instructions. For example, an integrated circuit (e.g., a processor) for executing instructions includes a fusion circuitry that is configured to detect a sequence of macro-ops stored in a processor pipeline of the processor core, the sequence of macro-ops including a first macro-op identifying a first register as a destination register followed by a second macro-op identifying the first register as both a source register and as a destination register, wherein one or more intervening macro-ops occur between the first macro-op and the second macro-op in the program order; determine a micro-op that is equivalent to the first macro-op followed by the second macro-op; and forward the micro-op to at least one of the one or more execution resource circuitries for execution. For example, the sequence of macro-ops may be detected in a vector dispatch stage of a processor pipeline.

The invention relates to the technical field of human-computer interaction, in particular to a multi-modal user task intelligent decision and execution method based on a graphical interface, which comprises the following steps: acquiring user task input, acquiring a current equipment graphical interface and historical planning records, and constructing a multi-modal input set; the calling instruction Agent is used for calling the planning Agent to perform user task understanding and global planning on the basis of the multi-modal input set, outputting thinking content, global planning and a next plan, receiving the next plan from the planning Agent, translating an operation instruction into a control instruction and outputting the control instruction; executing the control instruction output by the instruction Agent, and feeding back an execution result; and according to the uncompleted state of the task, returning to the planning Agent to perform new global planning and next plan reasoning. And repeating task understanding, global planning and execution of the next plan until the global planning is completed. According to the method, the execution accuracy, continuity and robustness of the task on the actual graphical interface can be improved.

The invention discloses a processor, a chip product, computer equipment and a tensor processing method, and relates to the technical field of processors. The processor comprises a tensor calculation engine and a target storage unit, wherein the tensor calculation engine comprises a tensor calculation unit and a first buffer area; the tensor calculation unit executes logical operation on the tensor data to obtain an operation result of a first sequence, and the operation result of the first sequence is in a first data format; the tensor calculation unit is also used for caching the operation result of the first sequence to the first buffer area; the tensor calculation unit is also used for converting the operation result of the first sequence cached in the first buffer area into an operation result of a second sequence according to a second data format; and storing the operation result of the second sorting to the target storage unit. In this way, inverse conversion does not need to be carried out after the tensor storage engine executes data format conversion, and the influence of the storage mode adopted by the operation result of the first sequence in the storage unit does not need to be considered.

Systems, methods, and apparatuses relating to hardware for auto-predication of critical branches. In one embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to disable use of the predicted future outcome for a conditional critical branch comprising the branch instruction.

The present application provides an instruction processing apparatus, an instruction execution method, a system on chip and a board card. The solution described in the present application may hide the heterogeneity of execution units by proposing a unified mixed-scale instruction, thereby improving programming efficiency and hardware utilization.

In one embodiment, a processor includes a branch predictor to predict whether a branch instruction is to be taken and a branch target buffer (BTB) coupled to the branch predictor. The branch target buffer may be segmented into a first cache portion and a second cache portion, where, in response to an indication that the branch is to be taken, the BTB is to access an entry in one of the first cache portion and the second cache portion based at least in part on a type of the branch instruction, an occurrence frequency of the branch instruction, and spatial information regarding a distance between a target address of a target of the branch instruction and an address of the branch instruction. Other embodiments are described and claimed.