162results about "Runtime instruction translation" patented technology

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

The invention discloses a spacecraft intelligent design method and system capable of autonomously learning, and belongs to the technical field of spacecraft design and simulation. The problems that in spacecraft design, natural language requirements are fuzzy and difficult to process, instruction generation is prone to ambiguity, linkage between simulation and design is not smooth, a design scheme lacks an effective iterative optimization mechanism, and traditional design is low in efficiency are solved. The method comprises the following steps: firstly, receiving a natural language demand, extracting key parameters to generate prompt words, inputting the prompt words into Design.AI, and generating a simulation instruction sequence; simulation is started through MCP Server conversion, if the result does not reach the standard, feedback correction is carried out, and iterative optimization is carried out. And repeating the steps until a design target is met, and generating a design report containing multiple items of content. Through natural language processing, real-time simulation, iterative optimization, knowledge accumulation and other technologies, the spacecraft design efficiency is greatly improved, the accuracy is enhanced, the threshold is lowered, and the flexibility is improved.

The embodiment of the invention discloses an instruction translation method and device, electronic equipment and a storage medium, and the method comprises the steps: receiving an instruction translation request, when the instruction translation request carries a target address of an original instruction, obtaining the target address in the instruction translation request, obtaining a first symbol table file, retrieving a target node in the tree data structure of the first symbol table file according to the target address, and reading symbol offset from the target node; retrieving a function number of the target address and a first line number of the original instruction from first symbol information of the first symbol table file according to the symbol offset; the first symbol dictionary is obtained according to the target address, the first function character of the original instruction is retrieved in the first symbol dictionary according to the function number, and the translation result of the original instruction is obtained based on the first function character and the first line number, so that the time complexity during instruction translation can be reduced, and the instruction translation efficiency is improved.

The present invention relates to a computer-implemented system for translating natural language instructions into precise input and output (I / O) commands. The innovative system integrates a computer vision module that captures and analyzes visual elements from a user interface with a high-performance language model that interprets the elements to generate contextually relevant action descriptions. The descriptions are refined by integrating specific screen coordinates, ensuring accuracy and precision in the resulting instructions. The refined instructions are then converted into actionable I / O commands, allowing intuitive interaction with the device through natural language input. The method significantly enhances human-computer interaction, especially for individuals with disabilities by enabling efficient control through natural language. It represents a significant advancement in artificial general intelligence by converting complex linguistic instructions into concrete system actions with broad potential applications across various technological fields.

Embodiments of the present disclosure provide a processor, an instruction processing method, and an electronic device including the processor. The processor includes a plurality of processor cores and an accelerator module, wherein each of the plurality of processor cores is configured to execute a first type of instruction; the accelerator module includes at least one accelerator engine configured to execute a second type of instruction different from the first type of instruction; the accelerator module is coupled with and shared by the plurality of processor cores, and each of the plurality of processor cores dispatches an object instruction belonging to the second type of instruction in an instruction stream processed by itself to the accelerator module for execution and receives an execution result message of the object instruction from the accelerator module. The processor can have higher accelerator module usage efficiency.

The invention discloses an instruction stream feature recognition-based instruction conversion memory access conflict optimization method, which comprises the following steps of: in a process of pre-executing an executable file in an ARM (Advanced RISC Machines) many-core system in a dynamic instruction conversion manner, determining shared memories among processes by adopting instruction stream analysis to form a first shared memory list, and on the basis, determining the memory access conflict among the processes; the executable file is loaded and executed again, the memory access type to-be-converted instruction with the memory address located in the first shared memory list is converted into an instruction sequence composed of a locking instruction sequence, a second ARM instruction sequence and an unlocking instruction sequence, and meanwhile conversion execution of the executable file is completed based on a cache consistency protocol. The memory access conflict of the x86 program on the ARM many-core system is obviously reduced, and powerful support is provided for realizing high-performance dynamic instruction conversion.

Data flows and data processing modules are provided to fulfill the implementation of: contextualized data collection, scalable analytics, and machine learning operations quality assurance. These modules may be implemented as standalone components, and / or bundled as a group of coordinated microservices. The conversion of raw domain expertise and knowledge into data processors, analytics, and visualization modules for industry oriented Industrial Internet of Things (IIoT) solutions is streamlined.

Apparatus and method for signed and unsigned shift, round and saturate using different data element values. For example, one embodiment of an apparatus comprises a decoder to decode an instruction having fields for a first packed data source operand to provide a first source data element and a second source data element, a second packed data source operand or immediate to provide a first shift value and a second shift value corresponding to the first source data element and second source data element, respectively, and a packed data destination operand to indicate a first result value and a second result value corresponding to the first source data element and second source data element, and execution circuitry to execute the decoded instruction to: shift the first source data element by an amount based on the first shift value to generate a first shifted data element; shift the second source data element by an amount based on the second shift value to generate a second shifted data element; update a saturation indicator responsive to detecting a saturation condition resulting from the shift of the first and / or second source data elements; round and / or saturate the first and second shifted data elements in accordance with a specified rounding mode and the saturation indicator, respectively, to generate the first and second result data elements; and store the first result value and the second result value in a first data element location and a second data element location in a destination register.

The invention relates to a multivariate step read operation for accessing matrix operands. In one embodiment, a matrix processor includes a memory to store matrix operands and a strided read sequence, in which: the matrix operands are stored out of order in the memory; and the step read sequence includes a series of read operations that read the matrix operands from the memory in a correct order. The matrix processor further includes circuitry to: receive a first instruction to be executed by the matrix processor, where the first instruction to instruct the matrix processor to perform a first operation on a matrix operand; reading a matrix operand from a memory based on the stride read sequence; and executing the first instruction by performing a first operation on the matrix operand.

The present application relates to image processors and methods for processing images. A method of computing a warp result is disclosed that can include performing, for each target pixel in a set of target pixels, a warp computation process that includes receiving, by a first set of processing units in an array of processing units, a first weight and a second weight associated with the target pixel; receiving, by a second set of processing units in the array, values of neighboring source pixels associated with the target pixel; computing, by the second set, a warp result responsive to the values of the neighboring source pixels and the pair of weights; and providing the warp result to a memory module.

A method for updating a container in a container-based vehicle system includes: executing an application included in the container, the application configured to access at least one item included in the container to operate a service related to a vehicle, receiving, from a server, a container image of an update target based on determining an update of the container being needed, the container image including a set of items, storing the received container image of the update target in a system registry, generating a new container by combining a user data item that is generated in the container and the stored container image of the update target, and updating the container by using a container management table on the new container while executing the application. The application reflects the updated container based on items included in the updated container.

One embodiment provides a graphics processor comprising an instruction cache to store an instruction and a compute block configured to perform multiply-accumulate operations in response to execution of the instruction. The compute block includes a scheduler to schedule a plurality of threads for execution of the instruction and multiply-accumulate circuitry configured to execute the instruction via the plurality of threads, wherein the multiply-accumulate circuitry includes a plurality of functional units configured to process, in parallel via the plurality of threads, a corresponding plurality of matrix elements to multiply a first matrix and a second matrix, and to multiply the first matrix and the second matrix includes to multiply data elements in a row of the first matrix by corresponding data elements in a column of the second matrix to generate a plurality of products.

The application relates to a kind of automation control devices of test and control station based on editable script, including at least one script file, for defining the test and control task flow of test and control station in editable text form;Script analysis execution module is used for parsing script file and mapping to internal function for calling;At least one device control command execution module is used for controlling the test and control equipment in test and control station;Script server, by calling script analysis execution module and device control command execution module, carries out parallel control to test and control station according to preset execution mode multiple script tasks.The application also relates to a kind of automation control method of test and control station based on editable script.Can effectively improve the standardization, flexibility and scalability of spaceflight test and control station, to execute the tracking and control task of various spacecrafts with low cost flexibility, high efficiency.

A Multi-Purpose Dynamic Simulation and run-time Control platform includes a virtual process environment coupled to a physical process environment, where components / nodes of the virtual and physical process environments cooperate to dynamically perform run-time process control of an industrial process plant and / or simulations thereof. Virtual components may include virtual run-time nodes and / or simulated nodes. The MPDSC includes an I / O Switch which delivers I / O data between virtual and / or physical nodes, e.g., by using publish / subscribe mechanisms, thereby virtualizing physical I / O process data delivery. Nodes serviced by the I / O Switch may include respective component behavior modules that are unaware as to whether or not they are being utilized on a virtual or physical node. Simulations may be performed in real-time and even in conjunction with run-time operations of the plant, and / or simulations may be manipulated as desired (speed, values, administration, etc.). The platform simultaneously supports simulation and run-time operations and interactions / intersections therebetween.

The multi-purpose dynamic simulation and runtime control platform includes a virtual process environment coupled to a physical process environment, and components / nodes of the virtual and physical process environments cooperate to dynamically perform runtime process control of an industrial process plant and / or its simulation. The virtual components may include virtual runtime nodes and / or simulation nodes. The MPDSC includes an I / O switch that virtualizes physical I / O process data transfer, for example, by using a publish / subscribe mechanism to transfer I / O data between virtual nodes and / or physical nodes. The nodes served by the I / O switch may include corresponding component behavior modules that are unaware of whether they are utilized on a virtual or physical node. The simulation can be performed in real time and even in conjunction with the runtime operation of the plant, and / or the simulation can be operated as needed (speed, numerical values, management, etc.). The platform supports both simulation and runtime operations and the interactions / intersections between them.

Techniques for converting half-precision floating-point to 8-bit floating-point are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction having a first field to identify a first source single instruction, multiple data, SIMD, register, a second field to identify a second source SIMD register, and a third field to identify a destination SIMD register, the first source SIMD register to store a first plurality of half-precision floating-point data elements, the second source SIMD register to store a second plurality of half-precision floating-point data elements; and execution circuitry to perform operations corresponding to the single instruction, including to: convert the first plurality of half-precision floating-point data elements to a first plurality of 8-bit floating-point data elements; convert the second plurality of half-precision floating-point data elements to a second plurality of 8-bit floating-point data elements; and store the first and second pluralities of 8-bit floating-point data elements in corresponding data element positions of the destination SIMD register.

Apparatuses, methods, and systems are disclosed for use-limited instructions cryptographically linked with data. A method includes reading a handle including a ciphertext of a key, an authentication tag, and additional authentication data; performing a first verification of the authentication tag against the ciphertext of the key and the additional authentication data to determine whether there is any modification to the ciphertext of the key or the additional authentication data; performing a second check on the current request against one or more restrictions specified by the additional authentication data; and decrypting the ciphertext of the key to regenerate the key wherein the key is regenerated only if the first check indicates no modification to the ciphertext of the key or additional authentication data and the second check indicates that the one or more restrictions are not violated by the current request.

The embodiment of the invention provides an automatic operation method, computing equipment and a storage medium. Wherein a natural language description instruction is obtained, the natural language description instruction relates to a target element in a target page and a target interaction operation, then a data object corresponding to the target page is determined, and prompt information is generated according to the natural language description instruction and element information of at least one interactive element in the data object. The prompt information can instruct the artificial intelligence model to recognize a target page element and a target interaction operation related to the natural language description instruction, query a data object to determine element information of the target page element, and generate a target language structured instruction in combination with the element information; and enabling the automatic engine to execute the target language structured instruction so as to execute the target interaction operation aiming at the target element in the target page. According to the technical scheme provided by the embodiment of the invention, the target language structured instruction development efficiency can be improved, so that the automatic operation efficiency for the page is improved.

To provide simulation for actual process control by using virtualized elements.SOLUTION: Through a virtual node of a control system, a runtime behavior of physical elements which can be installed to a plant is reflected. The reflection includes a process for acquiring a first data published by an I / O by a virtual pair through subscription to publish a second data subscribed by the I / O. The reflection occurs while the I / O carries out, during its plant operation, controls processes by routing I / O data among run time nodes through subscription and publication. The run time node includes a controller and a device included in a control loop of the control system, and switches over the virtual pair to its execution as a virtual execution node of the control system operating in association with the I / O from execution as the virtual pair in order to carry out process control during the plant operation.SELECTED DRAWING: Figure 1

The invention provides a ConfigMap format disorder processing method and device based on cloud edge collaboration, a medium and equipment. The method comprises the following steps of: increasing sub-commands corresponding to different processing ranges and different processing modes by utilizing the custom characteristic of a kubectl plug-in; wherein the processing range comprises format disordered contents in all ConfigMap resources and format disordered contents in ConfigMap resources with specified namespace and specified name; the processing mode comprises checking after the temporary format is repaired, repairing the format, and storing the repaired ConfigMap resource in a preset database; and when the processing demand of ConfigMap format disorder exists, according to the sub-command corresponding to the processing demand, processing the format disorder content in the ConfigMap resource in the corresponding processing range according to the corresponding processing mode. According to the invention, the readability requirement can be met.

Techniques for register renaming caching are described. In an embodiment, an apparatus includes a register renaming cache, front-end circuitry, lookup circuitry, and execution circuitry. The register renaming cache is to store register renaming information associated with an instruction trace. The register renaming information is to be learned from a first execution of the instruction trace and is to be used to perform register renaming in connection with a second execution of the instruction trace. The front-end circuitry is to provide, based on the instruction trace, operations for execution. The lookup circuitry to look in the register renaming cache for entries corresponding to the operations. The execution circuitry is to execute the instruction trace.

The invention discloses dedicated fixed function hardware for efficient convolution. One embodiment provides a computing device to perform machine learning operations, the device comprising a decode unit to decode a single instruction into a decoded instruction to perform one or more machine learning operations, where the decoded instruction is a single instruction to perform one or more machine learning operations. The decode unit is to request a scheduler to schedule the one or more machine learning operations to one of the array of programmable computing units and the fixed function computing units based on parameters of the one or more machine learning operations.

A method of activating a new device in a vehicle based on a container includes: detecting the new device mounted in the vehicle using an interface implemented in the vehicle, identifying the detected new device, transmitting, to a server, (i) a request for a container for controlling an execution of the identified new device and (ii) information obtained by one or more sensors implemented in the vehicle, receiving, from the server, a container package including at least one container that is retrieved in the server in response to the request for the container, and controlling the execution of the new device by activating the at least one container.

Techniques for converting FP16 to BF8 using bias are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source / destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source / destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source / destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source / destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source / destination operand.

The invention discloses an instruction generation method and device, equipment, a storage medium and a program product, and relates to the technical field of machine learning. The method comprises the following steps: acquiring a first natural language instruction, wherein the first natural language instruction is used for indicating to realize a first function through computer equipment; obtaining a function vector set, wherein the function vector set comprises function feature vectors corresponding to a plurality of performance functions respectively; recalling at least one candidate performance function meeting a correlation degree requirement from a function vector set based on a vector correlation degree between a first feature vector corresponding to the first natural language instruction and a plurality of function feature vectors; based on the first natural language instruction and the at least one candidate performance function, an equipment driving instruction is constructed, and the content of the equipment driving instruction comprises a target performance function in the at least one candidate performance function and a first parameter of the target performance function when the first function is achieved, the first parameter is a function parameter obtained based on analysis of the first natural language instruction.

In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.

Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

This invention proposes a micro-operation decomposition module, processor, and electronic device. A numbering update unit provides the current micro-operation number to an element quantity counting unit and an execution module. The element quantity counting unit determines the current micro-operation element quantity based on the current micro-operation number and the reference information corresponding to the target vector instruction. The execution module executes the corresponding micro-operation based on the current micro-operation number, the current micro-operation element quantity, and decoding information. Performing micro-operations before instruction execution avoids excessive pipeline delays caused by micro-operations, enabling rapid response to instruction changes, accurate completion of micro-operations, and improved instruction processing efficiency, thus meeting the demands of high-performance computing.

Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

A binary instruction translation method includes: receiving and decoding an instruction stream including instructions and pieces of instruction-information respectively corresponding to the instructions; determining whether the instructions in the instruction stream are translatable into a vector instruction stream based on the pieces of instruction-information; and based on a result of the determining, translate the instructions of the instruction stream to a vector instruction stream, the translating including translating at least some of the instructions of the instruction stream to vector instructions in a vector-specific instruction set by replacing scalar instructions of a first instruction set architecture (ISA) with functionally equivalent vector instructions of a vector-specific ISA.