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86results about "Binary to binary" patented technology

Dynamic binary translation optimization method and system based on regional granularity

The invention provides a dynamic binary translation optimization method and system based on regional granularity. The method comprises the following steps: S1, initializing a program entry; s2, acquiring and analyzing an instruction; s3, performing cache query; s4, hot spot judgment; s5, performing interpretive execution; s6, initiating a compiling request; s7, compiling mode selection; s8, compiling and caching the code blocks; s9, skipping to a local code for execution; and S10, returning to the main cycle. According to the invention, the technical problems of limited optimization space, high context switching overhead and high code expansion rate are solved.
Owner:江淮前沿技术协同创新中心

Systems and methods for dynamic mapping and rerouting of a non-optimized binary to an optimized binary

Systems, methods, and devices are provided for dynamically mapping and rerouting a non-optimized binary to an optimized binary. Embodiments identify a position-independent portion within a non-optimized binary and receive metadata associated with an optimized binary. Further, embodiments identify a location identifier within the optimized binary from the metadata and generate a delta value between the position-independent portion and the location identifier. Embodiments also update the position-independent portion with the delta value.
Owner:MICROSOFT TECHNOLOGY LICENSING LLC

Code processing method and apparatus, and storage medium

This application discloses code processing methods, apparatuses, and storage media. An example method includes: obtaining a first code in low-level language and applicable to a source platform; decompiling the obtained first code to obtain an intermediate representation (IR); and then compiling the IR into a second code in low-level language and applicable to a first target platform, where the source platform and the target platform have different instruction sets.
Owner:HUAWEI TECH CO LTD

GPU architecture conversion method and device

The invention relates to the technical field of data processing, in particular to a GPU architecture conversion method and device. The method comprises the steps that assembly code input is received, ISA is analyzed into lexical units containing instruction elements according to input content, then detection of grammar rules and semantic logic is conducted on the lexical units based on grammar standards, and instruction objects carrying complete instruction attributes are generated; converting the instruction object into a corresponding LLVM function according to the attribute of the instruction object, generating an initial intermediate representation code, and finally compiling the optimized intermediate representation code into an executable machine code according to the target GPU hardware type. Through the embodiment of the invention, efficient conversion from the GPU assembly code to the multi-architecture machine code is realized, and the problem of performance loss caused by inaccurate grammar detection and insufficient optimization in traditional GPU development can be solved.
Owner:海光信息技术(成都)有限公司

Compiler for generating reconfigurable executable programs

The invention discloses a compiler for generating reconfigurable executable programs, and particularly discloses apparatuses, systems, and techniques for executing a compiler to generate one or more executable programs that can be configured to be executed by one or more of a plurality of different processor architectures. In at least one embodiment, a compiler generates one or more executable programs based at least in part on the original uncompiled executable programs, which may be configured to be executed by one or more of a plurality of different processor architectures.
Owner:NVIDIA CORP

Translation program, translation device, and translation method

The translation program causes, as a receiving unit (13), a PLC program development environment (10) that translates a first source code (21), which is described in a first language, of a program to be executed in order to control a device to be controlled by a PLC (30) into a second source code (22), which is described in a second language, and causes a translation unit (12) to function, said receiving unit (13) receiving a specification of a monitoring variable. The translation unit (12) translates the first source code (21) into the second source code (22). A translation unit (12) converts a code relating to a variable of a value stored in a shared memory between a PLC (30) and a device to be controlled in a first source code (21) to a code that refers to the shared memory when the variable is a monitoring variable, and converts the code to a code that refers to a non-shared memory when the variable is different from the monitoring variable.
Owner:MITSUBISHI ELECTRIC CORP

Cross-ISA extension program translation method based on binary rewriting

The invention discloses a cross-ISA (Industrial Standard Architecture) extension program translation method based on binary rewriting, which comprises the following steps of: 1) naming an instruction set ISA of a program to be translated as an original ISA, and naming an instruction set ISA on target hardware for running original ISA extension as a target ISA; 2) performing comparative analysis on a binary file corresponding to the original ISA extension compilation and a binary file corresponding to the target ISA extension compilation to obtain an instruction needing to be translated relative to the target ISA extension in the original ISA extension, and segmenting the instruction into a plurality of program basic blocks needing to be translated; 3) allocating a jump instruction and an address space for translating and storing translated codes to each program basic block; (4) distributing the program basic blocks into the corresponding address spaces through a jump instruction to carry out static binary translation, and generating a static file; and (5) distributing a loading address for the static file by utilizing a loader according to the address distribution information in the static file, and loading the static file to a corresponding position.
Owner:INST OF SOFTWARE - CHINESE ACAD OF SCI

Multi-code transformation method and apparatus for binary obfuscation

The objective of the present invention is to prevent reverse engineering of a program and enhance resistance to an analysis tool. Provided is a multi-code transformation method for binary obfuscation, comprising: a first obfuscation step of reconstructing a source code into a plurality of executable basic blocks; a second obfuscation step of inserting at least one fake basic block among the executable basic blocks; and a third obfuscation step of inserting a junk code into each of the executable basic block and the fake basic blocks, wherein the executable basic block includes at least one switch-case statement representing at least some statements of the source code.
Owner:FOUND OF SOONGSIL UNIV IND COOP

Processing method of multi-mode operating system

The invention discloses a processing method of a multi-modal operating system, belongs to the field of embedded operating systems, and mainly realizes multi-modal collaborative symbiosis of different operating systems on the same hardware platform through firmware fusion compiling, hardware resource sharing and application layer parameter unified management. The same hardware product supports the ecology of a plurality of different operating systems and supports the different operating systems to process respective skilled tasks in parallel; through firmware fusion compiling and hardware resource sharing, code redundancy and waste of hardware resources are effectively reduced, the development cost is reduced, and efficient utilization of system resources is achieved; through unified management of application layer parameters, synchronization is combined with an atomization read-write and synchronization mechanism, consistency of data states among different operating systems is guaranteed, logic errors caused by data conflicts are avoided, and data reliability is improved.
Owner:SHENZHEN ZHONGYI TENGDA TECH CO LTD

Function name resolution in library transformation on same architecture

A computer-implemented method for transforming a library from a source operating system to a target operating system is disclosed. Thereby, the source operating system comprises an ABI, the target operating system comprising a target ABI, the target ABI being different from the source ABI, the library being implemented by a source object file that is compliant with the source application binary interface and comprising a source memory image, source symbol and source relocation information. The method comprises also creating a target memory image, that is compliant with the target application binary interface, wherein the target memory is derived from the source memory image, enriching the target memory image with an address information pointing to a variable length information, and writing the target memory image to the target object file to implement the transformed library by the target object file.
Owner:INTERNATIONAL BUSINESS MACHINE CORPORATION

A network interface device as a computing platform

The examples described in this document relate to a network interface device. In some examples, the network interface device includes: a network interface, a direct memory access (DMA) circuitry, a host interface, memory, one or more processors, and a circuitry designed to: based on an operating configuration specifying standalone operation, cause the network interface device to operate in standalone mode to run one or more applications; and based on an operating configuration specifying companion operation, cause the network interface device to operate in companion mode to provide at least one host system with access to one or more hardware resources that the network interface device can access.
Owner:INTEL CORP

Function name resolution in library transformations on same architecture

A computer-implemented method for transforming a library from a source operating system to a target operating system is disclosed. Thereby, the source operating system comprises an ABI, the target operating system comprises a target ABI, the target ABI is different from the source ABI, the library is implemented by a source object file, the source object file conforms to the source application binary interface and comprises a source memory image, a source symbol and source relocation information. The method further includes creating a target memory image conforming to the target application binary interface, where the target memory is derived from the source memory image; enriching the target memory image with address information directed to the variable length information; and writing the target memory image to the target object file to implement the transformed library from the target object file.
Owner:INTERNATIONAL BUSINESS MACHINE CORPORATION

Program upgrading method and device, operating system, equipment, terminal, medium and program

The embodiment of the invention discloses a program upgrading method and device, an operating system, equipment, a terminal, a medium and a program, and the method comprises the steps: checking whether a called function has an upgrading link or not when an execution function calls a related byte code; under the condition of determining that the called function has the upgrading link, searching a byte code address of an upgrading function in an upgrading module corresponding to the called function through the upgrading link of the called function; and on the premise of keeping the operation domain of the original module, executing the byte code of the upgrading function based on the byte code address of the upgrading function in the upgrading module corresponding to the called function. The technical scheme of the embodiment of the invention can improve the execution speed of the upgrade program and reduce the memory overhead of the system RAM.
Owner:BEIJING TONGFANG MICROELECTRONICS

Method and device for optimizing basic block jump in binary translation super block and computing equipment

The invention discloses a method and device for optimizing basic block jumping in a binary translation super block and computing equipment. The method for optimizing the basic block jump in the binary translation super block comprises the following steps: constructing a basic block in the super block; obtaining the current basic block and starting translation; if a direct jump instruction is encountered, jumping to a target basic block, combining the current basic block and the target basic block into a new basic block, and continuing to translate; if an indirect jump instruction is encountered, the current basic block which is translated at present points to the scheduling basic block, and translation is ended; if a privilege or abnormal instruction is encountered, the basic block which is translated currently points to the scheduling basic block, and translation is ended; and if the counter in the corresponding basic block exceeds a set threshold value, the translation is ended, otherwise, the translation is continued. According to the method, the times of quitting the super block when the super block is translated can be reduced, so that the overall execution performance of the super block is improved.
Owner:ZHEJIANG DIJIE SOFTWARE TECH CO LTD

Binary translation optimization method, binary translator and electronic equipment

The embodiment of the invention provides a binary translation optimization method, a binary translator and electronic equipment, and the method comprises the steps: updating a state mark of a first register in a preset state table according to the write bit width of a narrow write operation to the first register when a narrow write operation instruction is translated; the state mark is used for indicating whether the high bit of the corresponding register needs to be reset or not and recording the effective bit width of the corresponding register; when a read operation instruction is translated, obtaining a state mark of a second register corresponding to read operation from the preset state table; if it is judged that the reading bit width of the reading operation is larger than the effective bit width indicated by the state mark of the second register, a first zero clearing instruction is inserted before the translation result of the reading operation instruction; the first zero clearing instruction is used for performing zero clearing on a specified high bit of the second register. According to the method, the target machine code sequence generated by translation can be simplified, redundant operations are greatly reduced, and the execution efficiency of a translation system is improved.
Owner:LOONGSON TECH CORP

Method and apparatus with scalar-to-vector binary instruction translation

A binary instruction translation method includes: receiving and decoding an instruction stream including instructions and pieces of instruction-information respectively corresponding to the instructions; determining whether the instructions in the instruction stream are translatable into a vector instruction stream based on the pieces of instruction-information; and based on a result of the determining, translate the instructions of the instruction stream to a vector instruction stream, the translating including translating at least some of the instructions of the instruction stream to vector instructions in a vector-specific instruction set by replacing scalar instructions of a first instruction set architecture (ISA) with functionally equivalent vector instructions of a vector-specific ISA.
Owner:SAMSUNG ELECTRONICS CO LTD

Stateless content management system

One embodiment comprises a stateless container of binaries and a broker. The stateless container of binaries includes a code memory having stored thereon code for a first version of a first functional component of a content management system, the first functional component executable to provide a first version of a service. The broker may be executable to: receive a request for the service from a client application, the request associated with a user of the content management system; determine that the first version of the service is accessible with regard to the user; determine an available first server that hosts the first version of the service; provide an indication of the first version of the service to the client application; and provide an IP address and a port number associated with the available first server to the client application.
Owner:OPEN TEXT CORP

Systems and methods for performing binary translation

Systems and methods for performing binary translation include a system that is capable of translating binaries written for use in a source execution environment to binaries compatible with a target execution environment. Consistent with some embodiments, a binary translation system includes a system service and a runtime code module that exists in an application memory address space. The binary translation system translates object-level binaries corresponding to executables, linkers, libraries, and the like and stores the translation in a translation cache that is cryptographically secured to ensure that only a system having a specific key is able to access the translations. If the application or application binary has been modified since the translation was performed, the system service will ensure that the translation is removed from the cache, a new translation is performed, and all threads accessing that translation are updated to the new translation.
Owner:APPLE INC

Computer-implemented method and apparatus for providing binary instructions

A computer-implemented or hardware-implemented method and apparatus (100) for automated diverse redundancy execution of binary instructions, where the apparatus (100) comprises a first processor (102) having a first architecture and a second processor (104) having a second architecture, where the first processor (102) is configured to execute binary instructions in a first format, where the second processor (104) is configured to execute binary instructions in a second format. The second processor (104) is configured to execute binary instructions in a second format, different from the first format, the device (100) is configured to provide at least one binary instruction (1) in the first format to the first processor (102) and to provide at least one binary instruction (2) redundant to the at least one first binary instruction (1) in the second format to the second processor (104), the device (100) is designed to either receive the at least one binary instruction (1) in the first format and to determine the at least one binary instruction (2) in the second format from the at least one binary instruction (1) in the first format, or receiving a binary instruction in a third format different from the first format and from the second format for the binary instruction, a binary instruction (3) redundant with the at least one binary instruction (1) of the first format and with the at least one binary instruction (2) of the second format and determining the at least one binary instruction (1) of the first format and the at least one binary instruction (2) of the second format according to the binary instruction of the third format.
Owner:ROBERT BOSCH GMBH

Parallel code fragments with foreign code

In various examples, an executable object including parallel code fragments with foreign code is executed by one or more processors. For example, when a selection mask is enabled, instructions encoded in the executable object are translated for execution by the one or more processors. Continuing this example, the executable object includes the parallel code fragment with the foreign code, once enabled and translated, the foreign code is provided to the target processor for execution.
Owner:UNISYS CORP

Systems and methods for automatically generating computer programming code and schedules and comparing their performance

Systems and methods utilize an auto-scheduler of a Domain Specific Language (DSL) to schedule one or more portions of a computer program written in a programming language other than the DSL. Portions of the computer program compatible with the DSL may be identified. The portions may be translated to a form compatible with the DSL. The DSL may generate schedules for the portions. Code may be generated for the computer program and the code may be executed. The schedules generated by the DSL may be utilized during execution of the code generated for the computer program.
Owner:MATHWORKS INC

Cyphergenics-based ecosystem security platforms

The present disclosure relates to Cyphergenics(CG)-enabled security platforms and corresponding digital genomic constructions that exhibit controlled entropy yet are subject to digital modification and reconstruction by computationally complex functions and processes without loss of genomic integrity. These constructions enable formation of comprehensively secure hyper-scalable digital ecosystems, enclaves, and / or digital cohorts having mutual identity of interests, and application specific security architectures based on genomic network topologies that are interoperable with contemporary application and networks stacks. In some implementations of the disclosure, the security platforms may be configured to facilitate secure data exchange between ecosystem members. In some aspects of the disclosure, the security platforms are configured to facilitate virtual trusted execution domains, whereby a processing environment is configured to perform CG-based encoding and decoding of instructions and program data. In some aspects of the disclosure, the security platforms are configured to facilitate material data chains (MDCs).
Owner:QUANTUM DIGITAL SOLUTIONS CORP

Method and apparatus for executing a plurality of computer programs on a data processing system

The invention relates to a method for executing a plurality of computer programs on a data processing system which has at least two separate computing units that share a common resource of the data processing system, wherein each computer program is executed by means of bytecode as program code means on one of the computing units of the data processing system, by converting the program code means of the respective computer program, which is present as bytecode, into the machine instructions relevant for the computing units by means of a code converter of the data processing system, characterized in that the code converter determines at least one interference value for each computer program as a function of a number of converted machine instructions per time step.
Owner:DEUTSCHES ZENTRUM FÜR LUFT UND RAUMFAHRT E V

Data security through temporary value translation

An example operation includes one or more of receiving a request to compile a software application, identifying one or more dummy values which were previously stored in source code of the software application, translating the one or more dummy values into source code using one or more secret values stored in a data store, and compiling, via a device, the source code of the software application into binary code using the secret values.
Owner:TOYOTA MOTOR NORTH AMERICA INC

Data processing method and apparatus

The application provides a data processing method and device, wherein the data processing method comprises: obtaining to-be-stored binary data and writing the to-be-stored binary data into a binary file; determining a data length of the to-be-stored binary data and a relative offset corresponding to the to-be-stored binary data; wherein the relative offset is a distance between a target address of the to-be-stored binary data in the binary file and a segment address of a field where the to-be-stored binary data is located; and updating a data structure object corresponding to the binary file based on the data length and the relative offset. Data stored in this form can be directly loaded into memory when called, and target data can be obtained without deserialization operation, so that data loading is more efficient, and in particular in a situation requiring real-time calculation of data, the operation without deserialization greatly increases system running efficiency, thereby solving the problems of slow system running and lag.
Owner:ZHUHAI KINGSOFT ONLINE GAME TECH CO LTD

Methods for monitoring a data flow

According to various embodiments, a method for monitoring a data flow in several executed application programs is described, wherein at least some of the application programs of the several application programs are programmed in different programming languages, comprising: Transforming the program code of each of the multiple application programs into code of a predefined binary instruction format, Inserting a data flow monitoring code into the code of the specified binary instruction format in each transformed application program to generate multiple extended transformed application programs in the code of the specified binary instruction format, and executing the multiple extended transformed application programs and thereby monitoring the data flow in the multiple extended transformed application programs using the data flow monitoring code inserted in each case.
Owner:ROBERT BOSCH GMBH

Composable kernels

A compiler for generating composable kernels. The compiler receives a kernel generator comprising a kernel parameterization and code of a set of operators written in a general purpose programming language. For each operator of the set of operators, the compiler lowers code of the each operator into an intermediate representation of the each operator in an intermediate language, determines a configuration of the each operator based on the kernel parameterization and the intermediate representation of the each operator, and generates a. binary object of the each operator of a set of binary' objects of the set of operators based on the configuration. The compiler composes a kernel corresponding to the kernel generator based on the set of binary objects of the set of operations and the kernel parameterization.
Owner:MODULAR INC