173results about "Binary to binary" patented technology

The embodiment of the invention provides a binary translation method, a binary translator, electronic equipment and a readable storage medium, and the method comprises the steps: calling a preset instruction if a current instruction is recognized as an indirect jump instruction; the instruction code of the preset instruction comprises a first operand and a second operand; the first operand points to the first register, and the second operand points to the second register; the target PC value is stored in the first register; the second register is used for storing a calculation result of the preset instruction; the preset instruction executes preset calculation logic to calculate a target index value corresponding to the target PC value in the hash table, and the target index value is written into a second register; the target index value is read from the second register, whether the target PC value hits the hash table or not is inquired through the target index value, and the next instruction is executed based on the inquiry result. According to the embodiment of the invention, the instruction translation number of the high-frequency instruction can be reduced, and the execution efficiency of the binary translator is improved.

The embodiment of the invention provides a binary translation method, a binary translator, electronic equipment and a readable storage medium, and the method comprises the steps: obtaining a thread mode of a client program when an indirect jump instruction in the client program is translated; generating a target search code sequence according to the thread mode; wherein different thread modes correspond to different target search code sequences; the target search code sequence is used for searching a target jump table based on a jump target address of the indirect jump instruction to obtain a cache initial address of a translated basic block corresponding to the jump target address; and if the target search code sequence is successfully searched, skipping to a cache initial address of the translated basic block corresponding to the skipping target address. According to the embodiment of the invention, the translation of the indirect jump instruction can be optimized, and the efficiency of searching the indirect jump table is improved, so that the running efficiency of a translated program is improved.

A system, method, and computer-program product includes commencing a parent computer process based on receiving a request to perform an analytical operation on one or more datasets, commencing at least one child computer process that is launched by the parent computer process when the parent computer process initiates an execution of the analytical operation on the one or more datasets, transmitting, by the at least one child computer process, a request to the parent computer process to retrieve the one or more datasets, writing, by the parent computer process, the one or more datasets to a cross-process queue based on the parent computer process receiving the requests, reading, by the at least one child computer process, the one or more datasets from the cross-process queue, and executing, using an analytical application executing on the least one child computer process, the analytical operation based on the one or more datasets.

A system, method, and computer-program product includes commencing a parent computer process based on receiving a request to perform an analytical operation on one or more datasets, commencing at least one child computer process that is launched by the parent computer process when the parent computer process initiates an execution of the analytical operation on the one or more datasets, transmitting, by the at least one child computer process, a request to the parent computer process to retrieve the one or more datasets, writing, by the parent computer process, the one or more datasets to a cross-process queue based on the parent computer process receiving the requests, reading, by the at least one child computer process, the one or more datasets from the cross-process queue, and executing, using an analytical application executing on the least one child computer process, the analytical operation based on the one or more datasets.

A system, method, and computer-program product includes commencing a parent computer process based on receiving a request to perform an analytical operation on one or more datasets, commencing at least one child computer process that is launched by the parent computer process when the parent computer process initiates an execution of the analytical operation on the one or more datasets, transmitting, by the at least one child computer process, a request to the parent computer process to retrieve the one or more datasets, writing, by the parent computer process, the one or more datasets to a cross-process queue based on the parent computer process receiving the requests, reading, by the at least one child computer process, the one or more datasets from the cross-process queue, and executing, using an analytical application executing on the least one child computer process, the analytical operation based on the one or more datasets.

A system, method, and computer-program product includes commencing a parent computer process based on receiving a request to perform an analytical operation on one or more datasets, commencing at least one child computer process that is launched by the parent computer process when the parent computer process initiates an execution of the analytical operation on the one or more datasets, transmitting, by the at least one child computer process, a request to the parent computer process to retrieve the one or more datasets, writing, by the parent computer process, the one or more datasets to a cross-process queue based on the parent computer process receiving the requests, reading, by the at least one child computer process, the one or more datasets from the cross-process queue, and executing, using an analytical application executing on the least one child computer process, the analytical operation based on the one or more datasets.

A system including at least one processor programmed to identify, based on a policy to be enforced, one or more metadata symbols corresponding to an entity name; identify, from a target description describing a target system, an entity description matching the entity name, wherein the entity description describes an entity of the target system; and apply a metadata label to the entity of the target system, wherein the metadata label is based on the one or more metadata symbols corresponding to the entity name, as identified based on the policy.

A computer-implemented method including quantifying pre-defined technical porting goal of a porting project into a technical value model, receiving selected decisions regarding the target system and porting tasks and current version of the porting system, executing traceable porting steps based on the selected decisions, porting tasks and current version of the porting system and creating software artefacts of the target system, evaluating software artefacts created or converted by each of the executed porting steps and / or evaluating test results by applying and / or simulating each ported software artifact, outputting references to the versions of created and / or converted and evaluated software artifacts into a porting log, and training the creation and evaluation component of the porting system with data of the porting log based on the decisions and the outcome of the porting project using porting mechanism to reach the pre-defined goal for the porting system.

The invention relates to an accelerator chip instruction operation analysis method and device, equipment, a medium and a product. The method comprises the following steps: obtaining a plurality of data streams obtained by executing a binary file corresponding to a target kernel function by an accelerator chip, then obtaining a plurality of assembly instruction codes corresponding to the binary file according to the binary file, and then obtaining a plurality of assembly instruction codes corresponding to the binary file according to a time sequence of a clock cycle, performing matching processing on each assembly instruction code and a data stream corresponding to the assembly instruction code in sequence to obtain an instruction code analysis result corresponding to the assembly instruction code, the instruction code analysis result comprises at least one of the number of clock cycles required by the accelerator chip to execute the assembly instruction code and the number of execution times corresponding to the assembly instruction code. By adopting the method, the accuracy of analysis results can be improved.

The invention discloses a binary optimization method supporting multiple platforms, and the method comprises the following steps: 1, starting a target application load in a process, and collecting and analyzing program dynamic behavior information in the process; 2, taking the program dynamic behavior information and the target application load obtained in the step 1 as input, disassembling a corresponding binary code, optimizing, and outputting an optimized application load after linking is completed; and 3, replacing the original code of the application load with the optimized code of the application load to realize online code replacement. The invention further discloses a system for realizing the binary optimization method. The system comprises a program dynamic behavior information acquisition module, an offline binary optimization module and an online code replacement module. The invention further discloses application of the binary optimization method or the binary optimization system in multi-platform binary code optimization.

The invention provides a dynamic binary translation optimization method and system based on regional granularity. The method comprises the following steps: S1, initializing a program entry; s2, acquiring and analyzing an instruction; s3, performing cache query; s4, hot spot judgment; s5, performing interpretive execution; s6, initiating a compiling request; s7, compiling mode selection; s8, compiling and caching the code blocks; s9, skipping to a local code for execution; and S10, returning to the main cycle. According to the invention, the technical problems of limited optimization space, high context switching overhead and high code expansion rate are solved.

Systems, methods, and devices are provided for dynamically mapping and rerouting a non-optimized binary to an optimized binary. Embodiments identify a position-independent portion within a non-optimized binary and receive metadata associated with an optimized binary. Further, embodiments identify a location identifier within the optimized binary from the metadata and generate a delta value between the position-independent portion and the location identifier. Embodiments also update the position-independent portion with the delta value.

An example operation includes one or more of receiving a request to compile a software application, identifying one or more dummy values which were previously stored in source code of the software application, translating the one or more dummy values into source code using one or more secret values stored in a data store, and compiling, via a device, the source code of the software application into binary code using the secret values.

The invention discloses a binary translation method and device, electronic equipment and a readable storage medium. The method comprises the steps of obtaining a translation result of each basic block from a cache of a translator; when an instruction in the translation result is executed, if it is determined that the currently executed instruction is a target instruction with memory access alignment abnormity, remapping is performed according to a first memory access address included in the target instruction, a second memory access address is generated, and a memory area corresponding to the first memory access address is configured to be inaccessible; and executing memory access operation aiming at the second memory access address to access data of the second memory access address. The problem that in the prior art, execution of all other threads is stopped unconditionally, and consequently the execution efficiency of source program instruction translation is affected can be solved.

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: carrying out binary translation on a first code block to obtain a first translated code block, and determining a target state tag corresponding to the first code block during translation; when an indirect jump instruction in the first translation code block is executed, querying a quick lookup table according to a jump target address of the indirect jump instruction; when the quick lookup table is not hit, querying a first hash table corresponding to the target state tag according to a jump target address of the indirect jump instruction; the first hash table is used for recording a pointer of the translation code block matched with the target state tag, and the pointer points to an entry address of the translation code block. According to the embodiment of the invention, the code block searching efficiency can be improved, so that the execution efficiency of the indirect jump instruction is improved, and the performance of the system-level binary translator is improved.

The embodiment of the invention provides an exception processing method and device, electronic equipment and a readable storage medium. If a target exception is triggered when a target platform executes a target instruction, a target exception signal is generated, and an exception processing function corresponding to the target platform is called; the target instruction is obtained by performing binary translation on a current instruction in the source platform; based on the exception handling function, determining an exception type corresponding to the target exception signal; and under the condition that the exception type is a specified type, correcting an instruction operation result corresponding to the target instruction, and continuing to execute a subsequent instruction of the target instruction. Therefore, when floating point exceptions occur, the target exception signal is generated on the target platform, and the exception handling function is called for checking and handling, and compared with the prior art, the method and the device have the advantages that by changing the triggering mode of floating point exception checking, the number of times of executing exception checking is reduced, the program running overhead is reduced, and the program running efficiency is improved. And meanwhile, the program running efficiency is improved.

This application discloses code processing methods, apparatuses, and storage media. An example method includes: obtaining a first code in low-level language and applicable to a source platform; decompiling the obtained first code to obtain an intermediate representation (IR); and then compiling the IR into a second code in low-level language and applicable to a first target platform, where the source platform and the target platform have different instruction sets.

The invention discloses a binary translation method and device, electronic equipment and a readable storage medium. The method comprises the steps that a translation result of each basic block is obtained from a cache of a translator and executed; when it is detected that a preset position in the translation result contains a target instruction, execution of the translation result is stopped; the target instruction is used for triggering writing in the preset position when it is detected that updating operation is carried out on the basic block; and when the translation result change is not detected in the cache, translating the basic block after the updating operation is executed, so as to obtain a corresponding correction result after the basic block is updated, and continuing to execute the correction result. The problem that in the prior art, cached basic block codes are not matched with actual codes after updating operation, code execution errors occur when the cached basic block codes are executed, and then translation accuracy is affected can be solved.

The invention relates to the technical field of data processing, in particular to a GPU architecture conversion method and device. The method comprises the steps that assembly code input is received, ISA is analyzed into lexical units containing instruction elements according to input content, then detection of grammar rules and semantic logic is conducted on the lexical units based on grammar standards, and instruction objects carrying complete instruction attributes are generated; converting the instruction object into a corresponding LLVM function according to the attribute of the instruction object, generating an initial intermediate representation code, and finally compiling the optimized intermediate representation code into an executable machine code according to the target GPU hardware type. Through the embodiment of the invention, efficient conversion from the GPU assembly code to the multi-architecture machine code is realized, and the problem of performance loss caused by inaccurate grammar detection and insufficient optimization in traditional GPU development can be solved.

The invention discloses a compiler for generating reconfigurable executable programs, and particularly discloses apparatuses, systems, and techniques for executing a compiler to generate one or more executable programs that can be configured to be executed by one or more of a plurality of different processor architectures. In at least one embodiment, a compiler generates one or more executable programs based at least in part on the original uncompiled executable programs, which may be configured to be executed by one or more of a plurality of different processor architectures.

The invention is suitable for the technical field of block chains, and provides a byte code editing method and device, electronic equipment and a program product. The byte code editing method comprises the following steps: acquiring a first byte code to be edited; editing the first byte code to obtain a second byte code; according to the first byte code and the second byte code, determining whether the length of the byte code is changed or not; and if it is determined that the length of the byte code changes, adjusting the second byte code to obtain a target byte code, and outputting the target byte code. Through the editing method provided by the invention, after the byte code is edited, the edited byte code can be automatically checked and adjusted through the electronic equipment, so that the editing efficiency of the byte code editing method is improved.

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: when a direct jump instruction in a first code block is translated, if it is determined that a jump target has a cross-page condition, recording jump target cross-page information, the jump target cross-page information being used for indicating a cross-page type; executing a target link strategy on the first translation code block and the second translation code block according to the jump target cross-page information; the target link strategy is used for judging whether the direct jump instruction meets an optimization condition or not according to a cross-page type indicated by the jump target cross-page information; and if the optimization condition is met, establishing a direct jump link for the first translation code block and the second translation code block. According to the embodiment of the invention, on the basis of ensuring the correct execution, the optimizable condition when the target page is skipped is identified, the link optimization operation is further executed, the code block search operation in the program running process is reduced, and the program running efficiency is improved.

This application is applicable to the field of blockchain technology, and provides a method, apparatus, electronic device, and program product for editing bytecode. The method for editing bytecode includes: obtaining a first bytecode to be edited; editing the first bytecode to obtain a second bytecode; determining whether the length of the bytecode changes according to the first bytecode and the second bytecode; if it is determined that the length of the bytecode changes, then adjusting the second bytecode to obtain a target bytecode, and outputting the target bytecode. Through the editing method of this application, after editing the bytecode, the electronic device can automatically verify and adjust the edited bytecode, improving the editing efficiency of the bytecode editing method.

The translation program causes, as a receiving unit (13), a PLC program development environment (10) that translates a first source code (21), which is described in a first language, of a program to be executed in order to control a device to be controlled by a PLC (30) into a second source code (22), which is described in a second language, and causes a translation unit (12) to function, said receiving unit (13) receiving a specification of a monitoring variable. The translation unit (12) translates the first source code (21) into the second source code (22). A translation unit (12) converts a code relating to a variable of a value stored in a shared memory between a PLC (30) and a device to be controlled in a first source code (21) to a code that refers to the shared memory when the variable is a monitoring variable, and converts the code to a code that refers to a non-shared memory when the variable is different from the monitoring variable.

The application discloses a binary optimization method supporting multiple platforms, which comprises the following steps: step one, starting a target application load in a process, collecting and analyzing program dynamic behavior information in the process; step two, taking the program dynamic behavior information obtained in step one and the target application load as inputs, disassembling corresponding binary codes, optimizing the binary codes, and outputting the application load after the optimization is completed; and step three, replacing the code of the original application load with the code of the optimized application load, so as to realize online code replacement. The application further discloses a system for realizing the binary optimization method, which comprises a program dynamic behavior information collecting module, an offline binary optimization module and an online code replacement module. The application further discloses application of the binary optimization method or the binary optimization system in optimization of multiple-platform binary codes.

The present disclosure relates to CipherGenics (CG)-enabled security platforms and corresponding digital genome constructions that undergo digital modification and reconfiguration by computationally complex functions and processes without losing genome integrity while exhibiting controlled entropy. These constructions enable the formation of comprehensively secure hyper-scalable digital ecosystems, enclaves, and / or digital cohorts with mutual identities of interest, and enable application-specific security architectures based on genome network topologies interoperable with modern applications and network stacks. In some embodiments of the present disclosure, the security platform may be configured to facilitate secure data exchange between members of the ecosystem. In some embodiments of the present disclosure, the security platform is configured to facilitate a Material Data Chain (MDC).

The invention discloses a cross-ISA (Industrial Standard Architecture) extension program translation method based on binary rewriting, which comprises the following steps of: 1) naming an instruction set ISA of a program to be translated as an original ISA, and naming an instruction set ISA on target hardware for running original ISA extension as a target ISA; 2) performing comparative analysis on a binary file corresponding to the original ISA extension compilation and a binary file corresponding to the target ISA extension compilation to obtain an instruction needing to be translated relative to the target ISA extension in the original ISA extension, and segmenting the instruction into a plurality of program basic blocks needing to be translated; 3) allocating a jump instruction and an address space for translating and storing translated codes to each program basic block; (4) distributing the program basic blocks into the corresponding address spaces through a jump instruction to carry out static binary translation, and generating a static file; and (5) distributing a loading address for the static file by utilizing a loader according to the address distribution information in the static file, and loading the static file to a corresponding position.

The objective of the present invention is to prevent reverse engineering of a program and enhance resistance to an analysis tool. Provided is a multi-code transformation method for binary obfuscation, comprising: a first obfuscation step of reconstructing a source code into a plurality of executable basic blocks; a second obfuscation step of inserting at least one fake basic block among the executable basic blocks; and a third obfuscation step of inserting a junk code into each of the executable basic block and the fake basic blocks, wherein the executable basic block includes at least one switch-case statement representing at least some statements of the source code.

The invention discloses a processing method of a multi-modal operating system, belongs to the field of embedded operating systems, and mainly realizes multi-modal collaborative symbiosis of different operating systems on the same hardware platform through firmware fusion compiling, hardware resource sharing and application layer parameter unified management. The same hardware product supports the ecology of a plurality of different operating systems and supports the different operating systems to process respective skilled tasks in parallel; through firmware fusion compiling and hardware resource sharing, code redundancy and waste of hardware resources are effectively reduced, the development cost is reduced, and efficient utilization of system resources is achieved; through unified management of application layer parameters, synchronization is combined with an atomization read-write and synchronization mechanism, consistency of data states among different operating systems is guaranteed, logic errors caused by data conflicts are avoided, and data reliability is improved.

A computer-implemented method for transforming a library from a source operating system to a target operating system is disclosed. Thereby, the source operating system comprises an ABI, the target operating system comprising a target ABI, the target ABI being different from the source ABI, the library being implemented by a source object file that is compliant with the source application binary interface and comprising a source memory image, source symbol and source relocation information. The method comprises also creating a target memory image, that is compliant with the target application binary interface, wherein the target memory is derived from the source memory image, enriching the target memory image with an address information pointing to a variable length information, and writing the target memory image to the target object file to implement the transformed library by the target object file.