135results about "Binary to binary" patented technology

A system, method, and computer-program product includes commencing a parent computer process based on receiving a request to perform an analytical operation on one or more datasets, commencing at least one child computer process that is launched by the parent computer process when the parent computer process initiates an execution of the analytical operation on the one or more datasets, transmitting, by the at least one child computer process, a request to the parent computer process to retrieve the one or more datasets, writing, by the parent computer process, the one or more datasets to a cross-process queue based on the parent computer process receiving the requests, reading, by the at least one child computer process, the one or more datasets from the cross-process queue, and executing, using an analytical application executing on the least one child computer process, the analytical operation based on the one or more datasets.

A computer-implemented method including quantifying pre-defined technical porting goal of a porting project into a technical value model, receiving selected decisions regarding the target system and porting tasks and current version of the porting system, executing traceable porting steps based on the selected decisions, porting tasks and current version of the porting system and creating software artefacts of the target system, evaluating software artefacts created or converted by each of the executed porting steps and / or evaluating test results by applying and / or simulating each ported software artifact, outputting references to the versions of created and / or converted and evaluated software artifacts into a porting log, and training the creation and evaluation component of the porting system with data of the porting log based on the decisions and the outcome of the porting project using porting mechanism to reach the pre-defined goal for the porting system.

The invention provides a dynamic binary translation optimization method and system based on regional granularity. The method comprises the following steps: S1, initializing a program entry; s2, acquiring and analyzing an instruction; s3, performing cache query; s4, hot spot judgment; s5, performing interpretive execution; s6, initiating a compiling request; s7, compiling mode selection; s8, compiling and caching the code blocks; s9, skipping to a local code for execution; and S10, returning to the main cycle. According to the invention, the technical problems of limited optimization space, high context switching overhead and high code expansion rate are solved.

Systems, methods, and devices are provided for dynamically mapping and rerouting a non-optimized binary to an optimized binary. Embodiments identify a position-independent portion within a non-optimized binary and receive metadata associated with an optimized binary. Further, embodiments identify a location identifier within the optimized binary from the metadata and generate a delta value between the position-independent portion and the location identifier. Embodiments also update the position-independent portion with the delta value.

An example operation includes one or more of receiving a request to compile a software application, identifying one or more dummy values which were previously stored in source code of the software application, translating the one or more dummy values into source code using one or more secret values stored in a data store, and compiling, via a device, the source code of the software application into binary code using the secret values.

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: carrying out binary translation on a first code block to obtain a first translated code block, and determining a target state tag corresponding to the first code block during translation; when an indirect jump instruction in the first translation code block is executed, querying a quick lookup table according to a jump target address of the indirect jump instruction; when the quick lookup table is not hit, querying a first hash table corresponding to the target state tag according to a jump target address of the indirect jump instruction; the first hash table is used for recording a pointer of the translation code block matched with the target state tag, and the pointer points to an entry address of the translation code block. According to the embodiment of the invention, the code block searching efficiency can be improved, so that the execution efficiency of the indirect jump instruction is improved, and the performance of the system-level binary translator is improved.

The embodiment of the invention provides an exception processing method and device, electronic equipment and a readable storage medium. If a target exception is triggered when a target platform executes a target instruction, a target exception signal is generated, and an exception processing function corresponding to the target platform is called; the target instruction is obtained by performing binary translation on a current instruction in the source platform; based on the exception handling function, determining an exception type corresponding to the target exception signal; and under the condition that the exception type is a specified type, correcting an instruction operation result corresponding to the target instruction, and continuing to execute a subsequent instruction of the target instruction. Therefore, when floating point exceptions occur, the target exception signal is generated on the target platform, and the exception handling function is called for checking and handling, and compared with the prior art, the method and the device have the advantages that by changing the triggering mode of floating point exception checking, the number of times of executing exception checking is reduced, the program running overhead is reduced, and the program running efficiency is improved. And meanwhile, the program running efficiency is improved.

This application discloses code processing methods, apparatuses, and storage media. An example method includes: obtaining a first code in low-level language and applicable to a source platform; decompiling the obtained first code to obtain an intermediate representation (IR); and then compiling the IR into a second code in low-level language and applicable to a first target platform, where the source platform and the target platform have different instruction sets.

The invention relates to the technical field of data processing, in particular to a GPU architecture conversion method and device. The method comprises the steps that assembly code input is received, ISA is analyzed into lexical units containing instruction elements according to input content, then detection of grammar rules and semantic logic is conducted on the lexical units based on grammar standards, and instruction objects carrying complete instruction attributes are generated; converting the instruction object into a corresponding LLVM function according to the attribute of the instruction object, generating an initial intermediate representation code, and finally compiling the optimized intermediate representation code into an executable machine code according to the target GPU hardware type. Through the embodiment of the invention, efficient conversion from the GPU assembly code to the multi-architecture machine code is realized, and the problem of performance loss caused by inaccurate grammar detection and insufficient optimization in traditional GPU development can be solved.

The invention discloses a compiler for generating reconfigurable executable programs, and particularly discloses apparatuses, systems, and techniques for executing a compiler to generate one or more executable programs that can be configured to be executed by one or more of a plurality of different processor architectures. In at least one embodiment, a compiler generates one or more executable programs based at least in part on the original uncompiled executable programs, which may be configured to be executed by one or more of a plurality of different processor architectures.

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: when a direct jump instruction in a first code block is translated, if it is determined that a jump target has a cross-page condition, recording jump target cross-page information, the jump target cross-page information being used for indicating a cross-page type; executing a target link strategy on the first translation code block and the second translation code block according to the jump target cross-page information; the target link strategy is used for judging whether the direct jump instruction meets an optimization condition or not according to a cross-page type indicated by the jump target cross-page information; and if the optimization condition is met, establishing a direct jump link for the first translation code block and the second translation code block. According to the embodiment of the invention, on the basis of ensuring the correct execution, the optimizable condition when the target page is skipped is identified, the link optimization operation is further executed, the code block search operation in the program running process is reduced, and the program running efficiency is improved.

This application is applicable to the field of blockchain technology, and provides a method, apparatus, electronic device, and program product for editing bytecode. The method for editing bytecode includes: obtaining a first bytecode to be edited; editing the first bytecode to obtain a second bytecode; determining whether the length of the bytecode changes according to the first bytecode and the second bytecode; if it is determined that the length of the bytecode changes, then adjusting the second bytecode to obtain a target bytecode, and outputting the target bytecode. Through the editing method of this application, after editing the bytecode, the electronic device can automatically verify and adjust the edited bytecode, improving the editing efficiency of the bytecode editing method.

The translation program causes, as a receiving unit (13), a PLC program development environment (10) that translates a first source code (21), which is described in a first language, of a program to be executed in order to control a device to be controlled by a PLC (30) into a second source code (22), which is described in a second language, and causes a translation unit (12) to function, said receiving unit (13) receiving a specification of a monitoring variable. The translation unit (12) translates the first source code (21) into the second source code (22). A translation unit (12) converts a code relating to a variable of a value stored in a shared memory between a PLC (30) and a device to be controlled in a first source code (21) to a code that refers to the shared memory when the variable is a monitoring variable, and converts the code to a code that refers to a non-shared memory when the variable is different from the monitoring variable.

The application discloses a binary optimization method supporting multiple platforms, which comprises the following steps: step one, starting a target application load in a process, collecting and analyzing program dynamic behavior information in the process; step two, taking the program dynamic behavior information obtained in step one and the target application load as inputs, disassembling corresponding binary codes, optimizing the binary codes, and outputting the application load after the optimization is completed; and step three, replacing the code of the original application load with the code of the optimized application load, so as to realize online code replacement. The application further discloses a system for realizing the binary optimization method, which comprises a program dynamic behavior information collecting module, an offline binary optimization module and an online code replacement module. The application further discloses application of the binary optimization method or the binary optimization system in optimization of multiple-platform binary codes.

The invention discloses a cross-ISA (Industrial Standard Architecture) extension program translation method based on binary rewriting, which comprises the following steps of: 1) naming an instruction set ISA of a program to be translated as an original ISA, and naming an instruction set ISA on target hardware for running original ISA extension as a target ISA; 2) performing comparative analysis on a binary file corresponding to the original ISA extension compilation and a binary file corresponding to the target ISA extension compilation to obtain an instruction needing to be translated relative to the target ISA extension in the original ISA extension, and segmenting the instruction into a plurality of program basic blocks needing to be translated; 3) allocating a jump instruction and an address space for translating and storing translated codes to each program basic block; (4) distributing the program basic blocks into the corresponding address spaces through a jump instruction to carry out static binary translation, and generating a static file; and (5) distributing a loading address for the static file by utilizing a loader according to the address distribution information in the static file, and loading the static file to a corresponding position.

The objective of the present invention is to prevent reverse engineering of a program and enhance resistance to an analysis tool. Provided is a multi-code transformation method for binary obfuscation, comprising: a first obfuscation step of reconstructing a source code into a plurality of executable basic blocks; a second obfuscation step of inserting at least one fake basic block among the executable basic blocks; and a third obfuscation step of inserting a junk code into each of the executable basic block and the fake basic blocks, wherein the executable basic block includes at least one switch-case statement representing at least some statements of the source code.

The invention discloses a processing method of a multi-modal operating system, belongs to the field of embedded operating systems, and mainly realizes multi-modal collaborative symbiosis of different operating systems on the same hardware platform through firmware fusion compiling, hardware resource sharing and application layer parameter unified management. The same hardware product supports the ecology of a plurality of different operating systems and supports the different operating systems to process respective skilled tasks in parallel; through firmware fusion compiling and hardware resource sharing, code redundancy and waste of hardware resources are effectively reduced, the development cost is reduced, and efficient utilization of system resources is achieved; through unified management of application layer parameters, synchronization is combined with an atomization read-write and synchronization mechanism, consistency of data states among different operating systems is guaranteed, logic errors caused by data conflicts are avoided, and data reliability is improved.

A computer-implemented method for transforming a library from a source operating system to a target operating system is disclosed. Thereby, the source operating system comprises an ABI, the target operating system comprising a target ABI, the target ABI being different from the source ABI, the library being implemented by a source object file that is compliant with the source application binary interface and comprising a source memory image, source symbol and source relocation information. The method comprises also creating a target memory image, that is compliant with the target application binary interface, wherein the target memory is derived from the source memory image, enriching the target memory image with an address information pointing to a variable length information, and writing the target memory image to the target object file to implement the transformed library by the target object file.

Embodiments of the present invention relate to the field of network orchestration technology, and in particular, to a model conversion method, apparatus, electronic device, and storage medium. In the present invention, a source model and a target model are obtained, where the source model and the target model are used to describe data formats; a mapping relationship between the fields of the source model and the fields of the target model is obtained; source model data is obtained; and according to the mapping relationship, the source model data is converted into target model data. By obtaining the source model and the target model and the mapping relationship between the fields of the source model and the fields of the target model, the mapping relationship between different models can be obtained. Then, by obtaining the source model data and converting the source model data into target model data according to the mapping relationship, it is no longer limited to the conversion between fixed models, but can be applied to the conversion between different models, without the need to re-code different models, saving human resources and reducing conversion time.

The examples described in this document relate to a network interface device. In some examples, the network interface device includes: a network interface, a direct memory access (DMA) circuitry, a host interface, memory, one or more processors, and a circuitry designed to: based on an operating configuration specifying standalone operation, cause the network interface device to operate in standalone mode to run one or more applications; and based on an operating configuration specifying companion operation, cause the network interface device to operate in companion mode to provide at least one host system with access to one or more hardware resources that the network interface device can access.

A computer-implemented method for transforming a library from a source operating system to a target operating system is disclosed. Thereby, the source operating system comprises an ABI, the target operating system comprises a target ABI, the target ABI is different from the source ABI, the library is implemented by a source object file, the source object file conforms to the source application binary interface and comprises a source memory image, a source symbol and source relocation information. The method further includes creating a target memory image conforming to the target application binary interface, where the target memory is derived from the source memory image; enriching the target memory image with address information directed to the variable length information; and writing the target memory image to the target object file to implement the transformed library from the target object file.

The embodiment of the invention discloses a program upgrading method and device, an operating system, equipment, a terminal, a medium and a program, and the method comprises the steps: checking whether a called function has an upgrading link or not when an execution function calls a related byte code; under the condition of determining that the called function has the upgrading link, searching a byte code address of an upgrading function in an upgrading module corresponding to the called function through the upgrading link of the called function; and on the premise of keeping the operation domain of the original module, executing the byte code of the upgrading function based on the byte code address of the upgrading function in the upgrading module corresponding to the called function. The technical scheme of the embodiment of the invention can improve the execution speed of the upgrade program and reduce the memory overhead of the system RAM.

The invention discloses a method and device for optimizing basic block jumping in a binary translation super block and computing equipment. The method for optimizing the basic block jump in the binary translation super block comprises the following steps: constructing a basic block in the super block; obtaining the current basic block and starting translation; if a direct jump instruction is encountered, jumping to a target basic block, combining the current basic block and the target basic block into a new basic block, and continuing to translate; if an indirect jump instruction is encountered, the current basic block which is translated at present points to the scheduling basic block, and translation is ended; if a privilege or abnormal instruction is encountered, the basic block which is translated currently points to the scheduling basic block, and translation is ended; and if the counter in the corresponding basic block exceeds a set threshold value, the translation is ended, otherwise, the translation is continued. According to the method, the times of quitting the super block when the super block is translated can be reduced, so that the overall execution performance of the super block is improved.

The embodiment of the invention provides a binary translation optimization method, a binary translator and electronic equipment, and the method comprises the steps: updating a state mark of a first register in a preset state table according to the write bit width of a narrow write operation to the first register when a narrow write operation instruction is translated; the state mark is used for indicating whether the high bit of the corresponding register needs to be reset or not and recording the effective bit width of the corresponding register; when a read operation instruction is translated, obtaining a state mark of a second register corresponding to read operation from the preset state table; if it is judged that the reading bit width of the reading operation is larger than the effective bit width indicated by the state mark of the second register, a first zero clearing instruction is inserted before the translation result of the reading operation instruction; the first zero clearing instruction is used for performing zero clearing on a specified high bit of the second register. According to the method, the target machine code sequence generated by translation can be simplified, redundant operations are greatly reduced, and the execution efficiency of a translation system is improved.

A binary instruction translation method includes: receiving and decoding an instruction stream including instructions and pieces of instruction-information respectively corresponding to the instructions; determining whether the instructions in the instruction stream are translatable into a vector instruction stream based on the pieces of instruction-information; and based on a result of the determining, translate the instructions of the instruction stream to a vector instruction stream, the translating including translating at least some of the instructions of the instruction stream to vector instructions in a vector-specific instruction set by replacing scalar instructions of a first instruction set architecture (ISA) with functionally equivalent vector instructions of a vector-specific ISA.

One embodiment comprises a stateless container of binaries and a broker. The stateless container of binaries includes a code memory having stored thereon code for a first version of a first functional component of a content management system, the first functional component executable to provide a first version of a service. The broker may be executable to: receive a request for the service from a client application, the request associated with a user of the content management system; determine that the first version of the service is accessible with regard to the user; determine an available first server that hosts the first version of the service; provide an indication of the first version of the service to the client application; and provide an IP address and a port number associated with the available first server to the client application.

Systems and methods for performing binary translation include a system that is capable of translating binaries written for use in a source execution environment to binaries compatible with a target execution environment. Consistent with some embodiments, a binary translation system includes a system service and a runtime code module that exists in an application memory address space. The binary translation system translates object-level binaries corresponding to executables, linkers, libraries, and the like and stores the translation in a translation cache that is cryptographically secured to ensure that only a system having a specific key is able to access the translations. If the application or application binary has been modified since the translation was performed, the system service will ensure that the translation is removed from the cache, a new translation is performed, and all threads accessing that translation are updated to the new translation.

To provide a secure software process.SOLUTION: An example operation includes one or more of: receiving a request to compile a software application; identifying one or more dummy values which were previously stored in source code of the software application; translating the one or more dummy values into source code using one or more secret values stored in a data store; and compiling, via a device, the source code of the software application into binary code using the secret values.SELECTED DRAWING: Figure 1A

The present disclosure discloses a method for compiling a computational graph and related products. The method includes: obtaining a computational graph to be compiled, expressed by a second intermediate representation, performing forward deduction of the shape, and obtaining complete shape information based on the forward deduction and tensor data splitting information; using the complete shape information, determining whether the tensor data splitting information needs to be adjusted; determining tensor data splitting information that meets the requirements based on the judgment result; deducing memory access modes for operators in the computational graph based on the tensor data splitting information that meets the requirements; determining address domain-related parameters of instructions involved in a loop in the code logic of the computational graph based on the deduced memory access mode; pipeline-arranging the instructions in the loop; and compiling the computational graph based on the address domain-related parameters of the instructions involved in the loop and the result of the instruction pipeline arrangement to obtain a binary file recognizable by an intelligent processor.