331 results about "High-level programming language" patented technology

A state machine gesture recognition algorithm for interpreting streams of coordinates received from a touch sensor. The gesture recognition code can be written in a high level language such as C and then compiled and embedded in a microcontroller chip, or CPU chip as desired. The gesture recognition code can be loaded into the same chip that interprets the touch signals from the touch sensor and generates the time series data, e.g. a microcontroller, or other programmable logic device such as a field programmable gate array.

A verification module evaluates intermediate language code to verify that the code is type safe before passing the code for execution. Code that is not deemed type safe can cause execution errors, corrupt the runtime environment in which the code is executing, or cause unauthorized access to protected system resources. As such, the verification module protects a computer system from intentional or inadvertent breaches of the computer system's defenses. The verification module verifies the type safety of intermediate language code that supports significant high-level language constructs prohibited by verification modules in the prior art. One exemplary verification module verifies intermediate language code that includes one or more reference-based parameter, such as a pointer (or reference), a value class containing pointers, a RefAny parameter, or a nested pointer.

A system and methods for parallel processing of queries to one or more databases are described herein. One or more databases may be distributed among a subset of slave nodes of a global-results processing matrix. A query to the database may be generated using a query-based high-level programming language. The query-based source code then may be converted to intermediary source code in a common programming language and then compiled into a dynamic link library (DLL) or other type of executable. The DLL is then distributed among the slave nodes of the processing matrix, whereupon the slave nodes execute related portions of the DLL substantially in parallel to generate initial query results. The initial query results may then be provided to master node of the global-results processing matrix for additional processing, whereby the master node is adapted to execute one or more associated portions of the DLL on the initial query results.

A card reader / writer which interfaces between a host application program and a data storage card. The card reader / writer reads from and writes to the application program with high level language of the commands. The card reader / writer translates the high level language commands of the host program to corresponding sequences of low level commands for reading and writing to the data storage card. The card reader / writer stores a plurality of sets of such low level commands, and is able to establish the card type for any card interfaced with the card reader / writer, and to use the appropriate command set for the established card type. The card reader / writer also translates low level commands from the card to high level commands for the host application program. The card reader / writer can be loaded with low level command sets for additional card types as required.

A system and method describing a compatibility server for rehosting database applications written for a specific vendor's database on the database of a second vendor, without the need of rewriting the application to take into account differences in the application programming interfaces between the first vendor's database and the second vendor's database. Requests for access to the database are translated from one format to another at execution time. The server is also capable of translating error messages, data types and data formatting from the format used by the second database to that expected when making requests to the first database. Stored procedures defined in the first database are migrated to the second database as text blocks, and are translated at execution time into a high level programming language, compiled and executed against the second database. All information necessary for the mapping of schema, data, data types, error and status messages and data formatting, as well as information necessary to execute stored procedures, is stored in a plurality of metadata tables in the second database, which are created during a migration phase prior to executing the application.

Usage semantics allow for shaders to be authored independently of the actual vertex data and accordingly enables their reuse. Usage semantics define a feature that binds data between distinct components to allow them to work together. In various embodiments, the components include high level language variables that are bound by an application or by vertex data streams, high level language fragments to enable several fragments to be developed separately and compiled at a later time together to form a single shader, assembly language variables that get bound to vertex data streams, and parameters between vertex and pixel shaders. This allows developers to be able to program the shaders in the assembly and high level language with variables that refer to names rather than registers. By allowing this decoupling of registers from the language, developers can work on the language separately from the vertex data and modify and enhance high level language shaders without having to manually manipulate the registers. This also allows the same shaders to work on different sets of mesh data, allowing the shaders to be reused. Generally, semantics can be used as a data binding protocol between distinct areas of the programmable pipeline to allow for a more flexible workflow.

A method for translating high-level languages to reconfigurable architectures is disclosed. The method includes building a finite automaton for calculation. The method further includes forming a combinational network of a plurality of individual functions in accordance with the structure of the finite automaton. The method further includes allocating a plurality of memories to the network for storing a plurality of operands and a plurality of results.

A card reader / writer which interfaces between a host application program and a data storage card. The card reader / writer reads from and writes to the application program with high level language of the commands. The card reader / writer translates the high level language commands of the host program to corresponding sequences of low level commands for reading and writing to the data storage card. The card reader / writer stores a plarality of sets of such low level commands, and is able to establish the card type for any card interfaced with the card reader / writer, and to use the appropriate command set for the established card type. The card reader / writer also translates low level commands from the card to high level commands for the host application program. The card reader / writer can be loaded with low level command sets for additional card types as required.

Code can be injected into a compiled application through the use of probes comprised of instrumentation code. Probes can be implemented in a custom high level language that hides low level instruction details. A directive file contains instructions on injecting a probe into a compiled application. An instrumentation engine reads these instructions and injects the probe into the compiled application at the appropriate injection points. Multiple probes can be used, and can be stored in a probe library. Each probe can inject code into the application at, for example, a package, class, method, or line of the compiled application. Calls can also be made to external runtime libraries. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures, and the claims.

An apparatus and method for partitioning programs between a general purpose core and one or more accelerators are provided. With the apparatus and method, a compiler front end is provided for converting a program source code in a corresponding high level programming language into an intermediate code representation. This intermediate code representation is provided to an interprocedural optimizer which determines which core processor or accelerator each portion of the program should execute on and partitions the program into sub-programs based on this set of decisions. The interprocedural optimizer may further add instructions to the partitions to coordinate and synchronize the sub-programs as required. Each sub-program is compiled on an appropriate compiler backend for the instruction set architecture of the particular core processor or accelerator selected to execute the sub-program. The compiled sub-programs and then linked to thereby generate an executable program.

In a computer implemented learning and / or process control system, a computer model is constituted by the most currently fit entity in a population of computer program entities. The computer model defines fitness as a function of inputs and outputs. A computing unit accesses the model with a set of inputs, and determines a set of outputs for which the fitness is highest. This associates a sensory-motor (input-output) state with a fitness in a manner that might be termed "feeling".The learning and / or control system preferably utilizes a Compiling Genetic Programming System (CGPS) in which one or more machine code entities such as functions are created which represent solutions to a problem and are directly executable by a computer. The programs are created and altered by a program in a higher level language such as "C" which is not directly executable, but requires translation into executable machine code through compilation, interpretation, translation, etc. The entities are initially created as an integer array that can be altered by the program as data, and are executed by the program by recasting a pointer to the array as a function type. The entities are evaluated by executing them with training data as inputs, and calculating fitnesses based on a predetermined criterion. The entities are then altered based on their fitnesses using a genetic machine learning algorithm by recasting the pointer to the array as a data (e.g. integer) type. This process is iteratively repeated until an end criterion is reached.

An integrated circuit card is used with a terminal. The integrated circuit card includes a memory that stores an interpreter and an application that has a high level programming language format. A processor of the card is configured to use the interpreter to interpret the application for execution and to use a communicator of the card to communicate with the terminal.

A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. The compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.

One or more machine code entities such as functions are created which represent solutions to a problem and are directly executable by a computer. The programs are created and altered by a program in a higher level language such as "C" which is not directly executable, but requires translation into executable machine code through compilation, interpretation, translation, etc. The entities are initially created as an integer array that can be altered by the program as data, and are executed by the program by recasting a pointer to the array as a function type. The entities are evaluated by executing them with training data as inputs, and calculating fitnesses based on a predetermined criterion. The entities are then altered based on their fitnesses using a machine learning algorithm by recasting the pointer to the array as a data (e.g. integer) type. This process is iteratively repeated until an end criterion is reached. The entities evolve in such a manner as to improve their fitness, and one entity is ultimately produced which represents an optimal solution to the problem. Each entity includes a plurality of directly executable machine code instructions, a header, a footer, and a return instruction. The instructions include branch instructions which enable subroutines, leaf functions, external function calls, recursion, and loops. The system can be implemented on an integrated circuit chip, with the entities stored in high speed memory in a central processing unit.

A Modeling, Design, Analysis, Simulation, and Evaluation (MDASE) aspects of gyrocompassing in relation to Far-Target Location (FTL) systems include a Gyrocompass Modeling and Simulation System (GMSS). The GMSS is a modularized software system which has four major components: the 6DOF Motion Simulator, the IMU Sensor Simulator, the Gyrocompass System and Calibration Process Simulator, the Gyrocompass System Evaluation and Analysis Module. Each module has one or two graphic user interfaces (GUIs) as user interfaces for simulation components selection and parameter setting. The modular architecture of GMSS makes it very flexible for programming and testing. And, the component-based software development technology greatly eases system extension and maintenance. The simulators can be used as either an off-line tool or as a real-time simulation tool. The realization of the GMSS can be based on any computer platforms, for it is written in high level language and tools and is portable. The stochastic signal analysis and sensor testing and modeling tools comprise a suite of generic statistical analysis software, including Allan Variance and PSD analysis tools, which are available to every GMSS module and greatly enhanced the system functionality.

An intelligent framework is provided that is disposed between a high-level language environment and a database system environment. According to one embodiment, the framework programmatically receives information regarding definitions of data structures of objects participating in a software application and information regarding relationships among the objects. Based upon the particular request from the high-level language environment and upon the definitions and relationships, the framework programmatically and dynamically generates appropriate statements associated with the database system environment that accomplish the request. For example, the framework may issue statements to define the structure of a database, access information from the database, and / or manipulate information within the database.

A network processor has numerous novel features including a multi-threaded processor array, a multi-pass processing model, and Global Packet Memory (GPM) with hardware managed packet storage. These unique features allow the network processor to perform high-touch packet processing at high data rates. The packet processor can also be coded using a stack-based high-level programming language, such as C or C++. This allows quicker and higher quality porting of software features into the network processor. Processor performance also does not severely drop off when additional processing features are added. For example, packets can be more intelligently processed by assigning processing elements to different bounded duration arrival processing tasks and variable duration main processing tasks. A recirculation path moves packets between the different arrival and main processing tasks. Other novel hardware features include a hardware architecture that efficiently intermixes co-processor operations with multi-threaded processing operations and improved cache affinity.

A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model (LIM) from the HLL program, wherein the LIM specifies a plurality of state resources and determining a first and last access to each of the plurality of state resources. The method further can include identifying a plurality of processing stages from the LIM, wherein each processing stage is defined by the first and last access to one of the plurality of state resources. A stall point can be included within the LIM for each of the first accesses. The LIM can be translated into a scheduled hardware description specifying the multi-staged hardware implementation.

A method for advantageously translating high-level language codes for data processing using a reconfigurable architecture, memories addressable internally from within said reconfigurable architecture, and memories external to said reconfigurable architecture, may include constructing a finite automaton for computation in such a way that a complex combinatory network of individual functions is formed, assigning memories to the network for storage of operands and results, and separating external memory accesses for providing a transfer of at least one of operands and results as data from an external memory to a memory addressable internally by the reconfigurable architecture.

Optionally-mixed highly representative real time simulation of at least part of an avionics system (2). The simulation provides at least a step of translating communications interfaces into the form of models encoded in high level language on the basis of formal files in mark-up language; and dynamically managing descriptions that provide for grouping together, updating, and sharing a database that, for each piece of equipment, incorporates signals that transit via its input and / or output interfaces.

The present invention is directed to a method and system for translating a high-level language (HLL) code such as C, C++, Fortran, Java or the like into a HDL code such as Verilog or VHDL which requires no modification in the original HLL source code, while supporting a cross call between software and hardware, and even recursive calls in hardware. The system includes: a HLL-to-HLL source translator which reads user programming directive from a translation-targeted high-level language code marked with the user directive, and separates the translation-targeted high-level language code into a hardware code part and a software code part; a main compiler which compiles the software code part; a HLL-to-HDL translator which includes the front-end and middle-end of the main compiler and a HDL backend; a main core which executes the compiled software code part; and a dedicated hardware which executes the HDL code.

A method of porting a video game or other application from one platform to another involves decompiling the game executable to develop source code in a high level programming language such as C. The (re)generated source code is re-linked using target native libraries to handle hardware functions (e.g., video, audio, etc.) for the target platform. The resulting “trans-compiled” executable is able to efficiently run on the target platform, potentially providing orders of magnitude speed performance boost over other traditional techniques.

A system and a method are disclosed for communicating between two programming languages on a client device. Commands in a high-level language are encoded as character string containing a series of numbers separated by delimiters, with each component of the command encoded as a different number. The encoded character strings are passed to compiled code that runs natively on the client device, and the native code decodes the character strings into corresponding native commands and executes the native commands. This communication protocol allows applications written in high-level code to perform functions that are typically set aside for native code, such as communicating with web servers and modifying files saved in memory. High-level code may also be transferred to client devices without being subjected to the restrictions that some operating systems place on the transfer for application binaries, which allows application developers to automatically send application updates to users.

The invention discloses an underwater target three-dimensional reconstruction method based on line structured light. The method includes the following steps that a, an underwater two-dimensional image including depth information is acquired; b, enhancement processing is conducted on the underwater two-dimensional image; c, noise reduction processing is conducted on the two-dimensional image acquired in the step b; d, image edge detecting and image shape processing are carried out on the two-dimensional image acquired in the step c, and the center of each laser streak is extracted; e, the two-dimensional image acquired in the step d is calibrated; f, three-dimensional coordinates are acquired from the two-dimensional image acquired in the step e; g, the three-dimensional coordinates are reconstructed through computer high-level programming languages, namely visual underwater target three-dimensional information is obtained. By means of the underwater target three-dimensional reconstruction method based on line structured light, the influence on detecting precision because of suspended matter in water, light absorbing and scattering by seawater, uneven light fields and the like can be effectively lowered, wide-angle and long-distance underwater target three-dimensional information extraction is achieved, and underwater long-distance high-precision real-time target three-dimensional detection is realized.

The invention provides a programming model oriented to a neural network heterogeneous computing platform. Specifically, the invention provides a compiling method and system of a heterogeneous computing platform and a program running support method and system thereof. A trained neural network model is input to a neural network (NN) optimization complier to generate a NN assembling file corresponding to the NN. The NN assembling file is input to a NN assembler to generate a NN binary file corresponding to the neural network; a host complier tool chain is used for compiling and assembling a neural network application program developed by a user by using the high-level language, and orderly generates a corresponding host assembling file and a host binary file. The host linker is used for linking the NN binary file and the host binary file to generate a single mixed link executable file. The technical scheme provided by the invention has the features of being good in calculation performance, strong in expandability, strong in compatibility and high in flexibility.

The invention discloses a structural finite-element parametric modeling method applicable to a grating-configuration rudder surface. According to the method, a mapping transformation method based on a finite element model and a parametric approach to achieving conversion from two-dimensional mesh parameterization division to three-dimensional appearance expansion are adopted. The method includes the steps of specifically conducting two-dimensional plane projection on the grating-configuration rudder surface, extracting characteristic parameters, and conducting two-dimensional parameterization division; building a mapping relation between a two-dimensional finite element mesh and a three-dimensional finite element mesh, designing a numbering rule for finite element mesh points, and achieving conversion from the two-dimensional mesh to the three-dimensional appearance expansion; by means of a high-level computer language program, implementing the structural finite-element parametric modeling procedures for the grating-configuration rudder surface. By using the method, in a conceptual design phase or a preliminary design phase, the structural modeling efficiency can be greatly increased, the costs of time and manpower are low, parameters of self-compiled programs can be adjusted quickly, analysis applicability is high, the obtained model is applicable to analytical calculation of structural vibration, structural dynamics and the like, and the method is applicable to grating-configuration rudder surfaces and grating-configuration airfoils.

One or more machine code entities such as functions are created which represent solutions to a problem and are directly executable by a computer. The programs are created and altered by a program in a higher level language such as "C" which is not directly executable, but requires translation into executable machine code through compilation, interpretation, translation, etc. The entities are initially created as an integer array that can be altered by the program as data, and are executed by the program by recasting a pointer to the array as a function type. The entities are evaluated by executing them with training data as inputs, and calculating fitnesses based on a predetermined criterion. The entities are then altered based on their fitnesses using a machine learning algorithm by recasting the pointer to the array as a data (e.g. integer) type. This process is iteratively repeated until an end criterion is reached. The entities evolve in such a manner as to improve their fitness, and one entity is ultimately produced which represents an optimal solution to the problem. Each entity includes a plurality of directly executable machine code instructions, a header, a footer, and a return instruction. The alteration process is controlled such that only valid instructions are produced. The headers, footers and return instructions are protected from alteration. The system can be implemented on an integrated circuit chip, with the entities stored in high speed memory in a central processing unit.

An integrated circuit modeling method 100 implementable on computer, which has an executable software model 145 having modules 140 of reusable functional cores 105 coded in a high level language and a virtual platform of the integrated circuit employable in an architecture exploration step 115. A modeling library of modules coded in high level languages and hardware level languages are provided and instantiated according to user input in a functional verification step 120 having a co-simulation environment, with interface code 170 between modules automatically generated by an interface generator 130 based on a two dimensional data array of hardware specification inputs 205, the interface code 170 further interfacing with wrappers engaged between high and hardware level language modules.