1717results about "Detecting faulty computer hardware" patented technology

The invention relates to the technical field of deconcentrator testing, and discloses a multifunctional deconcentrator testing method, device and equipment and a storage medium, and the method comprises the steps: dividing a multifunctional deconcentrator into a central processing area, a USB interface area, a card reader interface area, a charging circuit area and a lithium battery area, performing temperature data acquisition on the multifunctional deconcentrator in a working state to obtain multi-point temperature time sequence data; performing nonlinear thermal dynamic feature extraction on the multi-point temperature time sequence data to obtain a fusion feature vector, and performing two-dimensional temperature field reconstruction based on the fusion feature vector to obtain a target temperature distribution diagram; performing operation test on the multifunctional deconcentrator according to the target temperature distribution diagram to obtain a temperature response curve; according to the method, the problem that a traditional method is insufficient in hot spot area recognition is solved, accurate reconstruction of a whole surface temperature field is achieved, and the test accuracy of the multifunctional deconcentrator is improved.

The invention discloses a board card testing method, electronic equipment and a storage medium, and relates to the technical field of servers, and the method comprises the steps: obtaining parameter information of a to-be-tested board card, and calculating a matching degree value of an interface of the to-be-tested board card and a board card interface in a first preset rule base; the characteristics of the to-be-tested board card are accurately identified, the target control script of the board card test fixture suitable for the to-be-tested board card is determined, it is ensured that the matched script is used when the board card test fixture is connected with the to-be-tested board card, and the damage risk caused by version mismatching is avoided to a certain extent; meanwhile, the board card testing jig determines the target testing task according to the parameter information of the board card to be tested and executes testing, and automation and precision of the testing process are achieved. Therefore, the problems that the test accuracy is reduced and the security risk is increased due to the fact that the version change information is not transmitted in time or inaccurately are effectively solved, the dependence on manual checking of engineers is reduced, the working efficiency is improved, and the test accuracy and security are remarkably improved.

The invention discloses a bus module self-recovery method and device, equipment and a storage medium. According to the invention, the communication state of the bus module is monitored in real time, and the abnormal detection signal is identified; when an abnormal detection signal is identified, the fault type is automatically diagnosed; dynamically selecting and combining an optimal recovery strategy according to the fault type; executing a self-recovery operation corresponding to the recovery strategy, and verifying a recovery effect; if the recovery fails, automatically adjusting and executing the recovery strategy of the next priority according to the fault type and the failure frequency; isolating communication between the fault bus module and other normal modules through a bus arbitration mechanism; recording fault features and a recovery process, and generating historical data for subsequent fault prediction; and if recovery fails for multiple times, triggering a system-level security protection mechanism, and giving an alarm. According to the method, the fault type can be quickly and accurately identified, the optimal recovery strategy is selected in a targeted manner, and the system maintainability and safety of the bus module system are effectively improved.

The invention provides a notebook computer pre-installed environment simulation test method and system based on a virtualization technology, and the method comprises the steps: firstly creating a virtualization environment instance which is matched with a target notebook computer hardware architecture and comprises a pre-installed operation system and a preset software set, and then injecting a simulation user operation behavior sequence according to a predefined environment configuration strategy, the method comprises the steps of generating a dynamic test case set, executing and monitoring running state data in a virtual environment instance, generating an environment compatibility analysis report by extracting an abnormal response mode in the running state data, and finally adjusting resource configuration parameters of the virtual environment instance according to the environment compatibility analysis report. And generating the optimized pre-installed environment mirror image file, so that efficient and comprehensive simulation test on the notebook computer pre-installed environment is realized, and the test efficiency and accuracy are effectively improved.

To provide a computer hardware inspection table and an inspection system that make it difficult for computer hardware to move spontaneously during inspection and do not affect the inspection effect of computer hardware. 【Solution means】On the inspection table 7, a slide groove 8 and a placement groove 15 are provided on the side surface. A guide rod 9 is provided in the slide groove. A spring 10 and a moving plate 11 are fitted on the surface of the guide rod. One end of the moving plate is provided with a clamping plate 12. A moving groove 13 is opened on the side surface of the clamping plate. A position limiting block 14 is provided in the moving groove. When inspecting computer hardware, pull the position limiting block to remove the position limiting block from the placement groove, move one clamping plate, then place the hardware on the surface of the inspection table, release one clamping plate, and cooperate with the installation of the clamping plate and another clamping plate and the elastic force of the spring to clamp the hardware. Move the position limiting block and engage it in another placement groove to position and fix the hardware.

The invention provides a hard disk testing method and device, equipment and a storage medium, and can be applied to the technical field of hard disk testing. The hard disk test method comprises the steps that in response to a received test request for a target hard disk, a target error injection instruction matched with a target sector in the target hard disk is executed, and the target error injection instruction is used for injecting a logic error into the target sector; writing first preset data into the target sector under the condition of determining that the execution of the target error injection instruction is completed; when it is determined that the bad sector information of the target hard disk indicates that the target sector is a bad sector, according to the mapping relation between the sector of the target hard disk and the standby sector, executing a read operation on the target standby sector having the mapping relation with the target sector to obtain first read data; and comparing the first read data with first preset data, and determining a first test result for the target hard disk.

The invention discloses a computer board card testing method and system, and relates to the technical field of computer board card testing, the system comprises a central server and at least one intelligent test fixture, the model of a to-be-tested board card is identified through the intelligent test fixture to obtain test information, and the test information is sent to the central server; and the central server determines a parallel test program corresponding to each to-be-tested board card according to the test information, and performs a synchronous test on each to-be-tested board card by running the parallel test program to obtain a test result corresponding to each to-be-tested board card. In the process, the model of the to-be-tested board card is automatically identified through the intelligent test fixture, the test program is automatically determined through the central server, automation of the test process is achieved, the problem of low efficiency caused by manual operation is avoided, and meanwhile, the test efficiency of the computer board card is improved by synchronously testing multiple to-be-tested board cards.

The invention relates to an SOC chip performance test device, method and equipment and a readable storage medium. In the device, an upper computer is used for sending an excitation instruction to a voltage simulator and sending a test instruction to a signal generator according to a test requirement; the voltage simulator is used for inputting a voltage excitation signal to the test board according to the excitation instruction; the signal generator is used for inputting a test signal to the test board according to the test instruction; the test board is used for conditioning the voltage excitation signal and the test signal and sending a first conditioning signal to the SOC chip to be tested so as to indicate the SOC chip to be tested to respond to the first conditioning signal; the test board is also used for acquiring a response signal returned by the SOC chip to be tested, conditioning the response signal, and returning a second conditioning signal to the upper computer; and the upper computer is also used for analyzing the second conditioning signal to obtain a performance test result. The SOC chip performance test efficiency can be improved.

The invention discloses a resource management method and device, equipment and a medium, and relates to the technical field of storage, the resource management method comprises the following steps: carrying out performance test and data analysis on different storage architectures according to an I / O path of a distributed storage system and an asynchronous programming model, and determining processor static parameters under the different storage architectures according to the results of the performance test and the data analysis; the method comprises the following steps: collecting performance indexes of a distributed storage system through an asynchronous programming model, predicting load change conditions of the system according to the performance indexes of the distributed storage system, and dynamically adjusting processor resources according to the load change conditions of the system; managing a large-page memory pool and a cache according to the large-page memory management model and the business model type of the distributed storage system; and optimizing a memory application and release mechanism in the storage service of the distributed storage system. Through dynamic scheduling of processor resources and a large-page memory pool data sharing mechanism, balanced allocation of storage and calculation resources is realized, and the system performance and the resource utilization rate are improved.

The invention discloses a chip testing method and device, equipment, a storage medium and a program product. The method comprises the steps of obtaining structured description data based on a standard test description file of a first chip, wherein the standard test description file is used for describing a test requirement of the first chip; the structured description data is injected into an environment template to obtain a verification environment, the verification environment is a program used for bearing chip test logic, and the environment template is a preset test logic program framework; the first chip is driven and tested based on the verification environment, the chip test result is obtained, the test requirements of different chips can be met only through parameter injection of the structured description data, the full-automatic chip test process can be achieved, and the chip test efficiency is improved.

The invention relates to the technical field of data processing, in particular to an automatic test method, system and device for a digital card, and the method comprises the steps: determining test information for the digital card; starting a PC agent and an APP agent, and enabling the PC agent and the APP agent to be connected with the test service; wherein the PC agent is deployed at a computer end and is used for receiving a test instruction of a test service and forwarding the test instruction to the card reader, and the APP agent is deployed at a to-be-tested equipment end and is used for receiving the test instruction of the test service and forwarding the test instruction to a security chip of the to-be-tested equipment; determining a target PC agent and a target APP agent; acquiring a test instruction through a business service based on the test information, sending the test instruction to the card reader and the to-be-tested device end through the target PC agent and the target APP agent for testing, and acquiring feedback data through the target PC agent and the target APP agent; and generating a test report based on the feedback data. Therefore, the test of the digital card can be automatically and efficiently realized.

The invention discloses a test link abnormity positioning device, system, method, equipment, medium and program, and relates to the technical field of computers, and the method comprises the steps that when a test link is abnormal, a processing component writes a first enabling bit into a first register of each node device, each node device responds to the first enabling bit to enter a low-power-consumption mode, and the first enabling bit enters a low-power-consumption mode; according to the embodiment of the invention, each node device triggers link retraining in the low-power-consumption mode to expose the unstable position of the test link in the low-power-consumption conversion process, and determines the abnormal position of the link according to the flag bit state of the second register, so that the troubleshooting efficiency and the abnormality positioning precision are improved, and the time and the labor cost are saved. Therefore, the problems of low working efficiency and high time and labor cost caused by the fact that the abnormal problem cannot be effectively solved in time when the abnormal position of the link is checked manually in the prior art are solved.

The embodiment of the invention provides a test unit, a processor, a system on chip and a test method. The test unit comprises a bus slave interface, an input buffer and a controller, the bus slave interface is used for receiving scanning input data sent by the bus master interface through a functional high-speed bus and storing the scanning input data into the input buffer; the controller is used for reading the scanning input data from the input buffer, sending the scanning input data to a to-be-tested processor core so as to carry out on-line scanning testing on a to-be-tested processor, obtaining scanning output data from the to-be-tested processor, and sending the scanning output data to the to-be-tested processor core so as to carry out on-line scanning testing on the to-be-tested processor. Sending a test result to the bus slave interface according to the scanning output data; and the bus slave interface is used for sending the test result to the bus master interface through the functional high-speed bus. According to the scheme, the online scanning test efficiency of the processor core can be improved.

The invention discloses a UVM-based end-to-end random verification method for a complex bus interconnection bridge, and relates to the field of communication verification, and the method comprises the steps: building a verification environment based on a UVM, connecting a corresponding bus protocol master VIP containing a driver and a monitor to each slave interface of the bus interconnection bridge, connecting a corresponding bus protocol slave VIP containing a driver and a monitor to each master interface, and connecting the corresponding slave VIP containing a driver and a monitor to each slave interface of the bus interconnection bridge; a master VIP driver is used for sending read-write request excitation which carries the slave interface identity information and is carried by a sideband signal; a verification environment based on a UVM is established, excitation carrying slave identity information is sent through a VIP driver, data are packaged through a monitor and are distributed to a reference model and a scoreboard, meanwhile, the reference model is subjected to decoding routing according to a preset array, the scoreboard is matched with queue elements in sequence, and the functions of reserved queue grading processing, outsourcing characteristic directional coverage and timestamp calibration are further arranged. And multi-scene high-load simulation and error positioning are supported.

The invention provides a hard disk fault prediction method based on multi-view feature balance learning, and the method comprises the steps: comprehensively capturing the short-term abnormality, long-term trend change and distribution offset conditions of the health state of a hard disk through constructing original features, histogram statistical features and bulldozer distance-based distribution offset features; efficient fusion and deep representation learning of multi-view hard disk features are realized through the synergistic effect of a parallel encoder and a cross encoder; through a batch balance sampling strategy, samples with different difficulties are displayed in each training batch in a balanced manner, the rapid learning ability of the model for easily classified samples is ensured, and complex sample features are ensured to be concerned at the initial stage of model learning, so that the generalization performance and robustness of the whole model on the samples with different difficulties are improved, and the training efficiency is improved. The method is especially suitable for industrial prediction scenes with sample heterogeneity, such as hard disk fault prediction.

The invention relates to the technical field of integrated circuits, and provides a dynamic voltage frequency configuration method, device, equipment and program product of a chip, and the method comprises the steps: for each chip in a sample set comprising a plurality of chips, determining a performance index based on a chip parameter and a preset test frequency; comparing the performance index of each chip with a preset limit value to determine the number of chips passing the test; based on the number of the chips passing the test and the total number of the chips in the sample set, determining the actual yield under the preset test frequency; comparing the actual yield with a target yield, and iteratively adjusting the preset test frequency until the target yield is met so as to obtain an effective clock frequency; a voltage frequency table is generated based on the effective clock frequency and the corresponding voltage. According to the method, the relationship between the effective clock frequency and the yield is fully reflected, the generated voltage frequency table can provide the optimal working parameter combination for the chip under the condition of ensuring the yield, and the performance and efficiency of chip design are improved.

The invention relates to the technical field of vehicle gauge function safety design, and discloses a function safety design method of an Online NDT for sram, which comprises an NDT controller comprising an Intfctrl module, two NDTCTRL modules, a Compare module, an Arbitintf module and an Arbit module. The CPU is used for managing the NDT controller and reading information through the APB, and meanwhile, various Master accesses the SRAM after passing through the Arbit module through the AXI; the mutual redundancy of the two NDTCTRL modules is realized; the Compare module is used for supporting error injection and result comparison; and the Arbit module is responsible for arbitrating access requests from the NDTCTRL and the AXI, so that the Online NDT test does not influence the bandwidth of the SRAM interface or occupies part of the bandwidth. According to the function safety design method for the Online NDT of the sram, mutual redundant Online NDT design is utilized on the overall architecture, an error injection mechanism is supported, and a Lock Step Logic front-back staggered configuration three-level register and phase inverter mechanism is adopted, so that the whole design is safer, more flexible and more reliable.

The invention relates to the technical field of data storage, and discloses a solid state disk compatibility testing method which comprises the following steps: after a solid state disk is started, automatically collecting basic performance information of the solid state disk based on a Python script and generating a standardized log file; running performance operation of the solid state disk in a preset time period, and simultaneously executing multi-user or multi-task concurrent test operation based on the automated script; a script is used for calling a system startup command or a shutdown command, the next startup process is automatically triggered after shutdown, a startup and shutdown cycle test mechanism is formed, and the startup time, the initialization duration and the abnormal interruption record of the solid state disk are synchronously collected in each startup and shutdown process; when the system runs, the Python script is used for safely removing and reinserting the solid state disk. The problem that an existing test method is narrow in platform coverage range is solved.

The invention discloses an intelligent service starting arrangement system based on container life cycles, and particularly relates to the field of containerized starting service management. Comprising an arrangement control layer, a pre-detection layer and a life cycle management layer. The arrangement control layer comprises a starting manager module, a dependency relationship analysis sub-module, an arrangement strategy control sub-module and a starting sequence scheduling sub-module; the pre-detection layer comprises a multi-dimensional pre-detection engine, a port availability detection sub-module, a database connection verification sub-module, a configuration integrity verification sub-module and a resource ready state check sub-module. The life cycle management layer comprises a container life cycle monitoring module, a construction stage management sub-module, an operation state tracking sub-module and a stop process control sub-module. A multi-dimensional pre-detection engine, DAG-based complex dependency relationship management, intelligent fault classification and adaptive recovery, container life cycle full-stage perception and dynamic starting of an arrangement strategy are realized.

The invention provides an SOC array server test and image reconstruction method. According to the method, in response to an obtained test request instruction, at least two SOC chips to be tested are divided into a sending chip set and a receiving chip set, the number of chips in the sending chip set corresponds to the number of chips in the receiving chip set, and manual configuration of related information is avoided; on this basis, according to the pre-acquired test request, each sending chip in the sending chip set is called, and the test data packet is sent to the corresponding receiving chip in the receiving chip set, so that an external streaming server is not needed, and only the SOC chip to be tested can be tested, the security of the test process is improved, and the test efficiency is improved. The related information of the SOC chip to be tested is prevented from being manually configured, so that the resource waste is reduced to a certain extent.

The embodiment of the invention provides an interface testing method and device, electronic equipment and a storage medium. The method comprises the following steps: executing static code analysis on a to-be-tested system to obtain a code interface list, and executing dynamic flow analysis on the to-be-tested system to obtain a flow interface list; determining an interface document of the to-be-tested system, and analyzing the interface document through a pre-trained large language model to obtain a document interface list; and respectively testing the document interface list through the code interface list and the flow interface list to obtain a test result. According to the scheme, the interface document is analyzed through the large language model, various formats can be compatible, the compatibility of the interface document is improved, and therefore the test accuracy is improved.

The invention discloses a fault processing system, method and device and a storage medium, and relates to the technical field of servers, and the method comprises the steps: obtaining a configured fault processing strategy through a basic input and output system; in response to fault interruption triggered by a hardware fault occurring in the system, acquiring fault information corresponding to the hardware fault by using the basic input / output system; a target fault processing strategy of the fault information is determined based on the fault processing strategy through the basic input and output system, fault processing is carried out based on the target fault processing strategy, and fault processing information is generated; the method comprises the following steps: receiving fault processing information sent by a basic input / output system through a baseboard management controller, and analyzing the fault processing information to generate a corresponding event log; according to the invention, the fault processing difficulty is reduced, and the stability and reliability of a computer system are ensured.

A maintenance system for a medical device includes a user device configured to communicate with the medical device and execute maintenance tasks on the medical device and communicate with a user via a user interface of the user device or the medical device. The maintenance tasks may be executed by either device or both devices, and communication with a user may occur via a user interface of either device or both devices. The system may also include a server configured to communicate with one or both of the user device and the medical device. The maintenance tasks may include an electrical safety check, a physical check, a performance check, and a functional check. Examples of functional checks include validation of a transient current detector and a thermal cutout.

The invention relates to a mainboard debugging circuit and method compatible with an LPC bus and an eSPI bus. The debugging circuit comprises a mainboard connecting module, a main control module and a protocol mode control module. A signal input end of the mainboard connection module is connected with a debugging bus of a mainboard to be tested, a multiplexing signal pin group of the main control module is connected with a signal output end of the mainboard connection module, and the multiplexing signal pin group is used for multiplexing between an LPC bus signal mode and an eSPI bus signal mode; the protocol mode control module is used for generating a corresponding protocol mode selection signal according to the bus state data, so that the main control module is switched between an LPC bus signal mode and an eSPI bus signal mode; the problems that an existing debugging card needs to be switched manually and wiring is complex are solved, the debugging card can be compatible with mainboard signal standards of different architectures, and therefore multi-protocol self-recognition and sharing of the hardware level are achieved, debugging efficiency is improved, the misconnection risk is reduced, and the mainboard space layout is remarkably optimized.

The invention relates to the technical field of interface circuits, in particular to a multi-mode switching detection circuit for a Type-C interface, which is used for realizing peripheral type identification and automatic switching between a USB host mode and a DP input mode on a single Type-C interface. The circuit comprises an interface detection unit connected with a Type-C female seat interface, a voltage comparison unit, a main control processor chip, a mode discrimination unit and a control output unit. The voltage comparison unit carries out resistance voltage division and threshold comparison on CC pin voltage, two levels are formed at a detection node and sent to the main control processor chip, and USB equipment and DP source equipment are distinguished by the mode judgment unit. The control output unit controls the USB host power supply control circuit and the DP input chip power supply circuit, establishes a USB data channel in a USB host mode, and establishes a DP-to-video channel in a DP input mode. The circuit realizes rapid peripheral identification and mode automatic switching based on hardware, and is simple in structure, low in cost, high in response speed and high in system stability.

The invention discloses a mainboard function automatic detection method and device, and relates to the technical field of computer hardware detection. The method comprises: receiving a user instruction through a graphical interface to generate a test queue; distributing an independent thread for each test item to execute hardware detection, and dynamically mapping the position of a physical port; analyzing a test state in real time and updating interface feedback; comparing the actual hardware parameters with preset parameters; and hot update of the test script is supported. The device comprises a graphical interface module, a multi-thread execution engine, a scripted hardware detection module and the like. The mainboard function detection device can perform efficient, automatic and visual detection on the mainboard function, and is suitable for quality control of mainboard production, maintenance and research and development links.

The invention relates to the technical field of electronic testing, and discloses a USB module multi-station synchronous testing and data association method and system, and the method comprises the steps: constructing a global schedulable resource map of a testing station, so as to create a resource load balancing table and a global testing database of the testing station; configuring a synchronous test controller of the test station by using the test task flow generated by the test station and the global schedulable resource atlas; reading the unique identity label of the USB module so as to establish an association mapping network of the USB module in the global test database; and executing multi-station synchronous testing and data association processing of the USB module based on the global schedulable resource atlas, the resource load balancing table, the synchronous testing controller, the collaborative optimization strategy set and the association mapping network. According to the invention, accurate synchronous control of multi-station test and automatic correlation analysis of test data can be realized.

One or more computing devices, systems, and / or methods for visual troubleshooting a network device setup. Images of the network device setup are provided to the system. A GenAI component processes the images to generate one or more device identifying features. The features are further processed to identify the device. The system utilizes hardware-specific information to prompt the GenAI component to answer troubleshooting-related questions concerning the device setup. The images may be pre-processed to include one or more visual guides to assist the GenAI component.

The invention provides a communication system and a communication method used between multiple nodes and I2C equipment, and relates to the technical field of servers. The system is arranged in I2C equipment and comprises a CPLD (Complex Programmable Logic Device) module, a multiplexing switch module and a plurality of connectors, and the connectors are connected with a BMC (Baseboard Management Controller) and the CPLD module of a node to form a direct connection channel of the BMC and the CPLD; the multiplexing switch module is connected with the CPLD module, and the connector is also connected with I2C equipment through the multiplexing switch module; the CPLD module receives a permission request instruction of a multi-node BMC to an I2C bus through a direct connection channel, generates a channel selection instruction for indicating to gate a channel between a target BMC and I2C equipment, and sends the instruction to the multiplexing switch module; and the multiplexing switch module only gates the communication connection between the target BMC and the I2C equipment based on the instruction, so that the problem of I2C bus abnormity caused by communication arbitration of a plurality of BMCs is effectively avoided.

The utility model discloses a hard disk testing machine capable of synchronizing and patrolling and detecting, which belongs to the technical field of computer testing devices and comprises a casing and a switching power supply, a testing area and an operating area are arranged in the casing, a plurality of computer modules and hard disks are arranged in the testing area, and the operating area is provided with an input module and a display screen. The side wall of the shell is provided with a power supply insertion port, and the switching power supply is inserted into the power supply insertion port; the switching power supply comprises a power supply shell and a plugging clamping assembly, the plugging clamping assembly comprises an elastic piece and a clamping protrusion, one end of the elastic piece penetrates through the power supply shell and then is connected with the inner wall of the power supply shell, the other end of the elastic piece is located outside the power supply shell, and the clamping protrusion is connected with the elastic piece. And when the other end of the elastic sheet is pressed and moves downwards relative to the power supply shell, the clamping bulge is driven to retract into the power supply shell from the outside of the power supply shell. According to the hard disk testing machine capable of synchronizing and patrolling and detecting, the problem that a switching power supply of an existing hard disk testing machine is not convenient for maintenance personnel to replace or maintain is solved.