1096results about "Detecting faulty computer hardware" patented technology

The invention relates to an SOC chip performance test device, method and equipment and a readable storage medium. In the device, an upper computer is used for sending an excitation instruction to a voltage simulator and sending a test instruction to a signal generator according to a test requirement; the voltage simulator is used for inputting a voltage excitation signal to the test board according to the excitation instruction; the signal generator is used for inputting a test signal to the test board according to the test instruction; the test board is used for conditioning the voltage excitation signal and the test signal and sending a first conditioning signal to the SOC chip to be tested so as to indicate the SOC chip to be tested to respond to the first conditioning signal; the test board is also used for acquiring a response signal returned by the SOC chip to be tested, conditioning the response signal, and returning a second conditioning signal to the upper computer; and the upper computer is also used for analyzing the second conditioning signal to obtain a performance test result. The SOC chip performance test efficiency can be improved.

The invention discloses a resource management method and device, equipment and a medium, and relates to the technical field of storage, the resource management method comprises the following steps: carrying out performance test and data analysis on different storage architectures according to an I / O path of a distributed storage system and an asynchronous programming model, and determining processor static parameters under the different storage architectures according to the results of the performance test and the data analysis; the method comprises the following steps: collecting performance indexes of a distributed storage system through an asynchronous programming model, predicting load change conditions of the system according to the performance indexes of the distributed storage system, and dynamically adjusting processor resources according to the load change conditions of the system; managing a large-page memory pool and a cache according to the large-page memory management model and the business model type of the distributed storage system; and optimizing a memory application and release mechanism in the storage service of the distributed storage system. Through dynamic scheduling of processor resources and a large-page memory pool data sharing mechanism, balanced allocation of storage and calculation resources is realized, and the system performance and the resource utilization rate are improved.

The invention discloses a UVM-based end-to-end random verification method for a complex bus interconnection bridge, and relates to the field of communication verification, and the method comprises the steps: building a verification environment based on a UVM, connecting a corresponding bus protocol master VIP containing a driver and a monitor to each slave interface of the bus interconnection bridge, connecting a corresponding bus protocol slave VIP containing a driver and a monitor to each master interface, and connecting the corresponding slave VIP containing a driver and a monitor to each slave interface of the bus interconnection bridge; a master VIP driver is used for sending read-write request excitation which carries the slave interface identity information and is carried by a sideband signal; a verification environment based on a UVM is established, excitation carrying slave identity information is sent through a VIP driver, data are packaged through a monitor and are distributed to a reference model and a scoreboard, meanwhile, the reference model is subjected to decoding routing according to a preset array, the scoreboard is matched with queue elements in sequence, and the functions of reserved queue grading processing, outsourcing characteristic directional coverage and timestamp calibration are further arranged. And multi-scene high-load simulation and error positioning are supported.

The invention relates to the technical field of integrated circuits, and provides a dynamic voltage frequency configuration method, device, equipment and program product of a chip, and the method comprises the steps: for each chip in a sample set comprising a plurality of chips, determining a performance index based on a chip parameter and a preset test frequency; comparing the performance index of each chip with a preset limit value to determine the number of chips passing the test; based on the number of the chips passing the test and the total number of the chips in the sample set, determining the actual yield under the preset test frequency; comparing the actual yield with a target yield, and iteratively adjusting the preset test frequency until the target yield is met so as to obtain an effective clock frequency; a voltage frequency table is generated based on the effective clock frequency and the corresponding voltage. According to the method, the relationship between the effective clock frequency and the yield is fully reflected, the generated voltage frequency table can provide the optimal working parameter combination for the chip under the condition of ensuring the yield, and the performance and efficiency of chip design are improved.

The invention relates to the technical field of data storage, and discloses a solid state disk compatibility testing method which comprises the following steps: after a solid state disk is started, automatically collecting basic performance information of the solid state disk based on a Python script and generating a standardized log file; running performance operation of the solid state disk in a preset time period, and simultaneously executing multi-user or multi-task concurrent test operation based on the automated script; a script is used for calling a system startup command or a shutdown command, the next startup process is automatically triggered after shutdown, a startup and shutdown cycle test mechanism is formed, and the startup time, the initialization duration and the abnormal interruption record of the solid state disk are synchronously collected in each startup and shutdown process; when the system runs, the Python script is used for safely removing and reinserting the solid state disk. The problem that an existing test method is narrow in platform coverage range is solved.

The invention discloses an intelligent service starting arrangement system based on container life cycles, and particularly relates to the field of containerized starting service management. Comprising an arrangement control layer, a pre-detection layer and a life cycle management layer. The arrangement control layer comprises a starting manager module, a dependency relationship analysis sub-module, an arrangement strategy control sub-module and a starting sequence scheduling sub-module; the pre-detection layer comprises a multi-dimensional pre-detection engine, a port availability detection sub-module, a database connection verification sub-module, a configuration integrity verification sub-module and a resource ready state check sub-module. The life cycle management layer comprises a container life cycle monitoring module, a construction stage management sub-module, an operation state tracking sub-module and a stop process control sub-module. A multi-dimensional pre-detection engine, DAG-based complex dependency relationship management, intelligent fault classification and adaptive recovery, container life cycle full-stage perception and dynamic starting of an arrangement strategy are realized.

The invention provides an SOC array server test and image reconstruction method. According to the method, in response to an obtained test request instruction, at least two SOC chips to be tested are divided into a sending chip set and a receiving chip set, the number of chips in the sending chip set corresponds to the number of chips in the receiving chip set, and manual configuration of related information is avoided; on this basis, according to the pre-acquired test request, each sending chip in the sending chip set is called, and the test data packet is sent to the corresponding receiving chip in the receiving chip set, so that an external streaming server is not needed, and only the SOC chip to be tested can be tested, the security of the test process is improved, and the test efficiency is improved. The related information of the SOC chip to be tested is prevented from being manually configured, so that the resource waste is reduced to a certain extent.

The embodiment of the invention provides an interface testing method and device, electronic equipment and a storage medium. The method comprises the following steps: executing static code analysis on a to-be-tested system to obtain a code interface list, and executing dynamic flow analysis on the to-be-tested system to obtain a flow interface list; determining an interface document of the to-be-tested system, and analyzing the interface document through a pre-trained large language model to obtain a document interface list; and respectively testing the document interface list through the code interface list and the flow interface list to obtain a test result. According to the scheme, the interface document is analyzed through the large language model, various formats can be compatible, the compatibility of the interface document is improved, and therefore the test accuracy is improved.

A maintenance system for a medical device includes a user device configured to communicate with the medical device and execute maintenance tasks on the medical device and communicate with a user via a user interface of the user device or the medical device. The maintenance tasks may be executed by either device or both devices, and communication with a user may occur via a user interface of either device or both devices. The system may also include a server configured to communicate with one or both of the user device and the medical device. The maintenance tasks may include an electrical safety check, a physical check, a performance check, and a functional check. Examples of functional checks include validation of a transient current detector and a thermal cutout.

The invention relates to a mainboard debugging circuit and method compatible with an LPC bus and an eSPI bus. The debugging circuit comprises a mainboard connecting module, a main control module and a protocol mode control module. A signal input end of the mainboard connection module is connected with a debugging bus of a mainboard to be tested, a multiplexing signal pin group of the main control module is connected with a signal output end of the mainboard connection module, and the multiplexing signal pin group is used for multiplexing between an LPC bus signal mode and an eSPI bus signal mode; the protocol mode control module is used for generating a corresponding protocol mode selection signal according to the bus state data, so that the main control module is switched between an LPC bus signal mode and an eSPI bus signal mode; the problems that an existing debugging card needs to be switched manually and wiring is complex are solved, the debugging card can be compatible with mainboard signal standards of different architectures, and therefore multi-protocol self-recognition and sharing of the hardware level are achieved, debugging efficiency is improved, the misconnection risk is reduced, and the mainboard space layout is remarkably optimized.

The invention relates to the technical field of interface circuits, in particular to a multi-mode switching detection circuit for a Type-C interface, which is used for realizing peripheral type identification and automatic switching between a USB host mode and a DP input mode on a single Type-C interface. The circuit comprises an interface detection unit connected with a Type-C female seat interface, a voltage comparison unit, a main control processor chip, a mode discrimination unit and a control output unit. The voltage comparison unit carries out resistance voltage division and threshold comparison on CC pin voltage, two levels are formed at a detection node and sent to the main control processor chip, and USB equipment and DP source equipment are distinguished by the mode judgment unit. The control output unit controls the USB host power supply control circuit and the DP input chip power supply circuit, establishes a USB data channel in a USB host mode, and establishes a DP-to-video channel in a DP input mode. The circuit realizes rapid peripheral identification and mode automatic switching based on hardware, and is simple in structure, low in cost, high in response speed and high in system stability.

The invention discloses a mainboard function automatic detection method and device, and relates to the technical field of computer hardware detection. The method comprises: receiving a user instruction through a graphical interface to generate a test queue; distributing an independent thread for each test item to execute hardware detection, and dynamically mapping the position of a physical port; analyzing a test state in real time and updating interface feedback; comparing the actual hardware parameters with preset parameters; and hot update of the test script is supported. The device comprises a graphical interface module, a multi-thread execution engine, a scripted hardware detection module and the like. The mainboard function detection device can perform efficient, automatic and visual detection on the mainboard function, and is suitable for quality control of mainboard production, maintenance and research and development links.

The invention relates to the technical field of electronic testing, and discloses a USB module multi-station synchronous testing and data association method and system, and the method comprises the steps: constructing a global schedulable resource map of a testing station, so as to create a resource load balancing table and a global testing database of the testing station; configuring a synchronous test controller of the test station by using the test task flow generated by the test station and the global schedulable resource atlas; reading the unique identity label of the USB module so as to establish an association mapping network of the USB module in the global test database; and executing multi-station synchronous testing and data association processing of the USB module based on the global schedulable resource atlas, the resource load balancing table, the synchronous testing controller, the collaborative optimization strategy set and the association mapping network. According to the invention, accurate synchronous control of multi-station test and automatic correlation analysis of test data can be realized.

One or more computing devices, systems, and / or methods for visual troubleshooting a network device setup. Images of the network device setup are provided to the system. A GenAI component processes the images to generate one or more device identifying features. The features are further processed to identify the device. The system utilizes hardware-specific information to prompt the GenAI component to answer troubleshooting-related questions concerning the device setup. The images may be pre-processed to include one or more visual guides to assist the GenAI component.

The invention relates to the technical field of server testing equipment, and discloses a controllable device applied to server backboard testing and a control method thereof.The controllable device comprises a master device and at least one slave device, the master device is connected with the slave device through an FPC flexible circuit board, the master device is used for receiving a testing instruction, and the slave device is used for receiving the testing instruction; and a control instruction is sent to the slave device according to the test instruction, and the slave device is used for executing the control instruction to realize connection and disconnection of the data link. The slave device is embedded into the data link based on the SAS protocol, link on-off is achieved through electronic control, traditional manual insertion and extraction operation is replaced, manual intervention is reduced, and full-process automatic testing is achieved. The device not only improves the test efficiency, but also avoids mechanical wear of interfaces such as SFF-8643, Slimline x4 and the like caused by physical plugging and unplugging, and avoids the risk of damage caused by low positioning precision of traditional equipment at the same time.

The invention relates to the technical field of integrated circuits, and provides a verification platform, a verification method, electronic equipment and a medium. The verification platform comprises: an application layer bus function level model comprising a customized interface for a to-be-tested design for interacting with the to-be-tested design, the to-be-tested design being a PCIe protocol docking and protocol compliance test suite, and the to-be-tested design being a PCIe protocol docking and protocol compliance test suite; the PCIe protocol docking and protocol compliance test suite supports a verification demand of a physical layer intellectual property core and a verification demand of protocol consistency of a PCIe controller and a physical layer subsystem level; and the to-be-tested design interacts with the application layer bus function level model through the customized interface. Thus, the integration and through-flow debugging cost of subsystem protocol consistency verification is reduced, the verification period of a docking test of PCIe subsystem protocol standardization is shortened, and the completeness of docking verification of a full quantization protocol of a PCIe subsystem and the platform reuse efficiency are improved.

The invention belongs to the technical field of server detection, and particularly relates to a server network function test method and system, a terminal and a storage medium, and the method comprises the steps: defining a test target, and configuring probe interface parameters and a resource scheduling strategy; the probe reports the CPU, the memory and the network interface utilization rate of the server to the control node in real time, and the control node adjusts the distribution of the test task by calculating the real-time load coefficient and the dynamic weight of the node according to the configured resource scheduling strategy; executing a multi-dimensional test based on the test points distributed after the test task is adjusted; through configuring a resource scheduling strategy in the step S1 and combining calculation of a node real-time load coefficient and a dynamic weight in the step S2, dynamic allocation of a test task is realized. When the node load reaches the threshold value, task migration is triggered according to the dynamic scheduling logic, resource waste caused by fixed node configuration is avoided, test resources are made to incline towards low-load nodes, the test period is remarkably shortened, and the resource utilization rate is increased.

The embodiment of the invention relates to the technical field of electronics, and discloses a universal hardware interface test system and method, a terminal, a medium and a product. In the invention, the universal hardware interface test system comprises the hardware service module and the data interaction module which are connected with each other, and the construction of the universal hardware interface test system is realized by using the two mutually independent modules, so that the universal hardware interface test system is divided into the two mutually independent modules, and the maintainability and the expandability of the system are improved; moreover, under the condition that the hardware service module is successfully connected with the to-be-tested hardware, the to-be-tested data is acquired through the hardware service module, the to-be-tested hardware is tested through the data interaction module according to the test instruction of the user, and the test result of the target test is generated, so that unified test on different hardware interfaces is realized, and the test efficiency is improved. Hardware in a project can be managed and verified in a centralized and unified mode conveniently, the efficiency of test verification is improved, and time needed by testing is saved.

The embodiment of the invention discloses an address translation backup buffer invalidation verification method and device and electronic equipment, relates to the technical field of integrated circuit verification, and aims to improve the verification integrity of a processor and further improve the performance of the processor. The method comprises the following steps: determining first invalidation verification information according to a write address in an invalidation microinstruction; the write address is the address of a specified register; determining second invalidation verification information according to an invalidation signal received by an input interface of the address translation backup buffer; according to the first invalidation verification information and the second invalidation verification information, determining whether the function of a signal transmission path from the microcode execution module to the input interface of the address translation backup buffer through the physical signal converter meets the expectation or not; and if so, the address translation backup buffer performs invalidation verification. The method and the device are suitable for address translation backup buffer invalidation verification.

The invention provides a broadcast type multi-board card parallel test method and system, a medium and a product, and relates to the technical field of electronic manufacturing board card testing, and the method comprises the steps: enabling a plurality of to-be-tested board cards to start to execute a target test item at the same time through a broadcast test instruction; the to-be-collected address list of the initial token frame establishes an ordered mechanism of board card access, and the first data segment provides a unified data collection space. In the token frame transmission operation, the first to-be-tested board card executes differentiated token frame processing operation according to the test state of the first to-be-tested board card; the token frame is directly forwarded in an uncompleted state; and in the completion state, writing test completion result data into the first data segment and updating the to-be-collected address list. And when the to-be-collected address list is empty, the tested board cards automatically exit the circulation, the unfinished board cards continue to participate in token transmission until the to-be-collected address list is empty, and the test results of all the board cards are collected into the first token frame. Therefore, a technical problem of low time utilization efficiency in a multi-board-card parallel test process in the prior art is solved.

The embodiment of the utility model provides a test board for a touch drive circuit, and the test board comprises a development board which is connected with a mainboard of a mobile terminal and the touch drive circuit; the development board comprises a downlink interface communication module used for receiving and transmitting the touch signal and obtaining touch point data based on the touch signal, and an uplink interface communication module connected with the mobile terminal mainboard. The downlink data conversion module is used for converting the touch point data into touch point data which can be identified by a mobile terminal mainboard and / or a PC tool; and the uplink data conversion module is used for converting a command or data received from the mobile terminal mainboard and / or the PC tool into an operation time sequence communicated with the touch driving circuit. By means of the test board, the touch signal and the display signal can be separated, and the effect of collecting interference data from the display screen is achieved under the condition that a TPIC driver in the mobile terminal is not updated.

The invention discloses a design method for an on-orbit accompanying measurement and control communication machine state machine model, and the method comprises the steps: constructing a data model of a measurement and control communication machine state machine, and enabling the data model to be used for calling data externally; constructing a context model of the state machine of the measurement and control communication machine based on the data model, and constructing a logic architecture of the state machine of the measurement and control communication machine based on scene service data; based on the logic architecture, the context model obtains an executable extended state machine and updates the feature attributes; obtaining a simulation model through periodic continuation based on the state machine capable of executing expansion and the context model, wherein the simulation model is used for processing uplink and downlink remote control and telemetering, voice and distance measurement service data of satellite communication, responding to a communication machine instruction set of the state machine of the measurement and control communication machine and outputting communication machine product telemetering; universal configuration is implemented based on the communicator instruction set and the communicator product telemetry.

The invention discloses a test incentive generation method and device, equipment, a storage medium and a product, and belongs to the technical field of artificial intelligence chips, the method comprises the steps that a test case is acquired, the test case comprises multiple pairs of equipment identifiers, and each pair of equipment identifiers comprises an equipment identifier of one piece of master equipment and an equipment identifier of one piece of slave equipment; selecting a first excitation constraint set matched with the master device from the master device constraint set according to the device identifier of the master device in each pair of device identifiers, and selecting a second excitation constraint set matched with the slave device from the slave device constraint set according to the device identifier of the slave device in each pair of device identifiers; and according to the first excitation constraint set and the second excitation constraint set corresponding to each pair of device identifiers, generating a test excitation, the test excitation being used for testing a communication path from one master device to one slave device. According to the invention, a single test case can test a plurality of communication paths, and the number of the test cases is obviously reduced.

The invention relates to the technical field of contact resistance detection, in particular to a contact resistance detection method for data line connection stability, and the method comprises the steps: applying high-frequency pulse excitation, obtaining excitation response signals under to-be-detected and standard states, carrying out dynamic impedance modeling decomposition, and extracting an impedance component to be analyzed and a standard impedance component. Constructing an impedance peak position difference change coefficient based on a difference change trend and an average level of time corresponding to an impedance peak position, and calculating a contact interference factor of each component; meanwhile, the fluctuation consistency is evaluated by using the information entropy of the impedance peak amplitude difference, and the impedance amplitude difference consistency is determined. And combining the two to construct a superposition interference characteristic value, screening effective impedance components with small interference, and performing dynamic fusion to obtain a dynamic impedance spectrum after the contact interference is eliminated. And finally, high-precision transient calculation of the contact resistance is realized through a dynamic impedance-resistance conversion model.

The invention relates to the field of memory management, and provides a DDR memory frequency switching test method and device. The method comprises the following steps: acquiring a plurality of preset frequency gears of the DDR memory; constructing a multi-stage test flow of at least two different switching modes; for each test stage, generating target data before executing the frequency switching action, acquiring actual data from the DDR memory in the process of executing the frequency switching action, performing consistency comparison on the target data and the actual data, and detecting whether the frequency switching process causes data hopping or not; performing reliability judgment on a corresponding switching mode of the DDR memory based on a comparison result of each test stage, establishing a fault association relationship among the plurality of test stages, and when any test stage detects data hopping, determining a potential frequency switching fault currently existing in the DDR memory; and carrying out collaborative verification on the actual data in different switching modes in the multi-stage test process to form a frequency switching test report. The frequency switching test reliability and test efficiency can be improved.

The invention provides an automatic testing method and system for embedded equipment and a computer readable storage medium. The automatic testing method for the embedded device comprises the steps that a test case is obtained, wherein the test case comprises at least one natural language command written by a natural language; analyzing the test case to generate a marking command corresponding to the natural language command, wherein the marking command has a text format adaptive to the test management website; based on a natural language command in the test case and a marking command corresponding to the natural language command, an operation instruction is generated through an AI test tool, and the AI test tool is constructed based on a large language model and an embedded device knowledge graph; the embedded device is controlled to execute the operation instruction, the embedded device comprises an execution mechanism, and the operation path of the execution mechanism is determined based on the operation instruction and the sensed real-time environment; and responding to the execution of the operation instruction, and generating a test result according to feedback data of the embedded device.

The invention relates to an intelligent body evaluation method and device, computer equipment, a readable storage medium and a program product. The method comprises the steps of performing full-dimensional evaluation on an intelligent agent based on a hierarchical evaluation index for the intelligent agent to obtain evaluation data; the layered evaluation indexes comprise a plurality of indexes which are obtained in combination with the application scene and are used for reflecting the comprehensive performance of the intelligent body; the evaluation framework of the full-dimensional evaluation comprises body-oriented brain evaluation, body-oriented cerebellum evaluation, body-oriented system evaluation and body-oriented safety evaluation; and processing and analyzing the evaluation data to obtain an evaluation result. According to the invention, full-dimensional evaluation can be provided for the smart phone.

The invention provides a chip debugging interface control method and device supporting batch access. The method comprises the steps that a host sends an access command frame to a chip through a serial debugging interface; the chip controls the analysis process of the access command frame by using a state machine; when the access mode of the access command frame is a batch access mode and the sequence mode is a discontinuous address batch access mode, the host sends a plurality of address fields in sequence, and the chip executes a read-write operation after receiving each address field and progressively decreases the word counting field after finishing each read-write operation; when the sequence mode is a continuous address batch access mode, the host sends an initial address through an address field, the chip automatically generates a next address field according to the initial address and sequentially executes read-write operation of a plurality of continuous addresses according to the value of the word count field, and the value of the word count field is progressively decreased every time the read-write operation is completed; and when the value of the word counting field is 0, batch access is ended, and a result is returned.

The invention relates to a notebook computer user experience testing method and system combined with a virtual scene. In the application, a virtual scene library containing at least two types of target virtual scene element data and a scene configuration file are firstly configured, and then an analog sensor signal stream is generated based on the virtual scene library and the scene configuration file and is injected into a notebook hardware interface. And meanwhile, dynamically loading a test task sequence to the virtual scene according to the scene complexity parameter, and synchronously collecting real-time performance index data. Then correlation analysis is carried out on the data and the configuration file, performance bottleneck and interaction delay characteristics are identified, an experience test report containing scene performance scores, bottleneck position marks and optimization suggestion data is finally generated, and comprehensive and accurate notebook computer user experience testing is achieved.

The invention discloses a digital chip verification method and device, electronic equipment and a computer readable storage medium, the method and device are applied to a verification system, the verification system comprises a software simulation platform and a hardware verification platform, and the method comprises the following steps: determining a to-be-tested code of a target digital chip; utilizing the software simulation platform to generate an excitation signal according to the to-be-tested code, and sending the excitation signal to a hardware verification platform; executing verification operation on the target digital chip by using the hardware verification platform according to the excitation signal to obtain a hardware verification result; when the hardware verification result has abnormal information, determining an abnormal node in the to-be-tested code, and debugging at the abnormal node by using a software simulation platform to obtain a software simulation result; and determining a final verification result of the target digital chip according to the hardware verification result and the software simulation result. By applying the technical scheme provided by the invention, more flexible and efficient digital chip verification can be realized.