2831results about "Detecting faulty computer hardware" patented technology

Disclosed are a complex device fault diagnosis method and system based on multi-dimensional features, and the method comprises the following steps of: acquiring fault data of a target complex device, and carrying out input coding mapping and position coding; utilizing a multi-head attention mechanism and multi-head dilated convolution series connection, and acquiring fault features covering global and local deep information in combination with a feedforward neural network; fusing the extracted fault features to acquire a multi-dimensional feature vector; and acquiring a fault type probability score matrix by a classifier, and outputting a fault diagnosis result of the target complex device. The global modeling advantage of multi-head self-attention and the local multi-scale feature perception advantage of multi-head dilated convolution are fused, and a device fault diagnosis model in which a Transform model and the multi-head dilated convolution are mutually fused is established.

The invention discloses a link test method, electronic equipment, a storage medium, a product and computing equipment, and is applied to the technical field of data transmission. The method comprises the following steps: determining to-be-tested equipment according to a to-be-tested link and a link training trigger condition; when the to-be-tested link finishes executing the link training operation and the link is recovered, determining a target register storing running state parameter information of the to-be-tested link in the to-be-tested device based on a link training trigger condition, and reading the running state parameter information; and when the link to be tested is diagnosed to have no fault according to the running state parameter information, executing the corresponding link training operation again based on the link training triggering condition. According to the method, the problems that related technologies depend on special tools, the starting time is long and the low-probability hardware fault reproduction period is long can be solved, the applicability is high, and the link testing efficiency can be effectively improved.

The invention discloses a hardware basic service component test system, which comprises a test management module, a hardware simulation module, an automatic test module, a data acquisition module, a data analysis module, a report generation module and a feedback adjustment module, the hardware simulation module is used for simulating hardware environments under different load conditions; the automatic test module is used for executing predetermined test tasks; the data acquisition module is used for monitoring hardware states and performance data in real time; the data analysis module is used for analyzing the acquired data; abnormal behaviors are identified and performance is evaluated, a report generation module generates a test report, and a feedback adjustment module dynamically adjusts test parameters and resource allocation according to an analysis result. The hardware basic service component testing efficiency, accuracy and comprehensiveness are improved, and the method can be applied to the technical field of hardware testing.

The invention provides a data transmission rapid verification method of a non-standard Type-C interface, which comprises the following steps: firstly, obtaining a verification request triggered when target equipment accesses the non-standard Type-C interface, extracting interface real-time signal characteristics including a voltage fluctuation sequence and the like based on the physical connection state identifier, and sending the extracted interface real-time signal characteristics to the non-standard Type-C interface; and then dynamically matching the real-time signal characteristics with a standard transmission parameter library, generating a test instruction set containing a priority ranking verification action and a trigger condition threshold value, calling the test instruction set to perform staged signal injection and feedback capture on the interface, recording an execution result and marking a time sequence, and finally generating a verification report according to the result. And the abnormal nodes which do not meet the transmission stability index are mapped to the interface physical structure defect description, so that rapid, comprehensive and accurate data transmission verification of the non-standard Type-C interface is realized.

The invention provides a method for carrying out fault judgment based on a computer hard disk state index, and relates to the technical field of computers.The method comprises the steps that a periodic data collection mechanism is set, and multi-dimensional feature data including disk rotation instability, the data transmission rate, the read-write error rate and the like are obtained; carrying out normalization and de-noising processing on the data; then, data dimension reduction is achieved through an auto-encoder, key feature vectors are extracted, and then fault probability calculation is conducted through a support vector machine; on the basis, a threshold fine tuning model is constructed, and the fault probability threshold can be dynamically adjusted according to the relevance between the physical state and the operation state collected in real time and the change trend of the physical state and the operation state; the accuracy and timeliness of fault judgment are improved, the probability of false alarm is reduced through a dynamic adjustment mechanism, and the safety of data storage and the normal operation of the system are ensured.

The invention discloses an LED large screen automatic repair and fault-tolerant display system and method, and relates to the technical field of LED display. The method comprises the steps that a sensor network and a high-definition camera collect data in real time; when an abnormal area is found, an intelligent diagnosis algorithm carries out comprehensive judgment according to sensor data and an image processing result, and the position and the type of a fault lamp bead are determined; starting an automatic repair process; redundant pixels are started to carry out hardware restoration; the dynamic reconstruction algorithm automatically adjusts the arrangement and brightness of redundant pixels, so that the redundant pixels replace fault lamp beads to participate in display; the system automatically adjusts the resolution and the display mode of the large screen according to the number and the distribution of the fault lamp beads. The problem that the display effect of an existing LED large screen is reduced when part of LED lamp beads are damaged is solved, it is ensured that the large screen can still maintain the good display effect under the fault condition through an innovative automatic repair and fault-tolerant mechanism, and the reliability of the system and the user experience are improved.

The invention relates to the technical field of deconcentrator testing, and discloses a multifunctional deconcentrator testing method, device and equipment and a storage medium, and the method comprises the steps: dividing a multifunctional deconcentrator into a central processing area, a USB interface area, a card reader interface area, a charging circuit area and a lithium battery area, performing temperature data acquisition on the multifunctional deconcentrator in a working state to obtain multi-point temperature time sequence data; performing nonlinear thermal dynamic feature extraction on the multi-point temperature time sequence data to obtain a fusion feature vector, and performing two-dimensional temperature field reconstruction based on the fusion feature vector to obtain a target temperature distribution diagram; performing operation test on the multifunctional deconcentrator according to the target temperature distribution diagram to obtain a temperature response curve; according to the method, the problem that a traditional method is insufficient in hot spot area recognition is solved, accurate reconstruction of a whole surface temperature field is achieved, and the test accuracy of the multifunctional deconcentrator is improved.

The invention relates to the technical field of memory channel testing, in particular to a multi-channel parallel testing system and method based on a memory. The method comprises the following steps: acquiring original data of a memory test channel; performing topology analysis on the original data of the memory test channel to generate node distribution data of the memory channel; performing dynamic weight calculation on the storage channel node distribution data to obtain channel priority data; performing resource competition arbitration on the storage channel node distribution data according to the channel priority data to generate channel resource allocation data; performing control plane mapping on the channel resource allocation data to generate network topology virtualization data; and performing routing strategy optimization processing on the network topology virtualization data to generate dynamic routing table data. By optimizing channel resource allocation, topology virtualization management, elastic scheduling synchronization, fault prediction and data matching, the multi-channel parallel test efficiency and accuracy of the memory are improved.

The invention discloses a test method of a server system, a storage medium, electronic equipment and a program product, and relates to the technical field of computers, and the method comprises the following steps: firstly, obtaining an equipment feature vector of a to-be-tested server system; performing fuzzy matching on the equipment feature vector and a feature description vector capable of performing server system testing in a driver library; if the matching is successful, collecting hardware characteristic parameters of the server system to be tested, and dynamically determining a test threshold value of the hardware state of the server system to be tested according to the environment parameters monitored in real time; and then testing the hardware state of the to-be-tested server system based on the hardware characteristic parameters and the dynamically determined test threshold. Compared with the prior art, automatic identification and adaptation of multi-manufacturer hardware equipment are realized, the time of manual intervention and the complexity of drive configuration are remarkably reduced, the test cost is further reduced, the test efficiency is improved, and meanwhile, the test accuracy and flexibility are also improved.

The embodiment of the invention discloses a hard disk fault prediction method and device, electronic equipment and a storage medium, and relates to the technical field of reliability of data storage systems.The method comprises the steps that hard disk data are obtained, data cleaning and feature selection are conducted on the hard disk data to obtain feature data, and the feature data are stored in a database; performing standardization and normalization on the feature data to obtain a data set, using a long-short term memory network as a deep learning model, designing a model structure, introducing a regularization technology and a dropout layer to construct an initial model, training and optimizing the initial model by using the data set to obtain a trained prediction model, and performing prediction on the trained prediction model. And performing state monitoring, fault early warning and maintenance on the hard disk by using the prediction model. According to the method, efficient and accurate hard disk state monitoring, fault early warning and maintenance are achieved through data preprocessing and the LSTM network deep learning model, and the problems that in the prior art, changes of the running state of the hard disk cannot be accurately captured, and data loss and system crash cannot be prevented are solved.

The invention discloses a board card testing method, electronic equipment and a storage medium, and relates to the technical field of servers, and the method comprises the steps: obtaining parameter information of a to-be-tested board card, and calculating a matching degree value of an interface of the to-be-tested board card and a board card interface in a first preset rule base; the characteristics of the to-be-tested board card are accurately identified, the target control script of the board card test fixture suitable for the to-be-tested board card is determined, it is ensured that the matched script is used when the board card test fixture is connected with the to-be-tested board card, and the damage risk caused by version mismatching is avoided to a certain extent; meanwhile, the board card testing jig determines the target testing task according to the parameter information of the board card to be tested and executes testing, and automation and precision of the testing process are achieved. Therefore, the problems that the test accuracy is reduced and the security risk is increased due to the fact that the version change information is not transmitted in time or inaccurately are effectively solved, the dependence on manual checking of engineers is reduced, the working efficiency is improved, and the test accuracy and security are remarkably improved.

The invention discloses a bus module self-recovery method and device, equipment and a storage medium. According to the invention, the communication state of the bus module is monitored in real time, and the abnormal detection signal is identified; when an abnormal detection signal is identified, the fault type is automatically diagnosed; dynamically selecting and combining an optimal recovery strategy according to the fault type; executing a self-recovery operation corresponding to the recovery strategy, and verifying a recovery effect; if the recovery fails, automatically adjusting and executing the recovery strategy of the next priority according to the fault type and the failure frequency; isolating communication between the fault bus module and other normal modules through a bus arbitration mechanism; recording fault features and a recovery process, and generating historical data for subsequent fault prediction; and if recovery fails for multiple times, triggering a system-level security protection mechanism, and giving an alarm. According to the method, the fault type can be quickly and accurately identified, the optimal recovery strategy is selected in a targeted manner, and the system maintainability and safety of the bus module system are effectively improved.

The present invention discloses a computer motherboard automated integrated test and intelligent diagnosis system and method, which relates to the field of computer motherboard test diagnosis technology, including a test platform building module, multi-interface adaptation and automatic motherboard identification, including a high-precision signal source and acquisition card, a modular architecture and high-speed bus interconnection; a test project execution module, which carries out multiple functional tests and simulates multiple scenarios to adjust the load; a data acquisition and storage module, which synchronously acquires multiple types of data through multiple channels, and has distributed storage and redundant backup; an intelligent diagnosis and analysis module, big data and machine learning algorithm diagnosis, a report generation and output module, a template engine generates reports and optimizes layout; a system self-check and calibration module, which starts each self-check module. The present invention realizes efficient and accurate testing of computer motherboards, reliable data acquisition and storage, modular design facilitates upgrading, and convenient remote functions, improves test and diagnosis efficiency and quality, helps motherboard production, maintenance and research and development, and enhances industry competitiveness.

The invention provides a notebook computer pre-installed environment simulation test method and system based on a virtualization technology, and the method comprises the steps: firstly creating a virtualization environment instance which is matched with a target notebook computer hardware architecture and comprises a pre-installed operation system and a preset software set, and then injecting a simulation user operation behavior sequence according to a predefined environment configuration strategy, the method comprises the steps of generating a dynamic test case set, executing and monitoring running state data in a virtual environment instance, generating an environment compatibility analysis report by extracting an abnormal response mode in the running state data, and finally adjusting resource configuration parameters of the virtual environment instance according to the environment compatibility analysis report. And generating the optimized pre-installed environment mirror image file, so that efficient and comprehensive simulation test on the notebook computer pre-installed environment is realized, and the test efficiency and accuracy are effectively improved.

The invention discloses a PCIE (Peripheral Component Interface Express) link training device and method, computer equipment and a storage medium, and relates to the technical field of PCIE links, and the method comprises the steps that a host end identifies an in-place signal of the PCIE link training device, and confirms that the current PCIE link rate is a preset rate; sending a test request to the host end, so that the host end returns a test signal according to the test request; receiving a test signal from the host end, converting the test signal to form an eye pattern, and combining one or more eye patterns to form an eye pattern test result; and acquiring a parameter value corresponding to the maximum value in the eye pattern test result as an optimal parameter value, and configuring the optimal parameter value to the host end. According to the method and the device, the parameters adaptive to the link can be obtained according to the type of the link, and the link and the adaptive parameters form the reference database, so that the reference database is used as parameters of similar links under the condition that other similar links appear.

To provide a computer hardware inspection table and an inspection system that make it difficult for computer hardware to move spontaneously during inspection and do not affect the inspection effect of computer hardware. 【Solution means】On the inspection table 7, a slide groove 8 and a placement groove 15 are provided on the side surface. A guide rod 9 is provided in the slide groove. A spring 10 and a moving plate 11 are fitted on the surface of the guide rod. One end of the moving plate is provided with a clamping plate 12. A moving groove 13 is opened on the side surface of the clamping plate. A position limiting block 14 is provided in the moving groove. When inspecting computer hardware, pull the position limiting block to remove the position limiting block from the placement groove, move one clamping plate, then place the hardware on the surface of the inspection table, release one clamping plate, and cooperate with the installation of the clamping plate and another clamping plate and the elastic force of the spring to clamp the hardware. Move the position limiting block and engage it in another placement groove to position and fix the hardware.

Embodiments disclosed herein include apparatuses for improved testing between chips. In an embodiment, an apparatus comprises a plurality of transmit clusters on a first chip, where individual ones of the plurality of transmit clusters comprise a set of transmit lanes on the first chip. In an embodiment, a plurality of finite state machines (FSMs) are on the first chip, where individual ones of the plurality of transmit clusters comprise one of the plurality of FSMs. In an embodiment, a global transmit test generator is communicatively coupled to each of the set of transmit lanes on the first chip, and a global transmit expected response generator is communicatively coupled to each of the plurality of FSMs on the first chip.

The invention discloses a signal processing detection system based on an FPGA architecture, and particularly relates to the technical field of hardware resource management, and the signal processing detection system based on the FPGA architecture comprises a signal acquisition module, a signal characteristic analysis module, a fluctuation prediction module, a self-adaptive hardware reconstruction module and a resource scheduling and optimization module. The signal acquisition module acquires signal data in real time, the signal characteristic analysis module extracts characteristic characteristics, and the fluctuation prediction module predicts signal fluctuation based on an AR model and judges whether hardware reconstruction is triggered or not; the adaptive hardware reconstruction module dynamically adjusts FPGA configuration and monitors the performance improvement effect when a reconstruction mechanism is triggered, and the resource scheduling and optimizing module dynamically allocates hardware resources according to the adjustment result and optimizes the system resource utilization rate; according to the method, when the signal fluctuation is relatively large, the hardware resource adjustment and task scheduling capabilities still have enough guarantee, and the problems of low processing efficiency and system response delay are avoided.

The present application relates to a test tool and test method for an interface of a motherboard to be tested of a server. The test tool for an interface of a motherboard to be tested of a server comprises a test tool, wherein the test tool comprises a tool core board, a Riser adapter card and an OCP adapter card. The Riser adapter card and the OCP adapter card each comprise a gold finger interface and a SlimSAS connector, and the Riser adapter card and the OCP adapter card are respectively used for transferring and transmitting signals of Riser interfaces and OCP interfaces on said motherboard to the tool core board. The tool core board, the Riser adapter card and the OCP adapter card are respectively connected to the corresponding interfaces on said motherboard by means of cables, so that the test of the interfaces on said motherboard can be realized.

The embodiment of the invention provides an indicator light signal sending method, a storage medium, an integrated hard disk and a computer program product, the indicator light signal sending method is applied to the integrated hard disk, the integrated hard disk comprises a mainboard, a backboard and a hard disk interface card, the number of transmission channels of a virtual pin interface of a central processing unit on the mainboard is expanded to N through a channel expansion assembly, the N transmission channels are connected with N first connectors on a mainboard in a one-to-one correspondence mode, and the method comprises the steps that N enable signals are sent to first type pins of the N first connectors respectively, so that the N enable signals are forwarded to a logic control device through first type pins of N second connectors connected with the N first connectors in a one-to-one correspondence mode; and the N indicator light signals are respectively sent to the second type of pins of the N first connectors through the N transmission channels, so that the N indicator light signals are forwarded to the logic control device through the second type of pins of the N second connectors.

The invention provides a hard disk testing method and device, equipment and a storage medium, and can be applied to the technical field of hard disk testing. The hard disk test method comprises the steps that in response to a received test request for a target hard disk, a target error injection instruction matched with a target sector in the target hard disk is executed, and the target error injection instruction is used for injecting a logic error into the target sector; writing first preset data into the target sector under the condition of determining that the execution of the target error injection instruction is completed; when it is determined that the bad sector information of the target hard disk indicates that the target sector is a bad sector, according to the mapping relation between the sector of the target hard disk and the standby sector, executing a read operation on the target standby sector having the mapping relation with the target sector to obtain first read data; and comparing the first read data with first preset data, and determining a first test result for the target hard disk.

The invention relates to a chip verification method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: establishing a verification environment of a UVM test platform; calling a test case; in the verification environment, verifying the chip according to the test case to obtain a verification result; wherein the test case is generated by using a TCL script according to a test requirement. According to the method, the test case written by the TCL is introduced, various different scenes can be infinitely tested only by loading and one-time compiling in the simulation stage, a test platform does not need to be repeatedly modified, and a large amount of test time is saved.

The invention provides a BIOS operation and maintenance method and system and a storage medium, and relates to the technical field of computers. The BIOS operation and maintenance method is applied to a control server in the BIOS operation and maintenance system. The method comprises the following steps: sending an acquisition request to a baseboard management controller (BMC) of each to-be-detected server in the BIOS operation and maintenance system; receiving real-time configuration information of the BIOS sent by the BMC of each to-be-detected server; comparing the real-time configuration information of each to-be-detected server with standard configuration information corresponding to the to-be-detected server in a standard library; responding to difference configuration items which do not conform to the standard configuration information in the real-time configuration information, and generating a difference report based on the difference configuration items; based on the difference report, retrieving a repair script corresponding to the target to-be-detected server from a script library; and sending the repair script to the BMC of the target to-be-detected server, so that the BMC repairs the BIOS of the target to-be-detected server based on the repair script. Therefore, batch automatic BIOS detection and repair can be realized, and the operation and maintenance efficiency and accuracy of the BIOS are improved.

The invention discloses a configuration method, system and device, a program product and a storage medium. The method comprises the steps of obtaining a large language model LLM type and demand information; generating configuration parameters based on the LLM type and the demand information; creating a test service based on the configuration parameters; performing a pressure test on the test service by using a test script to obtain a pressure test result; and adjusting the configuration parameters based on the pressure measurement result to obtain the configuration parameters meeting preset performance requirements. The resource allocation problem caused by lack of professional knowledge is effectively solved, and meanwhile, the working efficiency and the service quality are greatly improved, so that even a non-professional operation and maintenance team can easily complete a complicated LLM deployment task only by inputting the LLM type and the requirement.

According to the charging terminal automatic test system provided by the invention, the front-end page display module, the service control and processing module, the data processing and message generation module and the communication module are integrated, so that comprehensive automatic test on various charging terminals is realized. According to the system, the dependence on manual operation is reduced, and the testing efficiency and accuracy are greatly improved. And moreover, protocol-free verification among different devices can be realized, and the test can be executed without the need for technicians to have deep protocol knowledge, so that the test process is greatly simplified. In addition, the system also supports configuration and verification of various comprehensive scenes, and ensures the performance and reliability of the equipment under various actual working conditions. In addition, a systematized test report is automatically generated, recording and subsequent analysis are facilitated, and the working efficiency is further improved.

The invention discloses a memory error injection test method and device, an interface, a storage medium and electronic equipment. The method comprises the following steps: acquiring a basic test case, a hardware error injection test object and a test condition; whether a hardware error injection test needs to be executed or not is judged, if yes, the hardware error injection test object is tested according to test conditions and a basic test case, and a hardware test result is obtained; if not, skipping the hardware error injection test; obtaining software error injection test items and all function test cases corresponding to each software error injection test item; receiving an error injection parameter corresponding to the software error injection test item, and sequentially executing all the function test cases corresponding to the software error injection test item based on the error injection parameter to obtain a software test result; and obtaining a firmware test result according to the hardware test result and the software test result. Based on hardware error injection and software error injection, defects in firmware design can be covered, and firmware algorithm stability and self-recovery capability detection is realized.

In some embodiments, a method for tuning a disaster recovery preparation system for a storage system includes determining whether the disaster recovery preparation system has not met a recovery point objective; and in response to determining that the recovery point objective is not met: determining a state of the storage system; applying a machine learning model to determine a change to one or more of a plurality of adjustable parameters of the disaster recovery preparation system based on the state of the storage system and the recovery point objective that is not met; adjusting the one or more of the plurality of adjustable parameters based on the determined change to the one or more parameters; after adjusting the one or more parameters, monitoring one or more metrics of the disaster recovery preparation system or the storage system; and updating the machine learning model based on the monitoring.

The invention relates to the technical field of core board testing, in particular to a core board cross-platform function testing and verifying method which comprises the following steps: building a testing environment of a plurality of operating systems and hardware platforms through a virtualization technology or actual hardware, automatically generating a cross-platform compatible testing script based on core board function requirements, supporting multi-platform operation, and verifying the core board cross-platform function. Executing the test scripts in parallel on the platforms, recording and analyzing running logs and outputting results; functional consistency on different platforms is verified through a Hash comparison algorithm, it is ensured that the core board has the same function under the multi-platform environment, performance testing is conducted on all the platforms, performance bottlenecks are recognized, and optimization is conducted through an adjusting and optimizing tool; and finally, verifying the repairing effect through fault positioning and regression testing, and automatically generating a test report. According to the method, the efficiency of cross-platform testing of the core board, the accuracy of function verification and the effect of performance optimization are improved, and the method is suitable for core board testing and optimization scenes in a complex multi-platform environment.

The invention discloses a computer board card testing method and system, and relates to the technical field of computer board card testing, the system comprises a central server and at least one intelligent test fixture, the model of a to-be-tested board card is identified through the intelligent test fixture to obtain test information, and the test information is sent to the central server; and the central server determines a parallel test program corresponding to each to-be-tested board card according to the test information, and performs a synchronous test on each to-be-tested board card by running the parallel test program to obtain a test result corresponding to each to-be-tested board card. In the process, the model of the to-be-tested board card is automatically identified through the intelligent test fixture, the test program is automatically determined through the central server, automation of the test process is achieved, the problem of low efficiency caused by manual operation is avoided, and meanwhile, the test efficiency of the computer board card is improved by synchronously testing multiple to-be-tested board cards.

This disclosure relates to techniques and apparatuses for mitigating interference on SuperSpeed (SS) pins of a Universal Serial Bus Type C (USB-C) resulting from wireless communications, such as cellular and / or Wi-Fi communications. Specifically, a USB-C module may determine that a high-speed connection is to be established on the SS pins, and may interrupt the establishment procedure. The USB-C module may then provide an indication or instruction to configure one or more wireless communication modules to mitigate interference with the high-speed connection on the SS pins. For example, the wireless communication modules may be configured to reduce transmit power, cap transmit power, or forego transmission within certain frequency ranges and / or on certain antennas. Once configuration of the wireless communication modules is complete, the USB-C module may resume establishment of the high-speed connection on the SS pins.