6 results about "Asymmetric multiprocessing" patented technology

The invention discloses a shared debugging terminal implementation method and a shared debugging terminal implementation system for an asymmetric multi-processing system. The shared debugging terminal implementation method and the shared debugging terminal implementation system have the following beneficial effects: (1) a plurality of cores share a single physical serial port through a shared memory area and a central routing agent; (2) each sub-region in the shared memory region comprises a core identifier region, so that a core identifier can be automatically added to each piece of debugging information to ensure that the source of the debugging information is clear, and the debugging efficiency is improved; (3) the method does not depend on a complex network protocol stack, so that the method can work reliably even at the initial stage of system starting or when the system crashes, and the debugging reliability is improved; (4) the resource occupation is less, and the debugging requirement of the multi-core system can be met by only needing one physical serial port and other types of interfaces; and (5) the method also has a failover mechanism, and when the main routing agent fails, the main routing agent can be automatically switched to the standby agent, namely, the main routing agent is automatically switched to the new central routing agent, so that the normal work of a debugging function is better ensured.

The embodiment of the application provides a system architecture for heterogeneous multi-core inter-core communication and a running method of the system architecture, and belongs to the chip technical field.The system architecture for heterogeneous multi-core inter-core communication is designed based on a remote processor (Remote Proc) framework, and comprises a first processor system, a second processor system and a control device.The first processor system comprises a first control device and a first operating system module;the second processor system comprises a second control device and a second operating system module, wherein the second operating system module is further configured with an asymmetric multiprocessor (AMP) communication software component, and the second processor system is used for controlling the first processor system to run through the Remote Proc and the AMP communication software component.The Linux Remote Proc framework is expanded by configuring the second processor system with the asymmetric multiprocessor (AMP) communication software component, so that efficient work of the heterogeneous multi-core inter-core communication is achieved, and the heterogeneous inter-core collaborative processing is completed.

This disclosure discloses a task migration method, apparatus, electronic device, and storage medium, relating to the field of computer technology, and particularly to the field of asymmetric multiprocessor systems. The specific implementation is as follows: In response to detecting an operational anomaly in an asymmetric multiprocessor system, load information of the asymmetric multiprocessor system and error information of the abnormal processor core are obtained. The asymmetric multiprocessor system includes multiple processor cores with independent memory address spaces. Based on the error information, at least one candidate processor core from the multiple processor cores and the target task to be migrated from the abnormal processor core are determined. Based on the load information, the target processor core is determined from the at least one candidate processor core. The target task to be migrated is then migrated to the target processor core.

Embodiments include an asymmetric multiprocessing (AMP) system having two or more central processing unit (CPU) clusters of a first core type and a CPU cluster of a second core type. Some embodiments include determining a control effort for an active thread group, and assigning the thread group to a first performance island according to the control effort range of the first performance island. The first performance island can include a first CPU cluster of the first core type, where a second performance island includes a second CPU cluster of the first core type, where the second performance island corresponds to a different control effort range than the first performance island. Some embodiments include assigning the first CPU cluster as a preferred CPU cluster of the first thread group, and transmitting a first signal identifying the first CPU cluster as the preferred CPU cluster assigned to the first thread group.

The invention discloses a hardware peripheral dynamic allocation method and device based on an asymmetric multi-processing architecture. The method comprises the following steps: receiving a resource application initiated by an application system business APP through resource management; determining the current use priority of the hardware peripherals needing to be applied according to the resource application, and judging whether the current application priority is higher than the current use priority or not; if the current application priority is higher than the current use priority, notifying a service APP using the hardware peripheral at present that the hardware peripheral is to be unavailable, performing resource release through drive management, and notifying an application system that the resource application is successful after the resource release is successful; and if the current application priority is lower than the current use priority, notifying the application of system resource application failure. According to the method, the hardware peripherals can be dynamically allocated according to the service APP requirements, the flexibility is high, the resource utilization rate is high, static configuration modification, system upgrading and restarting are not needed for allocation adjustment of the hardware peripherals, and the reallocation cost is low.