320 results about "Local memories" patented technology

The invention relates to the technical field of distributed computing, and discloses a heavy truck charging load scheduling-oriented distributed energy intelligent matching method, which comprises the following steps of: establishing a charging service computing power mapping table at a scheduling node; maintaining a shadow counter in a local memory, extracting a pre-estimated computing power consumption value according to an event type and accumulating the pre-estimated computing power consumption value to the shadow counter, and executing linear numerical deduction on the shadow counter according to a reference logic subtraction rate so as to simulate a scheduling data throughput evolution process; adjusting a linear deduction rate parameter according to the deviation between the state feedback data and the numerical value of the shadow counter; and distributing the charging matching task to a charging station edge computing node of which the shadow counter value does not exceed a preset logic saturation threshold value. According to the invention, through an open-loop estimation and closed-loop calibration mechanism of a local logic state, an instantaneous congestion risk caused by physical feedback lag is eliminated; and logic state consistency and self-adaptive distribution of the whole network computing power resources are realized.

The embodiment of the invention provides a memory allocation method and device.The method comprises the steps that under the condition that page table page allocation is determined to be conducted on a target page table of a target process, a resource binding mechanism corresponding to the target process is obtained; according to a memory node binding constraint in the resource binding mechanism, determining a target memory node corresponding to the target process, and allocating a page table page for the target page table at the target memory node; when it is determined that the local memory of the target memory node is insufficient, so that the page table page allocation fails, a target physical page in the local memory is migrated to a first remote memory node, and the step of allocating the page table page to the target page table at the target memory node continues to be executed until the page table page allocation succeeds. By forcibly distributing the pages of the page table at the target memory node and combining with an intelligent memory migration mechanism, the performance loss caused by remote access of the page table is fundamentally eliminated.

Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.

The invention discloses a structured data storage method based on natural language transformation, which comprises the following steps of: a system initialization configuration stage: deploying a protocol adapter in a local memory of a PC (Personal Computer) client, and loading natural language processing pipeline configuration parameters; a heterogeneous data acquisition stage: capturing a multi-source text data stream through the protocol adapter, uniformly converting the multi-source text data stream into a standardized data packet, and sending the standardized data packet to a message queue theme; a text cleaning stage: a named entity recognition stage: inputting the pure text data into an NER module deployed with a language model loader; in the conditional feature extraction stage, feature vectors are generated for texts meeting preset conditions on the basis of entity type tags in the entity recognition result; and a consistent storage stage: inserting the entity identification results into a relational database in batches, and updating the entity mapping relationship in the cache. According to the method, the intelligent level of cache management is remarkably improved, and the access fluency of the key data of the user is guaranteed.

The invention provides a memory access method and electronic equipment, and is applied to the technical field of accelerator systems. The memory access method comprises the following steps: determining a target memory access strategy from a preset memory access strategy set according to a local memory access feature of any computing core; under the condition that the target memory access strategy is a transmission optimization strategy, position information of the to-be-accessed data in a target cache line is determined according to a target cache line address in an initial memory access request initiated by any computing core; generating a bit mask for identifying the to-be-accessed data according to the position information; and adding the bit mask to the initial memory access request to form a memory access request, sending the memory access request to a target device to which the target cache line address belongs, and returning the to-be-accessed data by the target device according to the bit mask in the memory access request.

The invention discloses an underground pipeline intelligent leakage detection method and device, and relates to the field of intelligent leakage detection.The method comprises the steps that a high-frequency pressure sequence of a target pipe section is collected, and based on the Boltzmann superposition principle, the high-frequency pressure sequence is used for constructing a neural lag operator network by taking the environment temperature as a heat rheological regulation factor; taking the full historical stress-strain memory field tensor as input, carrying out non-local memory characteristic and hysteresis loop analysis, carrying out point-by-point differential processing on a high-frequency pressure sequence and the intrinsic nonlinear hysteresis response signal of the pipe, stripping non-stationary background fluctuation, avoiding modulation interference of material nonlinearity on a fluid signal, and obtaining a non-linear hysteresis response signal of the pipe. The method comprises the following steps: extracting the abnormal residual error of the fidelity fluid dynamics, constructing a spatio-temporal evolution Poincare section, inputting the spatio-temporal evolution Poincare section into a convolutional neural network, judging the real leakage negative pressure wave and the random drift of the sensor through the morphological difference of attractors on the spatio-temporal evolution Poincare section, and eliminating the periodic false alarm caused by the rheological property of the material.

The embodiment of the invention provides a task processing method and computing equipment, and the method comprises the steps: obtaining a processing task which comprises target application information; according to a mapping relation and the target application information, a target memory allocation proportion corresponding to the processing task is determined, the mapping relation comprises multiple pieces of application information and a memory allocation proportion corresponding to each piece of application information, and the memory allocation proportion is the proportion between a local memory used by the computing device and a computing fast connection CXL memory; and processing the processing task according to the target memory allocation proportion. In the method, the computing device can flexibly and accurately determine the adaptive target memory allocation proportion for each processing task according to the target application information in each processing task and the mapping relation, and accurately adjust the local memory and the CXL memory used by the computing device based on the target memory allocation proportion. Therefore, it is ensured that the computing device has high processing performance on the processing task.

Methods, systems, and devices for providing firmware management using a firmware management engine of a cloud computing system are described. The firmware management engine supports using a hot-plugged memory (e.g., Compute Express Link (CXL) pooled memory) to temporarily migrate system memory (e.g., Central Processing Unit (CPU) local memory or CXL attached memory) of a server node, while performing firmware management operations (e.g., a firmware update) on the server node. The hot-plugged memory can be CXL pooled memory that is a shared at a rack level, the CXL pooled memory can be used to store system memory data of system memory while updating and activating new memory initialization firmware code. A virtual machine associated with the server node stays operational temporarily using the hot-plugged memory. Firmware management is performed on a server node while virtual machines associated with the server node and the system memory of the server node remain operational.

Techniques discussed herein relate to an object-relational database management system (ODMS) (e.g., a PostgreSQL ODMS) that provides in-line materialization of database pages corresponding to read requests. A replica node of the ODMS may be configured to share access to a shared block storage volume with a primary node. The replica node may receive log updates from the primary indicating changes to the object-relational database. The read replica, in response to receiving a read request, may update a previous version of a database page, store the database page in local memory, and replay the log updates to update the database page in local memory. Data may be provided from the updated database page in response to the read request.

A telecommunications switch-type platform positioned between a private-branch exchange and a data network dynamically hosts artificial-intelligence agents that interpret, transcribe, translate and transliterate live call traffic while the session is in progress. Machine-readable instructions stored in local memory instantiate, migrate and terminate the agents on demand across dedicated processing resources such as field-programmable gate arrays, application-specific integrated circuits or system-on-chip devices, thereby maintaining end-to-end latency below 250 milliseconds. An integrated call-audio recorder captures bidirectional media streams for secure archiving without interrupting service. The platform exposes a network interface that passes both signalling and media traffic, enabling seamless deployment inside call-centre or enterprise environments and compatibility with softswitch architectures conforming to class-4 Computational Interpretation of Communication using Artificial Intelligence standards. The same functional stack is deliverable as a computer-implemented method and as a non-transitory machine-readable medium storing the instructions executed by the processing resources.

A machine learning accelerator includes a scalable processor with a plurality of cores that receive data from system memory via a system direct memory access (DMA) engine. Each core may include local memory, a compute sub-system, and one or more slices, each of which includes a descriptor execution engine and one or more compute engines. Each compute engine includes input data memory, one or more sub-compute engines, and partial data memory. The sub-compute engines are separately connected to the input data memory and are configured to independently perform compute operations, such as multiply-accumulate (MAC) operations, on the input data and to provide partial output data to the partial data memory. The cores, slices and sub-compute engines may be configured to operate independently to perform separate tasks in parallel that once completed are combined as part of a large artificial intelligence model.

The invention relates to the field of load balancing, and particularly discloses a national standard signaling load balancing system and a national standard signaling load balancing method based on elb and redis, which are characterized in that registration and session state data of all equipment are stripped from a signaling server and are converted into a high-availability shared cache for centralized persistence, so that the signaling server becomes a stateless computing node. When the load balancer detects that any signaling server fails, the load balancer accurately and smoothly redirects the subsequent signaling of the affected device to another healthy takeover server in the cluster by using the orderliness of the consistent Hash algorithm. As all the servers maintain the complete mirror image of the global device state in the local memory in advance, the takeover server can immediately identify the device and seamlessly recover the session. In this way, the problems of session loss and large-scale re-registration storm caused by server faults are solved.

Techniques for static instruction decoupling for data movement and computer are described. In some examples, hardware support at least includes a plurality of instruction queues to store instructions, wherein each instruction queue of the plurality of instruction queues is dedicated to a separate thread; a local memory to store instructions and / or data for a first thread; a scratchpad memory, coupled to the local memory, to store instructions and / or data for a second thread; and execution resources, coupled to the scratchpad memory, to execute one or more mathematic and / or logical instructions for a third thread.

The invention provides a data hierarchy scheduling method and system, a storage medium and equipment, and relates to the field of data processing, and the method comprises the steps: obtaining a sparse matrix in a row compression storage format; performing matrix segmentation on the sparse matrix to obtain segmented small matrixes; calling a vector access unit to package and access paired indexes in the sparse matrix, storing row data to be updated into an on-chip local memory, and storing a non-zero element column index of the sparse matrix corresponding to each row of the L matrix and a corresponding numerical value into a storage space of each thread in the on-chip local memory; global threads are grouped to obtain a plurality of thread blocks, and thread indexes of the thread blocks are stored in an atomic cache; and in the atomic cache, the segmented small matrixes are correspondingly processed by using the thread blocks. The parallel computing capability of the multi-core processor can be fully utilized, the memory delay is reduced, and the data access efficiency is improved.

The present disclosure relates to a data processing method, a processor, a chip, a graphics card and an electronic device, and relates to the technical field of intelligent computing. The method comprises the following steps: in response to M tensor computing engines in a tensor computing engine cluster completing reading of a partial first matrix from a local memory or a register of a computing unit to which the M tensor computing engines belong and reading of a second matrix from a tensor memory, the M tensor computing engines respectively perform matrix operation according to the partial first matrix and the second matrix to obtain corresponding operation results of the M tensor computing engines; and the M tensor computing engines respectively write the corresponding operation results into the registers of the M tensor computing engines. The embodiment of the present disclosure can increase computing power without increasing the size and bandwidth of the local memory and the register inside the computing unit.

The application discloses a memory allocation method without locking among multiple cores, comprising the following steps: dividing the memory into multiple local memory pools according to the number of CPU cores, wherein the number of the local memory pools is the same as the number of the CPU cores, and each local memory pool corresponds to a different CPU core, and each CPU core does not need to be locked when applying for memory resources in the multiple local memory pools; if the required memory resources of a second CPU core are less than the memory resources in a second local memory pool, the second CPU core applies for the memory resources from the second local memory pool; otherwise, the second CPU core continues to execute; if the required memory resources of the second CPU core are greater than the memory resources in the second local memory pool corresponding to the second CPU core, the second CPU core applies for and uses the memory resources from a first local memory pool corresponding to a first CPU core through multiple shared buffers. The application further discloses corresponding devices, electronic equipment and computer readable storage media, wherein in most scenarios, each CPU core fully uses the memory resources, and the performance is optimal; when cross-core application is required, the memory allocation is realized through the shared buffer mode without locking.

The invention discloses a field replaceable unit management method and computing equipment, and relates to the technical field of computing equipment. The method is applied to a computing device, and the computing device comprises at least one field replaceable unit FRU. The method comprises the steps that a storage space of a target FRU is read multiple times, multiple pieces of first label information are obtained, the storage space of the target FRU is used for storing the label information of the target FRU, and the target FRU is one of at least one FRU. And under the condition that the multiple pieces of first label information are consistent, storing the first label information in a local memory. And verifying the correctness of the first label information based on the local memory. And under the condition of verifying that the first label information has an error, correcting the first label information in the local memory to obtain second label information. And updating the tag information in the storage space based on the second tag information. Therefore, the reliability and the accuracy of FRU management are improved.

The application relates to the technical field of distributed data processing, in particular to a data collection and storage method and system, an organic light-emitting diode inkjet printing equipment and a storage medium. The method comprises the following steps: a collection client obtains a collection task of the organic light-emitting diode inkjet printing equipment; based on a preset data type classification rule, the collection task is split into multiple independent subtasks, wherein the number of the independent subtasks is adapted to the number of the collection clients; each collection client collects original data of the organic light-emitting diode inkjet printing equipment in parallel according to each independent subtask, and sends the original data to a master node of a distributed cache cluster; each master node receives original data of a corresponding type, divides a storage partition according to a type corresponding to the preset data type classification rule, and directly writes the original data into a local memory to complete real-time storage, so that the data storage delay of the organic light-emitting diode inkjet printing equipment multi-type data collection is low.

The invention discloses a log management method, device and equipment and a storage medium, is applied to solid state disk equipment, and relates to the technical field of computers, and the log management method comprises the steps that in the power-on initialization process, host memory demand information is reported to a host, so that the host returns a cache allocation result based on the host memory demand information; when a log export instruction sent by a host is received through a local out-of-band command processing component, determining a to-be-exported log and a segmented loop export strategy in combination with a local flash memory; completing a log export operation by using a segmented loop export strategy, the to-be-exported log, the cache allocation result and a local preset direct memory access engine to obtain instruction completion information; and feeding back instruction completion information to the host, so that the host reads the log in the local memory based on the instruction completion information to trigger log processing operation. According to the log exporting method and device, the problems existing in existing related schemes can be effectively solved, and therefore log exporting is efficiently, stably and reliably achieved.

The application discloses a processor, a data processing method, a chip and an electronic device, and belongs to the electronic technical field. The processor comprises an exchange module, a processing module and a local memory, the processing module and the exchange module are connected with the local memory and an extended memory, and the processing module is connected with the exchange module. Wherein, the processing module sends an exchange instruction to the exchange module when determining that the first data meeting the condition is located in the extended memory. The exchange module reads the first data from the extended memory and the second data from the local memory based on the exchange instruction, writes the first data into the local memory, and writes the second data into the extended memory. By exchanging the data that may be accessed from the extended memory to the local memory, the subsequent processing module can read data from the local memory, and the data reading delay is reduced.

A compute tile includes a WCB that receives a workload of writing an output tensor of a convolution into a local memory of the compute tile. The local memory may be a SRAM. The WCB receives write transactions. A write transaction includes a data block, which is a part of the output tensor, and metadata describing one or more attributes of the data block. The WCB may store write transactions in its internal buffers. The WCB may determine whether to combine two write transactions, e.g., based on an operation mode or metadata in the write transactions. In embodiments where the WCB determines to combine the two write transactions, the WCB may combine the two write transactions into a new write transaction and write the new write transaction into the local memory or an internal memory of the WCB. The total number of write transactions for the workload can be reduced.

The invention provides a high-speed serial protocol memory configuration method and electronic device.The method comprises the steps that when an operating system of the electronic device runs, at least one memory module is accessed in response to hot plugging of the electronic device, and a memory configuration mode of the at least one memory module is obtained through an out-of-band management system of the electronic device; when the memory configuration mode is the first memory configuration mode, deleting a first memory node where a first memory module is located in a local memory module of the electronic equipment, and applying the first memory configuration mode; wherein the first memory configuration mode represents that at least one memory module and the first memory module are configured at the same memory node; the first memory module is a part of or all memory modules in the local memory module.

The present disclosure provides a course data synchronization method and device, electronic equipment and storage medium. The method comprises: obtaining a course data list of a remote platform and storing it in a local memory; determining that the course data list is not empty, and iteratively traversing the course data list, taking out the remote course data in the course data list, and obtaining the identification information of the remote course data; querying whether the local course data in the local database is empty according to the identification information; in response to the local course data not being empty, determining the download state of the local course data, synchronizing the remote course data to the local course data to obtain first target course data, updating the first target course data and the download state to the local database; in response to determining that the local course data is empty, constructing a local course data object, and obtaining the remote course data corresponding to the local course data in the local memory as second target course data and adding it to the local database.

The invention relates to the technical field of local memories, and provides an efficient access method and device supporting a plurality of gate or scatter requests. The method comprises the following steps: carrying out shared resource arbitration on a plurality of original requests, so that the original requests enter corresponding request caches; performing multi-level memory bank arbitration on the original request in the request cache to obtain at least one to-be-processed request; and routing the to-be-processed request to a corresponding memory bank, so that the memory bank processes the to-be-processed request. According to the method and the device, the problem that aggregation or dispersion operation of a plurality of memory banks cannot be efficiently supported in the prior art is solved.

The invention provides an applet communication control method, an applet construction method, devices and equipment. The invention relates to the technical field of computers, in particular to the technical field of applets. According to the specific implementation scheme, when the applet is started, an event bus is initialized in a host environment, and the event bus is used for maintaining the event subscription relation of each independent subpackage; generating a corresponding event message through the event bus in response to a calling request sent by the first independent subpackage for the target service; under the condition that a second independent subpackage of the target service is not loaded in the local memory, temporarily storing the event message in a message queue, and triggering a downloading and loading process of the second independent subpackage; and monitoring the loading state of the second independent subpackage, and when it is detected that the second independent subpackage is loaded and registered to the event bus, taking out the event message from the message queue and distributing the event message to the second independent subpackage. According to the scheme, the starting speed of the applet is increased, and continuity and stability of the business process are guaranteed.

The application provides a high-throughput real-time data desensitization method, relates to the technical field of data processing, and comprises the following steps: acquiring a service data stream and a rule configuration stream; distributing rule objects to the local memories of each computing node, constructing a field path prefix tree, and storing an accurate matching rule list and a regular matching rule list in the nodes of the prefix tree; recursively traversing data records, identifying all fields and field paths that need to be matched; splitting the field path into a to-be-matched path segment sequence, sequentially matching each path segment in the to-be-matched path segment sequence from the root node of the prefix tree, obtaining a target node of a matching path, collecting the regular matching rule lists of each node on the traversal path, and obtaining a candidate regular rule set; acquiring a matching rule; and executing a corresponding desensitization algorithm on a field value according to the desensitization algorithm type in the matching rule to obtain a desensitized data record. The application can guarantee data security compliance and improve the throughput performance of real-time stream processing.

Methods, systems, and apparatus, including medium-encoded computer program products, for 3D model rendering, include: obtaining, by a computer having a display device and local memory, a three-dimensional scene description data structure encoding location information in a three-dimensional model of an environment, wherein the three-dimensional model is stored on a remote computer system, and the location information comprises bounding volumes for objects in the three-dimensional model; downloading, by the computer and from the remote computer system, a portion of the objects to the local memory; and rendering, by the computer, the portion of the objects along with one or more three-dimensional tiles representing a portion of the three-dimensional model in which at least one of the objects of the three-dimensional model that has not been downloaded is located, in accordance with the three-dimensional scene description data structure.

The application relates to a chip parallel communication system. The system comprises a plurality of nodes, each node comprising a GMAC unit, and a processor unit, an MC unit and a NIC unit connected to the GMAC unit; the GMAC unit is configured to, in response to receiving an access request, transmit a first remote memory access request to the NIC unit and a second remote memory access request to the MC unit; the NIC unit is configured to transmit the first remote memory access request to a corresponding external node; the MC unit is configured to read or write data from a memory coupled to the MC unit according to at least one of a local memory access request and the second remote memory access request, and in the case of reading out data, transmit the read-out data to a corresponding processor unit through the GMAC unit; by configuring the GMAC unit and the processor unit, the MC unit and the NIC unit connected to the GMAC unit, the application reduces the communication delay between the nodes, thereby improving the data volume communication parallel computing performance, and improving the system performance and efficiency.

The present application relates to hydrate depressurization production numerical simulation technical field, specifically relates to hydrate decomposition method and system considering pressure wave time lag and pore structure entropy, the method includes the following steps: calculating pore structure entropy, constructing saturation and structure entropy dependent time memory kernel, combining decomposition rate threshold, pressure drop threshold, forming the decomposition front indicator function with prediction-correction mechanism;The time memory kernel, space-time inseparable causal kernel and threshold response function are subjected to space-time convolution operation, based on the decomposition front indicator function, an integral form of non-local memory hydrate decomposition rate model is established;The Peacley number is calculated by grid Darcy velocity, the scalar characteristic memory time is extended to the second-order symmetric anisotropic memory time tensor, the second-order tensor type memory variable is constructed and the evolution equation is established, the non-local memory hydrate decomposition rate model is coupled to the energy conservation equation and two-phase Darcy seepage pressure equation, and the decomposition result is obtained by iterative solution.

Methods, systems, and apparatus, including medium-encoded computer program products, for 3D model rendering, include: obtaining, by a computer having a display device and local memory, three-dimensional scene description data structure encoding location information in a three-dimensional model of an environment, wherein the three-dimensional model is stored on a remote computer system, and the location information comprises bounding volumes for objects in the three-dimensional model; downloading, by the computer and from the remote computer system, a portion of the objects to the local memory; and rendering, by the computer, the portion of the objects along with one or more visual indicators representing a portion of the three-dimensional model that is still to be downloaded, wherein the one or more visual indicators are placed in three-dimensional space in accordance with the bounding volumes in the three-dimensional scene description data structure to provide feedback to a user regarding a status of object downloading.