749 results about "Local memories" patented technology

The invention discloses a request allocation method and system based on a heterogeneous computing system, equipment and a medium, relates to the technical field of computers, and determines reading time required for using key value cache when a plurality of heterogeneous computing power equipment accesses a memory under the condition of preferentially considering the use condition of a key value cache mechanism. Requests are reasonably distributed by considering the performance difference of the computing power information of the heterogeneous computing power equipment, the memory information corresponding to the memory extension and the characteristics of the reasoning task information. Furthermore, the reasonability of request allocation is improved according to a comparison relationship between the preset allocation request quantity and the concurrent request quantity and different strategies for judging whether allocation conditions are met or not. Therefore, the technical problem that more computing power resources are wasted due to the fact that the allocation balance of the reasoning request is poor when a separated memory or a local memory is called can be solved, and the technical effects that the reasoning task information is reasonably allocated to the heterogeneous computing power equipment, so that the allocation balance is improved, the computing power resources are saved, and the cost is reduced are achieved.

The invention discloses a process scheduling method and device based on an NUMA framework, electronic equipment and a storage medium, and relates to the technical field of computer systems.The process scheduling method comprises the steps that in the process running process, comprehensive performance scores of all NUMA nodes are calculated by obtaining performance index data corresponding to all the NUMA nodes respectively, and the performance index data of all the NUMA nodes are obtained; the target NUMA node is selected based on the comprehensive performance score to be bound with the execution core of the current running process, and the required memory page is pre-allocated for the current running process in the local memory area of the target NUMA node, so that the current running process can access the local memory of the bound NUMA node, the probability that the process accesses the memory across the NUMA node is reduced, and the memory access efficiency is improved. Therefore, the technical problem that the memory access delay is remarkably increased due to the fact that the process frequently accesses the memory across the NUMA nodes can be solved, and the technical effects of shortening the memory access delay and improving the system performance are achieved.

A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.

Examples described herein and includes at least one processor and a direct memory access (DMA) device. In some examples, the DMA device is to: access a command from a memory region allocated to receive commands for execution by the DMA device, wherein the command is to access content from a local memory device or remote memory node. In some examples, the DMA device is to: determine if the content is stored in a local memory device or a remote memory node based on a configuration that indicates whether a source address refers to a memory address associated with the local memory device or the remote memory node and whether a destination address refers to a memory address associated with the local memory device or the remote memory node. In some examples, the DMA device is to: copy the content from a local memory device or copy the content to the local memory device using a memory interface.

Methods, systems, and apparatus, including medium-encoded computer program products for loading and rendering include: obtaining a 3D spatial access tree data structure encoding location information for objects in a 3D model of an environment, wherein the 3D model is stored on a remote computer system; ranking a set of the objects in the 3D model to form an object hierarchy based at least on distances between each object of the set of objects and a specified viewpoint for a user within the environment, as determined using the three-dimensional spatial access tree data structure; selecting a proper subset of the set of objects to be rendered based on the object hierarchy and a current model load limit; downloading the proper subset to the local memory; and rendering the proper subset from the local memory to the display device based on the specified viewpoint within the environment for the user.

This application generally relates to memory provisioning and particularly describes systems and methods for distributed memory pools. For example, a computing / memory device in a distributed system may be configured to execute application logics using local cache for data maintained in non-local memory in another computing / memory device of the distributed system. The computing / memory device may further be configured to provide memory for other applications executed on other computing / memory devices of the distributed system. The local and non-local memory allocation for the applications in the computing / memory devices of may be dynamically and adaptively adjusted according to various system parameters and indicators.

One embodiment provides a graphics processor comprising a memory interface and a graphics core cluster including a plurality of graphics cores and tensor processing circuitry. The tensor processing circuitry includes a local memory, a tensor accelerator coupled with the local memory, the tensor accelerator configured to perform a matrix multiply and accumulate operation, and a tensor data movement accelerator configured to asynchronously transfer tensor data between a global memory coupled to the memory interface and the local memory. The tensor data movement accelerator includes circuitry configured to translate the tensor data from a first tensor format to a second tensor format.

Examples described herein include one or more processors; a network interface; and a direct memory access (DMA) engine communicatively coupled to the one or more processors. In some examples, the DMA engine is to receive a DMA data access request and based on an address in the DMA data access request corresponding to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device. In some examples, if the source address corresponds to a local memory device and the destination address corresponds to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device.

The embodiment of the invention provides a data processing method and device and electronic equipment. In the embodiment, when a data writing request is received, whether a target cache region corresponding to a target file indicated by the request exists locally or not is checked firstly, if not, the target cache region is created in a local memory, and the size of the target cache region is the same as that of a storage page in an NAND Flash medium; and then, before to-be-written target data is written into the NAND Flash medium, the target data is written into the target cache region based on the size of the available storage space of the target cache region, and on this basis, when the size of the available storage space in the target cache region is a preset value, namely when the target cache region is full, the data in the target cache region is written into the NAND Flash medium. In this way, write amplification caused by the fact that the size of the target data to be written is smaller than that of the storage page can be effectively avoided, and therefore the PE service life of the NAND Flash medium is prolonged.

The embodiment of the invention discloses a data caching method and device, equipment and a storage medium, and relates to the technical field of data processing. The method comprises the following steps: constructing a hash ring according to the number of machine nodes in the current micro-service and the number of virtual nodes in a consistent hash algorithm, wherein each position in the hash ring corresponds to each virtual node of each machine node in the current micro-service; receiving to-be-cached data, determining a hash value corresponding to each to-be-cached data based on a consistent hash algorithm, and performing data segmentation on the to-be-cached data based on the hash value corresponding to each to-be-cached data; and determining a target machine node for storing each group of to-be-cached data in the current micro-service in the hash ring based on the hash value corresponding to each group of segmented to-be-cached data, and caching each group of to-be-cached data to the target machine node. According to the technical scheme, batch caching of the to-be-cached data is realized based on the local memory of the current micro-service, so that the current micro-service can obtain the data from the local memory, and the performance of the current micro-service is improved.

Embodiments relate to utilizing artificial intelligence (AI) technology to enable comprehensive and systematic management of coupons that can be equivalent to marketing strategies or benefits. A first analysis on a raw data stored as text, image, video, or any combination thereof in the IT device is performed with an AI tool to automatically detect one or more coupons from the raw data. The result of the first analysis is treated as the detected coupons that will be stored in a coupon database or a local memory. A second analysis on the coupon database or local memory is performed with the AI tool to extract a detailed coupon information from each of the detected coupons. The detailed coupon information corresponding to each of the detected coupons is clustered based on one or more predetermined criteria and stored as the clustered result in the coupon database or local memory.

Techniques are described herein for performing thread-local garbage collection. The techniques include automatic profiling and separation of private and shared objects, allowing for efficient reclamation of memory local to threads. In some embodiments, threads are assigned speculatively-private heaps within memory. Unless there is a prior indication that an allocation site yields shared objects, then a garbage collection system may assume and operate as if such allocations are private until proven otherwise. Object allocations in a private heap may violate the speculative state of the heap when reachable outside of the thread. When violations to the speculative state are detected, an indication may be generated to notify the garbage collection system, which may prevent thread-local memory reclamation operations until the speculative state is restored. The garbage collection system may learn from the violations to reduce the allocation of invalidly private objects and increase the efficiency of the garbage collection system.

The disclosure describes hardware compression of sparse matrix content. One embodiment provides a graphics processor, the graphics processor comprising: a base die, the base die comprising a plurality of chiplet slots; and a plurality of chiplets, the plurality of chiplets being coupled with the plurality of chiplet slots. At least one chiplet of the plurality of chiplets comprises: a graphical core cluster comprising a plurality of processing elements; a shared local memory coupled with the plurality of processing elements; a plurality of matrix engines coupled to the shared local memory; and codec circuitry coupled with the shared local memory and the plurality of matrix engines. Codec circuitry is configured to decode matrix data stored in a first format in a shared local memory into a second format for consumption by a plurality of matrix engines.

The invention relates to a distributed file system adaptive to GPU cluster training, a creation method, electronic equipment and a storage medium, and the system comprises a management module which is used for distributing a target GPU cluster to a target training task after the target GPU cluster is distributed to the target training task; a server is created for a plurality of first computer nodes included in the target GPU cluster, a client is created for a plurality of second computer nodes included in the target GPU cluster, and at least one hardware GPU is deployed on each computer node included in the target GPU cluster; the server is used for constructing a GPU cluster distributed file system adaptive to the target training task by utilizing a preset local memory space deployed on the corresponding first computer node; and the client is used for executing IO operation on the GPU cluster distributed file system in the process of executing the target training task by utilizing the target GPU cluster. According to the embodiment of the invention, IO requirements in a GPU cluster training scene can be effectively met.

One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. At least one of the plurality of chiplets including a plurality of processing elements, a distributed shared local memory coupled with the plurality of processing elements, a plurality of matrix engines coupled with the distributed shared local memory, and an asynchronous matrix multiply accumulate (MMA) controller configured to perform an asynchronous MMA operation via the plurality of matrix engines.

The invention relates to a tensor data movement accelerator. One embodiment provides a graphics processor comprising a memory interface and a graphics core cluster comprising a plurality of graphics cores and tensor processing circuitry. The tensor processing circuit includes: a local memory; a tensor accelerator coupled with the local memory, the tensor accelerator configured to perform a matrix multiply-accumulate operation; and a tensor data movement accelerator configured to asynchronously transfer tensor data between a global memory and a local memory coupled to the memory interface. The tensor data moving accelerator includes circuitry configured to convert tensor data from a first tensor format to a second tensor format.

The invention relates to the technical field of distributed computing, and discloses a heavy truck charging load scheduling-oriented distributed energy intelligent matching method, which comprises the following steps of: establishing a charging service computing power mapping table at a scheduling node; maintaining a shadow counter in a local memory, extracting a pre-estimated computing power consumption value according to an event type and accumulating the pre-estimated computing power consumption value to the shadow counter, and executing linear numerical deduction on the shadow counter according to a reference logic subtraction rate so as to simulate a scheduling data throughput evolution process; adjusting a linear deduction rate parameter according to the deviation between the state feedback data and the numerical value of the shadow counter; and distributing the charging matching task to a charging station edge computing node of which the shadow counter value does not exceed a preset logic saturation threshold value. According to the invention, through an open-loop estimation and closed-loop calibration mechanism of a local logic state, an instantaneous congestion risk caused by physical feedback lag is eliminated; and logic state consistency and self-adaptive distribution of the whole network computing power resources are realized.

The invention relates to a data processing method, a processor, a chip, a display card and electronic equipment, and relates to the field of intelligent computing, and the method comprises the following steps: reading a part of a first matrix from a local memory or a register of a computing unit in response to M tensor computing engines in a tensor computing engine cluster, reading the second matrix from the tensor memory, and executing matrix operation by the M tensor calculation engines according to part of the first matrix and the second matrix respectively to obtain operation results corresponding to the M tensor calculation engines; and the M tensor calculation engines respectively write operation results corresponding to the M tensor calculation engines into registers of the M tensor calculation engines. According to the embodiment of the invention, the computing power can be increased under the condition that the sizes and the bandwidths of the local memory and the register in the computing unit are not increased.

The invention discloses a consistency interconnection control device and method, an electronic device, a product and a computing system, and relates to the technical field of computers, the consistency interconnection control device is provided and comprises a consistency interconnection network, a first controller and a first connector, the consistency interconnection network comprises a plurality of interconnected consistency interconnection nodes, the consistency interconnection node is connected with the first card slot for installing the acceleration card through the first connector, and the first controller manages the state of the cache line of the acceleration card and controls the consistency interconnection network to execute the consistency interconnection read-write task between different acceleration cards, so that the consistency interconnection system for the acceleration computing cluster is realized. By implementing the cache consistency between the acceleration cards, when the acceleration computing cluster executes distributed computing, the cache can be hit firstly, so that access to a local memory and memories of other acceleration cards is reduced, the problem of high time consumption of communication between different accelerators of the acceleration computing cluster is solved, and the efficiency of distributed computing is improved.

The embodiment of the invention provides a code compiling method, electronic equipment and a storage medium. The code compiling method is used for compiling a code comprising at least one thread local storage variable, and comprises the following steps: in response to existence of a target thread local storage variable, allocating the at least one target thread local storage variable to a thread local memory based on an attribute of the at least one target thread local storage variable, obtaining a thread local memory address corresponding to each target thread local storage variable, wherein the target thread local storage variable is the thread local storage variable used by the first function; updating an intermediate representation corresponding to the code based on a thread local memory address corresponding to each target thread local storage variable; and generating a machine code corresponding to the code based on the updated intermediate representation. According to the code compiling method, thread local storage model support under a parallel computing architecture is provided, and the problem that traditional thread local storage implementation cannot be directly applied to a GPU architecture is solved.

A central node can: receive a query comprising at least one parameter comprising a time range of a dataset stored in a cloud storage system; transmit one or more of the query parameters comprising the time range to a metadata service; receive from the metadata service a list of files related to the query; and assign to each processing node of a plurality of processing nodes a subset of the files. Each processing node can: determine that the subset is not stored on a cache; retrieving the subset not stored on the cache from the cloud storage system; store the retrieved subset in a local memory; scan the subset stored in the local memory for data matching the at least one parameter to generate a subset of query results; and concurrently copy using a separate thread from the scanning, the subset stored in the local memory to the cache.

An apparatus and method for efficiently processing vector memory accesses on an integrated circuit. In various implementations, a computing system includes a processing circuit with multiple compute circuits for executing wavefronts of a parallel data application. Each compute circuit includes a local memory subsystem for accessing data not found in vector register files of the compute circuit. The local memory subsystem includes a first execution pipeline and a second execution pipeline. The second execution pipeline processes vector stack access instructions that access temporary data such as stack data of a function call used by each wavefront that is generated based on the function call. The first execution pipeline processes other types of vector memory access instructions and includes multiple complex pipeline stages not found in the second execution pipeline. Thus, the second execution pipeline has a latency less than the latency of the first execution pipeline.

The embodiment of the invention provides a memory allocation method and device.The method comprises the steps that under the condition that page table page allocation is determined to be conducted on a target page table of a target process, a resource binding mechanism corresponding to the target process is obtained; according to a memory node binding constraint in the resource binding mechanism, determining a target memory node corresponding to the target process, and allocating a page table page for the target page table at the target memory node; when it is determined that the local memory of the target memory node is insufficient, so that the page table page allocation fails, a target physical page in the local memory is migrated to a first remote memory node, and the step of allocating the page table page to the target page table at the target memory node continues to be executed until the page table page allocation succeeds. By forcibly distributing the pages of the page table at the target memory node and combining with an intelligent memory migration mechanism, the performance loss caused by remote access of the page table is fundamentally eliminated.

An optical transceiver includes an electro-optic front end; a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC) connected to the electro-optic front end; and one or more Field Programmable Gate Arrays (FPGAs) connected to the DAC and the ADC, wherein the one or more FPGAs are connected to one or more of a local memory and a remote storage for loading FPGA bit files, and wherein the one or more FPGAs are loaded with a forward error correction (FEC) encoding app and a FEC decoding app. The FEC encoding app and the FEC decoding app can be selected based on any of an optical application and a standard compliance requirement.

The invention discloses a heterogeneous memory page migration device and method and a readable storage medium, and relates to the technical field of data processing, the heterogeneous memory page migration device comprises a first computing unit, a migration unit and a memory unit, and the migration unit comprises a communicator and a processor; a communicator configured to receive an address translation request; the processor is configured to transmit page contents of a remote page to a local memory frame according to a remote physical frame number in a first page table item when determining that the target page in the address conversion request is the remote page, and replace the remote physical frame number in the first page table item with a local physical frame number; and the communicator is further configured to return the second page table item to the first computing unit, so that the problem of relatively long time consumption when the computing unit accesses a remote page and triggers a page error in the related technology is solved, and the time consumption for migrating the heterogeneous memory page is saved.

Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.

The invention discloses a separated memory-oriented page migration method and system, and belongs to the field of data storage. The page migration method comprises the following steps that: a node dynamically samples the access condition of a page through NUMA Balancing, tracks and marks the access record of the page; static screening is carried out in combination with an LRU list, hot pages are obtained through identification, and other pages are marked as cold pages; storing the identified hot pages and cold pages in a hot to-be-migrated queue and a cold to-be-migrated queue respectively; the background kernel thread continuously obtains to-be-migrated hot pages and cold pages from the hot to-be-migrated queue and the cold to-be-migrated queue, asynchronous page migration is conducted, the hot pages are migrated to the node from the far-end memory node, and the cold pages of the node are migrated to the far-end memory node; when the page is migrated, the access of the user to the page is decoupled. Preferentially migrating a real high-frequency access page to a local memory node; the hit rate of local memory access is improved, and the delay of remote memory access is reduced.

The invention discloses a structured data storage method based on natural language transformation, which comprises the following steps of: a system initialization configuration stage: deploying a protocol adapter in a local memory of a PC (Personal Computer) client, and loading natural language processing pipeline configuration parameters; a heterogeneous data acquisition stage: capturing a multi-source text data stream through the protocol adapter, uniformly converting the multi-source text data stream into a standardized data packet, and sending the standardized data packet to a message queue theme; a text cleaning stage: a named entity recognition stage: inputting the pure text data into an NER module deployed with a language model loader; in the conditional feature extraction stage, feature vectors are generated for texts meeting preset conditions on the basis of entity type tags in the entity recognition result; and a consistent storage stage: inserting the entity identification results into a relational database in batches, and updating the entity mapping relationship in the cache. According to the method, the intelligent level of cache management is remarkably improved, and the access fluency of the key data of the user is guaranteed.

A memory page management method, system and apparatus, a device, and a computer non-volatile readable storage medium, relating to the technical field of memory management. The method comprises: acquiring a target virtual address of data to be accessed; on the basis of the target virtual address, searching an address translation cache for a physical address; if the corresponding physical address to be accessed is found from the address translation cache, reading, from the physical address to be accessed, target data to be accessed; and if the physical address to be accessed is not found from the address translation cache, on the basis of the target virtual address, concurrently searching a plurality of groups of unifiedly addressed page tables for the physical address, and if the physical address to be accessed is found, reading, from the physical address to be accessed, the target data to be accessed, wherein a local memory comprises a memory in a target node, and the other memories comprise memories in nodes other than the target node. The memory that can be used by a target processor is expanded, and the working load efficiency and performance of a processor are improved.

The invention provides a memory access method and electronic equipment, and is applied to the technical field of accelerator systems. The memory access method comprises the following steps: determining a target memory access strategy from a preset memory access strategy set according to a local memory access feature of any computing core; under the condition that the target memory access strategy is a transmission optimization strategy, position information of the to-be-accessed data in a target cache line is determined according to a target cache line address in an initial memory access request initiated by any computing core; generating a bit mask for identifying the to-be-accessed data according to the position information; and adding the bit mask to the initial memory access request to form a memory access request, sending the memory access request to a target device to which the target cache line address belongs, and returning the to-be-accessed data by the target device according to the bit mask in the memory access request.