Process scheduling method and device based on NUMA architecture, electronic equipment and storage medium

Abstract

The invention discloses a process scheduling method and device based on an NUMA framework, electronic equipment and a storage medium, and relates to the technical field of computer systems.The process scheduling method comprises the steps that in the process running process, comprehensive performance scores of all NUMA nodes are calculated by obtaining performance index data corresponding to all the NUMA nodes respectively, and the performance index data of all the NUMA nodes are obtained; the target NUMA node is selected based on the comprehensive performance score to be bound with the execution core of the current running process, and the required memory page is pre-allocated for the current running process in the local memory area of the target NUMA node, so that the current running process can access the local memory of the bound NUMA node, the probability that the process accesses the memory across the NUMA node is reduced, and the memory access efficiency is improved. Therefore, the technical problem that the memory access delay is remarkably increased due to the fact that the process frequently accesses the memory across the NUMA nodes can be solved, and the technical effects of shortening the memory access delay and improving the system performance are achieved.

Description

Technical Field

[0001] The present application relates to the technical field of computer systems, and in particular, to a process scheduling method, apparatus, electronic device, and storage medium based on the NUMA architecture. Background Art

[0002] In the current era of rapid development of computer technology, multi-core processors and the Non-Uniform Memory Access (NUMA) architecture have become the key foundation for building high-performance computer systems. The NUMA architecture divides the system memory into multiple independent NUMA nodes, and each node has its own dedicated local memory and processor cores.

[0003] Under the above NUMA architecture, when a processor needs to access the memory of other NUMA nodes, it will cause a large access delay. Especially when running a process involving a device of the Peripheral Component Interconnect Express (PCIe) standard, the process frequently accesses memory across NUMA nodes, resulting in a significant increase in memory access latency and affecting system performance. Summary of the Invention

[0004] The present application provides a process scheduling method, apparatus, electronic device, and storage medium based on the NUMA architecture, so as to at least solve the problem in the related art that the process frequently accesses memory across NUMA nodes, resulting in a significant increase in memory access latency.

[0005] The present application provides a process scheduling method based on the NUMA architecture, including:

[0006] During the running of the process, obtaining performance metric data respectively corresponding to multiple NUMA nodes;

[0007] Based on the performance metric data, determining comprehensive performance scores respectively corresponding to the multiple NUMA nodes;

[0008] Based on the comprehensive performance scores respectively corresponding to the multiple NUMA nodes, determining a target NUMA node from the multiple NUMA nodes;

[0009] Binding the execution core of the currently running process to the processor core of the target NUMA node, and pre-allocating memory pages required by the currently running process in the local memory area of the target NUMA node.

[0010] The present application also provides a process scheduling apparatus based on the NUMA architecture, including:

[0011] A data acquisition module, configured to acquire performance metric data corresponding to multiple NUMA nodes respectively during the running of a process;

[0012] A first determination module, configured to determine comprehensive performance scores corresponding to the multiple NUMA nodes respectively based on the performance metric data;

[0013] A second determination module, configured to determine a target NUMA node from the multiple NUMA nodes based on the comprehensive performance scores corresponding to the multiple NUMA nodes respectively;

[0014] A node binding module, configured to bind the execution core of the currently running process to the processor core of the target NUMA node, and pre-allocate memory pages required by the currently running process in the local memory area of the target NUMA node.

[0015] This application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any one of the above NUMA architecture-based process scheduling methods when executing the computer program.

[0016] This application also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any one of the above NUMA architecture-based process scheduling methods are implemented.

[0017] This application also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of any one of the above NUMA architecture-based process scheduling methods are implemented.

[0018] Through this application, during the running of a process, by acquiring the performance metric data corresponding to each NUMA node respectively to calculate the comprehensive performance scores of each NUMA node, selecting a target NUMA node based on the comprehensive performance scores to bind to the execution core of the currently running process, and pre-allocating the required memory pages for the currently running process in the local memory area of the target NUMA node, it is only necessary for the currently running process to access the local memory of the bound NUMA node, reducing the probability of the process accessing memory across NUMA nodes, thereby shortening the memory access latency. Therefore, the technical problem of significant increase in memory access latency caused by the process frequently accessing memory across NUMA nodes can be solved, and the technical effects of shortening the memory access latency and improving the system performance can be achieved. Description of the Drawings

[0019] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0020] Figure 1 It shows a schematic diagram of the NUMA architecture in the related art;

[0021] Figure 2 It is a schematic flowchart of a process scheduling method based on the NUMA architecture provided by an embodiment of the present application;

[0022] Figure 3 It is a schematic flowchart of another process scheduling method based on the NUMA architecture provided by an embodiment of the present application;

[0023] Figure 4 It is a schematic structural diagram of a scheduling system according to an exemplary embodiment of the present application;

[0024] Figure 5 It is a schematic structural diagram of a process scheduling device based on the NUMA architecture provided by an embodiment of the present application. Detailed implementation manners

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0026] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0027] To enable those skilled in the art of the present technology to better understand the solution of the present application, the following further details the present application with reference to the accompanying drawings and specific implementation manners.

[0028] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the process scheduling method based on the NUMA architecture depends, the specific application environment architecture or specific hardware architecture is described herein.

[0029] In today's era of rapid development of computer technology, multi-core processors and NUMA architecture have become the key foundation for building high-performance computing systems. Figure 1 A schematic diagram of a NUMA architecture in the related art is shown. Figure 1 It can be seen that the NUMA architecture breaks through the limitations of the traditional unified memory access mode, divides the system memory into multiple independent NUMA nodes, and divides the central processing unit (CPU) into multiple NUMA nodes, where the processors are connected through the Intel QuickPath Interconnect (QPI) bus. In other words, in a computer system using the NUMA architecture, each NUMA node not only has its own local memory, but is also equipped with a specific set of processor cores. Under this architecture, when the processor accesses the local memory, due to the short data transmission path, the access speed of the local memory is the fastest, and the access delay can be controlled at an extremely low level; when the processor needs to access the remote memory, that is, to access the memory of other NUMA nodes, the data transmission needs to go through a more complex system bus and network topology, which will cause the access delay to increase significantly.

[0030] In addition, PCIe, as a high-speed serial computer expansion bus standard, is widely used to connect various external devices and computer systems with its excellent high-speed data transmission capabilities. From high-performance graphics processing units (GPUs), large-capacity storage devices to high-speed data acquisition cards, many key external devices rely on PCIe interfaces to achieve efficient communication with computer systems.

[0031] However, the traditional process scheduling mechanism does not fully consider the characteristics of the NUMA architecture. It is often unable to accurately match processes with memory resources, resulting in frequent cross-node memory access by processes, thereby increasing memory access latency. When running processes involving PCIe devices, due to the lack of a reasonable scheduling strategy, the process may frequently access memory across NUMA nodes when accessing data that interacts with PCIe devices. This unreasonable memory access method will not only increase the latency of memory access, but also intensify competition for system bus resources, thereby seriously restricting the overall performance of the system. For example, in data-intensive application scenarios such as big data analysis and scientific computing, the increase in memory access latency will significantly reduce the data transmission rate; in tasks with high real-time requirements such as video stream processing and real-time control systems, the task execution time will be significantly extended, and may even cause the task to fail.

[0032] Based on the above problems, the present application focuses on computer systems adopting the NUMA architecture, deeply studies the technical solutions for realizing the efficient operation of PCIe processes, and proposes an innovative solution for comprehensively optimizing the binding of PCIe processes to NUMA nodes. By optimizing the data processing flow of PCIe devices in the computer system and selecting appropriate NUMA nodes to bind with the processes based on the comprehensive performance scores of each NUMA node, this process greatly reduces the number of memory accesses across NUMA nodes, significantly reduces the memory access latency, solves the problem in related technologies that due to the unreasonable utilization of the NUMA architecture characteristics, the memory access latency of PCIe processes is too high and the system performance is limited, helps to comprehensively improve the overall performance of the system and the resource utilization efficiency, and provides solid technical support for the efficient operation of the computer system.

[0033] An embodiment of the present application provides a process scheduling method based on the NUMA architecture. In combination with the execution process of the process scheduling method based on the NUMA architecture, the method is described in detail.

[0034] Figure 2 FIG. is a schematic flow chart of a process scheduling method based on the NUMA architecture provided by an embodiment of the present application. This method can be executed by a process scheduling device based on the NUMA architecture provided by an embodiment of the present application and can be integrated in an electronic device, which is a device adopting the NUMA architecture.

[0035] As Figure 2 shown, the process scheduling method based on the NUMA architecture includes the following steps:

[0036] Step 101, during the running of the process, obtain the performance index data corresponding to multiple NUMA nodes respectively.

[0037] Among them, the multiple NUMA nodes are all NUMA nodes in the computer system.

[0038] In this embodiment, during the running of the process (i.e., the currently running process), the process scheduling device based on the NUMA architecture can obtain the performance index data corresponding to each NUMA node.

[0039] Among them, the performance metrics used to represent the performance of NUMA nodes can be preset according to actual needs. Key performance metrics are predefined for each NUMA node and PCIe device, including but not limited to memory access latency, processor core utilization, PCIe device bandwidth utilization, etc. The process scheduling device based on the NUMA architecture can periodically collect the performance metric data of these performance metrics during the process running. For example, data sampling can be performed every T time interval to obtain the performance metric data corresponding to each NUMA node, where the value of T can be set according to actual needs. For example, T can be set to 10 seconds.

[0040] Step 102: Based on the performance metric data, determine the comprehensive performance scores corresponding to multiple NUMA nodes respectively.

[0041] In this embodiment, after obtaining the performance metric data corresponding to each NUMA node, the comprehensive performance score determination rule predefined in advance can be followed. For each NUMA node, the performance metric data of this NUMA node is used to determine the comprehensive performance score corresponding to this NUMA node, so as to obtain the comprehensive performance scores corresponding to each NUMA node.

[0042] As an example, for each NUMA node, its performance metric data can be normalized and then the mean value is calculated, and the obtained mean value is used as the comprehensive performance score of this NUMA node. Alternatively, after normalization, the processed data can be summed as the comprehensive performance score of this NUMA node.

[0043] Step 103: Based on the comprehensive performance scores corresponding to multiple NUMA nodes respectively, determine the target NUMA node from multiple NUMA nodes.

[0044] In this embodiment, after determining the comprehensive performance scores corresponding to each NUMA node respectively, the comprehensive performance scores of all NUMA nodes can be compared, and the NUMA node with the best performance is selected from all NUMA nodes as the target NUMA node according to the comprehensive performance score.

[0045] It can be understood that the selection of the target NUMA node with the best performance is related to the selected performance metrics. If the larger the data of the performance metric indicates the better the performance of the NUMA node, then according to the comprehensive performance scores of each NUMA node, the NUMA node with the highest comprehensive performance score is selected as the target NUMA node; if the smaller the data of the performance metric indicates the better the performance of the NUMA node, then according to the comprehensive performance scores of each NUMA node, the NUMA node with the lowest comprehensive performance score is selected as the target NUMA node.

[0046] Step 104: Bind the execution core of the currently running process to the processor core of the target NUMA node, and pre-allocate the memory pages required by the currently running process in the local memory area of the target NUMA node.

[0047] In this embodiment, after determining the target NUMA node with the optimal performance, the execution core of the currently running process can be bound to the processor core of the target NUMA node, so that the currently running process runs based on the processor core of the target NUMA node, and the memory pages required by the currently running process are pre-allocated in the local memory area of the target NUMA node, so that the currently running process preferentially accesses the memory of the bound NUMA node, thereby reducing the probability of the process accessing memory across NUMA nodes. For example, in the big data analysis scenario, the process can quickly obtain the data interacting with the PCIe device from the local memory of the bound NUMA node without transmitting data in the complex system bus and network topology, effectively improving the data reading speed, significantly reducing the memory access latency, and providing a solid guarantee for the high-speed data processing of the system.

[0048] It can be understood that in the embodiment of the present application, during the process execution, the process scheduling device based on the NUMA architecture continuously monitors the memory access behavior of the currently running process, and obtains the performance metric data of each NUMA node to calculate the comprehensive performance score of each NUMA node, so as to dynamically adjust the system resources of the currently running process according to the comprehensive performance score, and timely adjust the execution core binding and memory page allocation strategy of the process, and preferentially allocate or migrate the process to the NUMA node with the optimal performance, ensuring that the system always allocates resources reasonably according to the actual needs of the process, and realizing the optimization of the system performance. For example, in the video encoding task, as the encoding stage changes, the dependence of the process on the GPU and storage devices will change. The solution of the present application can dynamically adjust the resource allocation according to this change, ensure that the system resources are always optimally configured, further improve the stability and reliability of the system, and enable it to adapt to the complex and changeable actual application requirements.

[0049] In the process scheduling method based on the NUMA architecture according to the embodiments of the present application, during the running of a process, by obtaining the performance index data corresponding to each NUMA node respectively to calculate the comprehensive performance score of each NUMA node, based on the comprehensive performance score, a target NUMA node is selected to be bound to the execution core of the currently running process, and the required memory pages are pre-allocated for the currently running process in the local memory area of the target NUMA node, so that the currently running process can access the local memory of the bound NUMA node, reducing the probability of the process accessing memory across NUMA nodes, thereby shortening the memory access latency. Therefore, the technical problem of significant increase in memory access latency caused by the process frequently accessing memory across NUMA nodes can be solved, and the technical effects of shortening the memory access latency and improving the system performance can be achieved.

[0050] In an alternative embodiment of the present application, as Figure 3 shown, on the basis of the foregoing embodiment, the solution of the present application further includes the following steps:

[0051] Step 201, identify the connected external devices and obtain the port information of the external devices.

[0052] Among them, the external device refers to a device connected to the computer system using the PCIe standard, and the external device is connected to the computer system through a PCIe interface.

[0053] As an example, in the initial stage of the computer system startup, the PCIe device identification mechanism implanted in the computer system can be used to identify the external devices connected to the computer system. Among them, the currently common PCIe device identification mechanism can be used to identify the external devices. Different computer systems may use different PCIe device identification mechanisms, and the present application does not limit this. Through the PCIe device identification mechanism, all PCIe devices connected to the computer system can be quickly and accurately identified. Moreover, the PCIe device identification mechanism can further determine the physical PCIe port to which each PCIe device is connected, and record the corresponding port information in detail, and output the port information. These information will become important basic data for subsequent system resource management and scheduling, providing data support.

[0054] Step 202, obtain the memory layout information of multiple NUMA nodes and the topological connection relationship between the multiple NUMA nodes and the ports of the external devices.

[0055] Among them, the port of the external device refers to the PCIe port to which the external device is connected to access the computer system.

[0056] In this embodiment, the process scheduling device based on the NUMA architecture also comprehensively probes each NUMA node in the computer system to obtain the memory layout information of each NUMA node. The memory layout information includes, but is not limited to, memory capacity, memory module distribution, processor core distribution, etc. Moreover, the topological connection relationship between each NUMA node and the ports of external devices is also obtained. It can be understood that external devices are connected to the computer system through PCIe ports. Obtaining the topological connection relationship between a NUMA node and a PCIe port means obtaining the connection relationship between the NUMA node and the external device.

[0057] Step 203: Construct a system resource topology graph based on the memory layout information and topological connection relationships of multiple NUMA nodes.

[0058] In this embodiment, after obtaining the port information of the above-mentioned external devices and their connected ports, as well as the memory layout information of each NUMA node and the topological connection relationship between each NUMA node and the ports of external devices, a detailed system resource topology graph can be constructed based on this information. The system resource topology graph records the information of each NUMA node and its memory capacity, memory module distribution, processor core distribution, etc., and also records the external devices connected to each NUMA node. Through the memory module distribution information recorded in the system resource topology graph, the distance between the memories of each NUMA node can be determined, providing data support for subsequent memory allocation.

[0059] In an alternative embodiment of the present application, the system resource topology graph can be stored in the form of a database or a configuration file for subsequent query and update. Among them, in scenarios such as adding external devices or removing some external devices, the external devices connected to the computer system can be re-identified, the memory layout information of NUMA nodes can be obtained, etc., and the system resource topology graph can be updated based on the newly obtained information. When scheduling system resources in this solution, the resource allocation strategy will be dynamically adjusted according to the real-time update of the topology graph to ensure that the resource allocation always remains optimal when the system hardware or software environment changes.

[0060] The process scheduling method based on the NUMA architecture in the embodiment of the present application identifies the connected external devices, obtains the port information of the external devices, obtains the memory layout information of multiple NUMA nodes, and the topological connection relationships between multiple NUMA nodes and the ports of external devices, and then constructs a system resource topology graph based on the memory layout information and topological connection relationships of multiple NUMA nodes. The system resource topology graph provides a comprehensive and accurate data source for subsequent adaptive scheduling of system resources. The accurate system resource topology graph lays a foundation for accurate system resource invocation, thus ensuring the scientificity and rationality of resource allocation decisions.

[0061] Further, in an alternative embodiment of the present application, based on constructing a system resource topology diagram as shown in Figure 3 the embodiment, when obtaining the performance index data corresponding to multiple NUMA nodes, the system resource topology diagram can be traversed to determine the currently traversed node and the first external device having a topological connection relationship with the currently traversed node; obtain the index data of the first performance index corresponding to the currently traversed node, and obtain the index data of the second performance index corresponding to the first external device; after traversing the system resource topology diagram, obtain the performance index data corresponding to multiple NUMA nodes respectively.

[0062] Among them, the number of the first performance indexes is at least one, and the number of the second performance intelligences is at least one. The first performance index refers to the key performance indexes predefined for the NUMA node, including but not limited to memory access latency and processor core utilization rate; the second performance index refers to the key performance indexes predefined for the external device, including but not limited to the bandwidth utilization rate of the external device.

[0063] In this embodiment, since the system resource topology diagram is constructed according to the memory distribution information of all detected NUMA nodes and the topological connection relationship between the ports of the external devices, based on the constructed system resource topology diagram, all NUMA nodes in the computer system can be traversed, and the external devices associated with each NUMA node can be determined. Furthermore, the index data of the first performance index corresponding to the NUMA node and the index data of the second performance index corresponding to the connected external device can be obtained, providing data support for accurate system resource scheduling. Moreover, since the system resource topology diagram supports real-time update, there is no need to detect the NUMA node each time. Based on the system resource topology diagram, the latest relevant information of the NUMA node can be obtained, which helps to reduce the time-consuming of process scheduling and thus improve the overall performance of the system.

[0064] The influence of the same performance metric on the comprehensive performance scores of NUMA nodes in different types of tasks is usually different, which can be characterized by corresponding weights. For example, for real-time tasks sensitive to latency, the metric of memory access latency has a greater impact on the comprehensive performance score. Therefore, for latency-sensitive tasks, a larger weight can be assigned to memory access latency; for compute-intensive tasks, the metric of processor core utilization has a greater impact on the comprehensive performance score. Therefore, for compute-intensive tasks, a larger weight can be assigned to processor core utilization. Therefore, in an alternative embodiment of the present application, when determining the comprehensive performance score corresponding to a NUMA node based on performance metric data, the first weight corresponding to the first performance metric and the second weight corresponding to the second performance metric can be determined based on the task type of the currently running process. Then, the metric data of the first performance metric and the metric data of the second performance metric can be normalized respectively to obtain the first normalized metric data and the second normalized metric data. Furthermore, based on the first normalized metric data and the second normalized metric data of the same NUMA node, weighted summation is performed using the first weight and the second weight to obtain the comprehensive performance scores corresponding to multiple NUMA nodes respectively.

[0065] Exemplarily, different weights can be set for each performance metric for different task types in advance, and these weights can be dynamically adjusted by the user according to the actual requirements of the system and the real-time performance. The sum of the weights corresponding to all performance metrics is 1. For example, for tasks with frequent data reading and writing such as big data analysis, the weight corresponding to memory access latency is set to be the largest, the weight corresponding to processor core utilization is set to be the smallest, and the weight corresponding to external device bandwidth utilization is 1 minus the difference between the two; for tasks of the graphics rendering type, since such tasks are sensitive to latency and GPU performance, a larger weight can be set for memory access latency and external device bandwidth utilization, while a smaller weight can be set for processor core utilization. Therefore, in this embodiment, according to the task type of the currently running process, the corresponding weight combination can be determined, and this weight combination includes the first weight corresponding to the first performance metric and the second weight corresponding to the second performance metric.

[0066] Since the units and orders of magnitude of each performance metric are different, direct weighting will affect the accuracy and rationality of the comprehensive performance score. Therefore, in this embodiment, before determining the comprehensive performance score, the metric data of each performance metric is normalized first. For example, the value range of the metric data corresponding to each performance metric can be unified to the interval [0, 1] to achieve the normalization of the metric data.

[0067] As an alternative implementation, when performing normalization processing, for any performance metric, the metric data of this performance metric for all NUMA nodes obtained this time can be analyzed, and the maximum value and minimum value among these metric data can be determined. Then, based on the determined maximum value and minimum value, the metric data of each performance metric is normalized to obtain the normalized metric data corresponding to this performance metric. For example, the normalized metric data can be expressed as the ratio of the difference between the metric data of the performance metric minus the minimum value to the difference between the maximum value minus the minimum value. Among them, the first performance metric and the second performance metric can be normalized using the same normalization method. The result obtained by normalizing the metric data of the first performance metric is called the first normalized metric data, and the result obtained by normalizing the metric data of the second performance metric is called the second normalized metric data.

[0068] Taking the memory access latency as an example of the performance metric, assuming that the maximum value of the determined metric data is L max , and the minimum value of the metric data is L min , then the metric data of the normalized memory access latency can be expressed as:

[0069]

[0070] where L' i represents the normalized metric data of the memory access latency of the i-th NUMA node, and L i represents the metric data of the memory access latency of the i-th NUMA node.

[0071] In this embodiment, by normalizing the metric data of each performance metric to obtain the corresponding normalized metric data, the order of magnitude of the data of different performance metrics is unified, laying a foundation for subsequently determining the comprehensive performance score of the NUMA node by weighting, and ensuring the accuracy and rationality of the determined comprehensive performance score; moreover, when performing normalization calculation, by determining the maximum value and minimum value from the performance data of the performance metrics obtained for normalization calculation, there is no need to set additional parameters for normalization processing, optimizing the normalization method.

[0072] Next, for each NUMA node, by using the weights of each performance metric and the normalized metric data of the same NUMA node obtained, the comprehensive performance score corresponding to each NUMA node can be obtained through weighted summation.

[0073] Exemplarily, assuming that the first performance metric includes memory access latency and processor core utilization rate, and the second performance metric includes external device bandwidth utilization rate, where the weight corresponding to the memory access latency is denoted as w L , and the weight corresponding to the processor core utilization rate is denoted as w U, the bandwidth utilization rate of the external device is denoted as w B , then the comprehensive performance score of the i-th NUMA node (denoted as S i ) can be expressed by the following formula:

[0074] S i = w L × L' i + w U × U i ' + w B × B i '.

[0075] Among them, L' i represents the normalized index data corresponding to the memory access latency of the i-th NUMA node, U i ' represents the normalized index data corresponding to the processor core utilization rate of the i-th NUMA node, and B i ' represents the normalized index data corresponding to the bandwidth utilization rate of the external device of the i-th NUMA node.

[0076] For example, in a big data analysis center, the server adopts a configuration of dual NUMA nodes (denoted as N1 and N2) and multiple PCIe devices. When the system starts, by identifying PCIe devices, it quickly identifies PCIe devices such as high-speed data acquisition cards and large-capacity storage devices and their connection ports. At the same time, by performing NUMA detection, it obtains information such as the memory layout and processor core distribution of N1 and N2, and constructs a system resource topology map. When a big data analysis process starts, this process needs to obtain a large amount of data from the high-speed data acquisition card with a PCIe interface and frequently read and write the storage device with a PCIe interface. Through process analysis, the main interaction devices can be judged. In the initial stage, the normalized memory access latency L′ 1 of N1 = 0.5, the processor core utilization rate U 1 ′ = 0.6, and the PCIe device bandwidth utilization rate B 1 ′ = 0.4; the normalized memory access latency L′ 2 of N2 = 0.6, the processor core utilization rate U 2 ′ = 0.3, and the PCIe device bandwidth utilization rate B 2 ′ = 0.5. For tasks with frequent data reading and writing such as big data analysis, the memory access latency weight w L = 0.5, the processor core utilization rate weight w U = 0.2, and the PCIe device bandwidth utilization rate weight w B = 0.3.

[0077] Calculate the comprehensive performance scores corresponding to N1 and N2 respectively:

[0078] S1 = 0.5×0.5 + 0.2×0.6 + 0.3×0.4 = 0.49

[0079] S2 = 0.5×0.6 + 0.2×0.3 + 0.3×0.5 = 0.51

[0080] Since S1 < S2, bind the process execution core to the processor core within N1 and pre - allocate the memory pages to the local memory area of N1. During the process of running the process, collect performance metric data every once in a while (such as every 10 seconds). If, as the analysis progresses, the normalized processor core utilization rate of N1 rises to 1 and at this time the comprehensive performance score of N2 is lower, the system will then migrate the process to N2.

[0081] For another example, in a professional graphics workstation, the system has multiple NUMA nodes (assumed to be N1, N2, N3) and a complex PCIe device configuration, including a GPU for graphics acceleration and high - speed storage devices. When the system starts up, device recognition and system resource topology map construction are performed. When a 3D graphics rendering process starts, through process analysis, it is determined that the main interactive devices are the GPU and the storage device. Assume that the connection bandwidth between N1 and the GPU is higher, the memory access latency of N2 is lower, and the processor core of N3 performs better in graphics processing algorithms. Initially, the normalized memory access latency L′ of N1 1 = 0.5, the processor core utilization rate U 1 ′ = 0.4, the PCIe device bandwidth utilization rate B 1 ′ = 0.8; the normalized memory access latency L′ of N2 2 = 0.3, the processor core utilization rate U 2 ′ = 0.5, the PCIe device bandwidth utilization rate B 2 ′ == 0.6; the normalized memory access latency L′ of N3 3 = 0.4, the processor core utilization rate U 3 ′ = 0.3, the PCIe device bandwidth utilization rate B 3 ′ = 0.7. For a task like graphics rendering that is sensitive to latency and GPU performance, set the memory access latency weight w L = 0.4, the processor core utilization rate weight w U = 0.2, the PCIe device bandwidth utilization rate weight w B = 0.4.

[0082] Calculate the comprehensive performance scores corresponding to N1, N2, and N3 respectively:

[0083] S1 = 0.4×0.5 + 0.2×0.4 + 0.4×0.8 = 0.60

[0084] S2 = 0.4×0.3 + 0.2×0.5 + 0.4×0.6 = 0.46

[0085] S3 = 0.4×0.4 + 0.2×0.3 + 0.4×0.7 = 0.50

[0086] Since S2 < S1 and S2 < S3, bind the process execution core to the processor core of N2, and pre-allocate the memory pages to the local memory area of N2. During the rendering process, if it is found that the bandwidth utilization rate of the GPU continues to increase, resulting in an increase in the comprehensive performance score of N2, while the resource utilization rate of N1 decreases due to the end of other processes and the comprehensive performance score is better, the system will migrate the graphics rendering process to N1.

[0087] As can be seen from the above examples, the solution of the present application can effectively improve the running efficiency of processes involving PCIe devices in different scenarios, reduce memory access latency, give full play to the synergistic advantages of the NUMA architecture and PCIe devices, and provide strong support for the performance optimization of computer systems.

[0088] In this embodiment, by determining the weights corresponding to each performance index according to the task type of the task executed by the currently running process, it is possible to flexibly select appropriate weights for the task type, which helps to improve the accuracy of the comprehensive performance score; by normalizing the index data of each performance index to obtain the normalized index data, the index data of different performance indexes can be unified, which is convenient for weighting, and then the comprehensive performance scores of each NUMA node are determined by weighted summation, ensuring the accuracy and rationality of the obtained comprehensive performance scores, thereby helping to ensure the accuracy of system resource scheduling.

[0089] In an alternative embodiment of the present application, when a new process starts, the process scheduling device based on the NUMA architecture can first detect whether the new process involves interaction with external devices. For example, when it is detected that the new process needs to access devices such as network cards, or involves input / output (I / O) related information, it can be determined that the new process involves interaction with external devices. In the case of determining that the new process involves interaction with external devices, the new process is further analyzed to obtain the memory access parameters corresponding to the new process and the second external device interacting with the new process, and then based on the memory access parameters, the second external device and the system resource topology map, the execution core of the new process is initially bound.

[0090] Among them, the memory access parameters include but are not limited to memory access patterns (such as random access, sequential access, etc.), the required memory size, etc.

[0091] In this embodiment, when a new process starts and involves external device interaction, a comprehensive and in-depth analysis can be performed on the new process, comprehensively considering various factors such as memory access instructions issued during the process operation, data transfer frequency, and data flow direction, accurately determining which external devices the process mainly exchanges data with, so as to determine the second external device interacting with the new process.

[0092] As an example, a set of process matching rules can be preset, including rules summarized according to different application scenarios and PCIe device characteristics. When performing process analysis, the memory access behavior during the process operation is matched with these rules. For example, for large data storage and retrieval applications, the rule can be set that if the process frequently accesses a large-capacity storage device of the PCIe interface within a short period of time, and the data transfer volume is large, and there is also data transfer to the CPU or other computing units, then it is determined that the process mainly interacts with the storage device. Through this rule-based intelligent analysis, the main PCIe device interaction object of the process can be determined quickly and accurately.

[0093] In this embodiment, when performing the preliminary binding of the new process, the relevant information of each NUMA node recorded in the system resource topology map can be combined to select a NUMA node that can meet the memory access parameters of the new process, such as the memory access mode of the NUMA node is the same as that of the new process, and the associated external device is at least partially the same as the second external device, and bind it to the execution core of the new process to achieve the preliminary binding of the new process.

[0094] It can be understood that after the new process runs, it becomes the currently running process. During the process execution, the process scheduling device based on the NUMA architecture regularly collects the performance index data of each NUMA node, calculates the comprehensive performance score of each NUMA node, and dynamically adjusts the binding relationship between the currently running process and the NUMA node based on the comprehensive performance score to achieve dynamic adjustment of the resource allocation priority of the currently running process.

[0095] In this embodiment, by performing process analysis on the started new process to obtain the corresponding memory access parameters and the interacting external devices, and based on this information and the system resource topology map, the preliminary binding of the new process is realized, achieving the rapid binding of the newly started process. Moreover, the accurate process analysis provides a basis for realizing dynamic system resource scheduling, and can realize flexible adjustment of resource configuration according to the actual needs of the process.

[0096] Furthermore, the result of the process analysis of the new process can also assist the subsequent resource allocation decision-making process. According to the memory access parameters of the new process, combined with the system resource topology map, memory resources are allocated to the new process.

[0097] In an optional embodiment of the present application, the memory access parameters include a required memory size. After the target NUMA node is determined, when allocating the required memory pages for the currently running process, memory is allocated to the currently running process in the local memory area of ​​the target NUMA node according to a preset memory pre-allocation algorithm, and a first allocated memory size of the allocated memory page is obtained; when the first allocated memory size is smaller than the required memory size, a neighboring NUMA node closest to the target NUMA node is determined based on a system resource topology map, and memory is allocated to the currently running process in the local memory area of ​​the neighboring NUMA node according to the memory pre-allocation algorithm, and a second allocated memory size of the allocated memory page is obtained; when the sum of the first allocated memory size and the second allocated memory size is not less than the required memory size, the pre-allocation of memory required for the currently running process is completed.

[0098] Among them, the memory pre-allocation algorithm can be a currently commonly used memory pre-allocation algorithm, and this application does not limit the specific algorithm used.

[0099] That is, in this embodiment, when allocating memory for the currently running process, the local memory area of ​​the bound target NUMA node is preferentially selected to pre-allocate memory. If the memory size of the allocated memory page in the local memory area (referred to as the first allocated memory size for ease of description and distinction) is smaller than the required memory size, the NUMA node closest to the target NUMA node (referred to as the adjacent NUMA node) is further determined according to the system resource topology map, and memory is pre-allocated in the local memory area of ​​the adjacent NUMA node, and the size of the allocated memory page (referred to as the second allocated memory size) is obtained, and then the sum of the second allocated memory size and the first allocated memory size is calculated. If the sum is not smaller than the required memory size, the pre-allocation of the memory required by the currently running process is completed, and the allocated memory is marked as accessible only to the currently running process. If the obtained sum is still smaller than the required memory size, the next adjacent NUMA node is obtained according to the system resource topology map, and memory is continued to be pre-allocated for the currently running process in the local memory area of ​​the node, and the sum of all allocated memory is calculated again and compared with the required memory size, and the above process is repeated until the sum of allocated memory is not smaller than the required memory size.

[0100] In summary, in this embodiment, memory is preferentially reserved for the currently running process in the local memory area of ​​the bound NUMA node. If it is insufficient, the local memory of the nearest NUMA node is selected for further allocation. The NUMA node is selected to allocate memory according to the rule from near to far, which can shorten the memory access delay as much as possible.

[0101] In an alternative embodiment of the present application, after determining the target NUMA node with the optimal performance, when binding the execution core of the currently running process to the target NUMA node, the processor core to which the execution core of the currently running process is currently bound (for the convenience of description and distinction, referred to as the target processor core) can be obtained first, and the current NUMA node corresponding to the target processor core can be determined according to the association relationship between each NUMA node and the processor core. For example, the current NUMA node corresponding to the target processor core can be determined according to the pre-stored correspondence table of different NUMA nodes and the corresponding processor cores; for another example, the constructed system resource topology map can be queried, and the current NUMA node corresponding to the target processor core can be determined according to the processor core distribution information of each NUMA node recorded in the system resource topology map. Then, the current NUMA node is compared with the determined target NUMA node. If the two are inconsistent, the execution core of the currently running process is bound to the processor core of the target NUMA node; if the two are consistent, the binding relationship between the currently running process and the current NUMA node is maintained without re-binding. By first determining whether the determined target NUMA node is consistent with the currently bound NUMA node during binding, and only binding the currently running process to the processor core of the target NUMA node when they are inconsistent, unnecessary repeated binding can be avoided, and the impact of switching the bound node on the process running can also be reduced.

[0102] The process scheduling method based on the NUMA architecture provided by the embodiments of the present application can be deployed and implemented as a scheduling system. Figure 4 It is a schematic structural diagram of a scheduling system according to an exemplary embodiment of the present application. As Figure 4 shown, the scheduling system mainly includes the following core modules:

[0103] PCIe device identification module: When the computer system starts up, through a specially designed PCIe device identification mechanism, all PCIe devices connected to the computer system can be quickly and accurately identified, and the physical PCIe port to which each PCIe device is connected can be determined, and the port information is output, providing basic data support for subsequent system resource management;

[0104] NUMA detection module: Deeply detect each NUMA node in the computer system, comprehensively obtain the memory layout of each NUMA node, including memory capacity, memory module distribution, processor core distribution, and topological connection relationship with the PCIe port, and construct a detailed system resource topology map. The quality of the work of this module is directly related to the accuracy and efficiency of system resource scheduling, and it is also an important source of basis for the adaptive scheduling module to make resource allocation decisions;

[0105] Process Analysis Module: When a new process starts and involves PCIe device interaction, this module quickly starts working, comprehensively and deeply analyzes the memory access pattern of the process, takes into account various factors such as the memory access instructions issued during the process operation, data transfer frequency, and data flow direction, accurately determines the main PCIe device interaction object of the process, and at the same time passes the analysis result to the Adaptive Scheduling Module to assist it in making resource allocation decisions;

[0106] Binding Execution Module: As the core execution unit of the entire system, based on the system resource topology map, the results obtained from the Process Analysis Module, and the calculation results of the comprehensive performance scores of each NUMA node, it accurately binds the process execution core to the processor core within the appropriate NUMA node and pre-allocates the memory pages required by the process to the local memory area. This module has a powerful dynamic adjustment function. When the memory access pattern of the process changes, for example, a new process needs to allocate resources or an existing process needs to adjust resources, it can re-determine the main PCIe device interaction object and the target NUMA node according to the Adaptive Scheduling Algorithm, and timely adjust the binding strategy of the process execution core and memory pages to ensure that the system resources are always optimally configured;

[0107] Adaptive Scheduling Module: This module is the intelligent decision-making core of the entire system. According to the process of the Adaptive Scheduling Algorithm, it regularly collects the performance index data of each NUMA node and PCIe device, calculates the comprehensive performance score, makes process allocation and migration decisions based on the score, and dynamically adjusts the weights according to the real-time performance of the system and user feedback. During the entire life cycle of the process execution, it continuously monitors and optimizes the resource allocation in real time according to the actual situation changes to ensure that the system performance is always in the best state.

[0108] The above-mentioned each module has a clear division of labor and works together to jointly achieve the comprehensive management and dynamic scheduling of system resources, ensuring that the system performance is always in the best state.

[0109] Traditional process scheduling mechanisms often fail to accurately match processes with memory resources in a NUMA architecture, resulting in frequent cross-node memory accesses by processes, thereby increasing memory access latency. In this application, during the process of process execution, the NUMA node with the optimal performance is selected according to the comprehensive performance score of the NUMA node, the process execution core is accurately bound to the processor core within the most suitable NUMA node, and memory pages are pre-allocated to the local memory area. This process greatly reduces the number of cross-NUMA node memory accesses, significantly reducing memory access latency. The reduction of memory access latency directly promotes a significant increase in the system data transfer rate. Experiments show that with the solution of this application, in various tasks involving PCIe devices, whether it is data acquisition, image processing, or other similar application scenarios, the task execution time can be effectively shortened. Taking the data acquisition process as an example, since it can quickly interact with the data acquisition card of the PCIe interface, reducing the data waiting time, more data can be acquired per unit time; in the image processing process, the data transfer speed between the GPU and the memory is accelerated, accelerating the image rendering and processing speed, enabling the entire computer system to run more efficiently and smoothly when processing complex tasks, providing a better user experience for users. In addition, the improvement of system performance is also reflected in the ability to handle more concurrent tasks simultaneously, increasing the system throughput and meeting the requirements of multi-task parallel processing.

[0110] In addition, the solution of this application has a powerful dynamic adjustment ability, which can monitor the changes in the memory access pattern during the process execution, the system load condition, and the resource usage status of each NUMA node in real time. Once it is found that the memory access pattern of the process has changed significantly, such as adding a major PCIe device interaction or changing the original main interaction device, the solution of this application can quickly respond, recalculate the resource allocation plan, and timely adjust the process execution core binding and memory page allocation strategy.

[0111] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0112] The embodiments of this application also provide a process scheduling device based on the NUMA architecture. Figure 5 The following is a schematic structural diagram of a process scheduling device based on the NUMA architecture provided by the embodiments of this application. As Figure 5 shown, the process scheduling device 50 based on the NUMA architecture includes: a data acquisition module 510, a first determination module 520, a second determination module 530, and a node binding module 540. Among them,

[0113] A data acquisition module 510, configured to acquire performance metric data corresponding to multiple NUMA nodes respectively during the running of a process;

[0114] A first determination module 520, configured to determine comprehensive performance scores corresponding to multiple NUMA nodes respectively based on the performance metric data;

[0115] A second determination module 530, configured to determine a target NUMA node from multiple NUMA nodes based on the comprehensive performance scores corresponding to the multiple NUMA nodes respectively;

[0116] A node binding module 540, configured to bind the execution cores of the currently running process to the processor cores of the target NUMA node, and pre-allocate memory pages required by the currently running process in the local memory area of the target NUMA node.

[0117] Optionally, the NUMA architecture-based process scheduling device 50 further includes:

[0118] A device identification module, configured to identify connected external devices and acquire port information of the external devices;

[0119] A node identification module, configured to acquire memory layout information of multiple NUMA nodes and topological connection relationships between the multiple NUMA nodes and ports of external devices;

[0120] A construction module, configured to construct a system resource topology map based on the memory layout information and topological connection relationships of multiple NUMA nodes.

[0121] Optionally, the data acquisition module 510 is further configured to:

[0122] Traverse the system resource topology map to determine the currently traversed node and a first external device having a topological connection relationship with the currently traversed node;

[0123] Acquire metric data of a first performance metric corresponding to the currently traversed node, and acquire metric data of a second performance metric corresponding to the first external device;

[0124] Upon completion of traversing the system resource topology map, obtain performance metric data corresponding to multiple NUMA nodes respectively.

[0125] Optionally, the first determination module 520 is further configured to:

[0126] Determine a first weight corresponding to the first performance metric and a second weight corresponding to the second performance metric based on the task type of the task executed by the currently running process;

[0127] Normalize the metric data of the first performance metric and the metric data of the second performance metric respectively to obtain the first normalized metric data and the second normalized metric data;

[0128] Based on the first normalized metric data and the second normalized metric data on the same NUMA node, perform weighted summation using the first weight and the second weight to obtain the comprehensive performance scores corresponding to multiple NUMA nodes respectively.

[0129] Optionally, the process scheduling device 50 based on the NUMA architecture further includes:

[0130] A detection module, configured to detect whether a new process involves interaction with an external device when the new process starts;

[0131] A process analysis module, configured to perform process analysis on the new process to obtain the memory access parameters corresponding to the new process and the second external device that interacts with the new process when it is determined that the new process involves interaction with an external device;

[0132] A preliminary binding module, configured to perform preliminary binding on the execution core of the new process based on the memory access parameters, the second external device, and the system resource topology map.

[0133] Optionally, the memory access parameters include the required memory size; the node binding module 540 is further configured to:

[0134] Allocate memory for the currently running process in the local memory area of the target NUMA node according to a preset memory pre-allocation algorithm, and obtain the first allocated memory size of the allocated memory page;

[0135] When the first allocated memory size is less than the required memory size, determine the nearest neighboring NUMA node to the target NUMA node based on the system resource topology map;

[0136] Allocate memory for the currently running process in the local memory area of the neighboring NUMA node according to the memory pre-allocation algorithm, and obtain the second allocated memory size of the allocated memory page;

[0137] When the sum of the first allocated memory size and the second allocated memory size is not less than the required memory size, complete the pre-allocation of the memory required by the currently running process.

[0138] Optionally, the node binding module 540 is further configured to:

[0139] Obtain the target processor core currently bound to the execution core of the currently running process;

[0140] Determine the current NUMA node corresponding to the target processor core;

[0141] When the current NUMA node is inconsistent with the target NUMA node, bind the execution core of the currently running process to the processor core of the target NUMA node.

[0142] For the description of the features in the corresponding embodiments of the process scheduling device based on the NUMA architecture, reference can be made to the relevant descriptions in the corresponding embodiments of the process scheduling method based on the NUMA architecture, which will not be elaborated here one by one.

[0143] An embodiment of the present application further provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above embodiments of the process scheduling method based on the NUMA architecture.

[0144] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above embodiments of the process scheduling method based on the NUMA architecture when running.

[0145] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs, and other various media that can store computer programs.

[0146] An embodiment of the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the process scheduling method based on the NUMA architecture.

[0147] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the process scheduling method based on the NUMA architecture.

[0148] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0149] The above has introduced in detail a process scheduling method based on the NUMA architecture provided by this application. Specific examples are applied in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A process scheduling method based on NUMA architecture, characterized in that: include: During the process running, obtain the performance indicator data corresponding to multiple NUMA nodes respectively; Based on the performance indicator data, determine the comprehensive performance scores corresponding to the multiple NUMA nodes respectively; Determine a target NUMA node from the multiple NUMA nodes based on the comprehensive performance scores respectively corresponding to the multiple NUMA nodes; Bind the execution core of the currently running process to the processor core of the target NUMA node, and pre-allocate memory pages required by the currently running process in the local memory area of ​​the target NUMA node.

2. The process scheduling method based on NUMA architecture according to claim 1, characterized in that: The method further comprises: Identify the connected external device and obtain the port information of the external device; Acquire memory layout information of the multiple NUMA nodes, and topological connection relationships between the multiple NUMA nodes and ports of the external device; A system resource topology map is constructed based on the memory layout information of the multiple NUMA nodes and the topological connection relationship.

3. The process scheduling method based on NUMA architecture according to claim 2, characterized in that: The obtaining of performance indicator data corresponding to the plurality of NUMA nodes respectively includes: Traversing the system resource topology map, determining a current traversal node and a first external device having a topological connection relationship with the current traversal node; Obtaining indicator data of a first performance indicator corresponding to the currently traversed node, and obtaining indicator data of a second performance indicator corresponding to the first external device; After traversing the system resource topology map, performance indicator data corresponding to each of the multiple NUMA nodes are obtained.

4. The process scheduling method based on NUMA architecture according to claim 3, characterized in that: The determining, based on the performance indicator data, the comprehensive performance scores corresponding to the multiple NUMA nodes respectively includes: Determining, based on a task type of the task executed by the currently running process, a first weight corresponding to the first performance indicator and a second weight corresponding to the second performance indicator; Normalizing the indicator data of the first performance indicator and the indicator data of the second performance indicator respectively to obtain first normalized indicator data and second normalized indicator data; Based on the first normalized indicator data and the second normalized indicator data of the same NUMA node, weighted sum is performed using the first weight and the second weight to obtain comprehensive performance scores corresponding to the multiple NUMA nodes respectively.

5. The process scheduling method based on NUMA architecture according to any one of claims 2 to 4, characterized in that: The method further comprises: When a new process is started, detecting whether the new process involves interaction with the external device; In the case where it is determined that the new process involves interaction with the external device, performing process analysis on the new process to obtain memory access parameters corresponding to the new process and a second external device interacting with the new process; Based on the memory access parameter, the second external device and the system resource topology map, a preliminary binding is performed on the execution core of the new process.

6. The process scheduling method based on NUMA architecture according to claim 5, characterized in that: The memory access parameter includes the required memory size; the pre-allocation of the memory pages required by the currently running process in the local memory area of ​​the target NUMA node includes: Allocate memory for the currently running process in a local memory area of ​​the target NUMA node according to a preset memory pre-allocation algorithm, and obtain a first allocated memory size of the allocated memory page; In a case where the first allocated memory size is smaller than the required memory size, determining, based on the system resource topology map, an adjacent NUMA node that is closest to the target NUMA node; Allocate memory for the currently running process in a local memory area of ​​the adjacent NUMA node according to the memory pre-allocation algorithm, and obtain a second allocated memory size of the allocated memory page; When the sum of the first allocated memory size and the second allocated memory size is not less than the required memory size, pre-allocation of the memory required for the currently running process is completed.

7. The process scheduling method based on NUMA architecture according to any one of claims 1 to 4, characterized in that: The step of binding the execution core of the currently running process to the processor core of the target NUMA node includes: Obtain the target processor core currently bound to the execution core of the currently running process; Determine the current NUMA node corresponding to the target processor core; When the current NUMA node is inconsistent with the target NUMA node, the execution core of the currently running process is bound to the processor core of the target NUMA node.

8. A process scheduling device based on NUMA architecture, characterized in that: include: A data acquisition module is used to obtain performance indicator data corresponding to multiple NUMA nodes during the process running; A first determination module, configured to determine, based on the performance indicator data, comprehensive performance scores corresponding to the plurality of NUMA nodes respectively; A second determination module is used to determine a target NUMA node from the multiple NUMA nodes based on the comprehensive performance scores respectively corresponding to the multiple NUMA nodes; The node binding module is used to bind the execution core of the currently running process to the processor core of the target NUMA node, and pre-allocate the memory pages required by the currently running process in the local memory area of ​​the target NUMA node.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the process scheduling method based on the NUMA architecture as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the process scheduling method based on the NUMA architecture as claimed in any one of claims 1 to 7.

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