75091 results about "Computer hardware" patented technology

A computer system implements a unified framework integrating an adaptive elastic funnel (AEF) with a convergent intelligence fabric (CIF) for multi-agent AI collaboration. The system provides a universal multi-modal key-value subsystem for sharing partial computations, implements hybrid placement strategies for dynamic memory management, and incorporates quantum-resistant secure enclaves. The architecture integrates hardware acceleration through GPU-FPGA hybrid caching and neuromorphic processors, applies adaptive energy and thermal management across hardware generations, and implements autonomous flash resource orchestration with multi-dimensional wear management. The system orchestrates tensor workflows using hierarchical scheduling, enables cross-agent collaboration with privacy preservation, and supports continuous learning without catastrophic forgetting. This integration delivers unprecedented computational efficiency and security in high-dimensional decision-making environments while supporting incremental adoption through modular interfaces.

A wearable device configured to monitor physiological parameters of a wearer can include: a physiological parameter measurement sensor configured to monitor a plurality of physiological parameters; a hardware processor; a display in communication with the processor; and a band configured to secure the physiological parameter measurement sensor on a wrist of the wearer. In some implementations, the hardware processor is configured to: obtain a first plurality of signals from the physiological parameter measurement sensor when the band is secured on the wrist at a first tightness; determine a signal quality responsive to the first plurality of signals; and output an indication on the display to adjust tightness of the band with respect to the wrist from the first tightness to a second tightness based on the determined signal quality.

Embodiments of the invention provide a pen-stylus that comprises a first antenna having a hemispherical shape at a proximal end of the pen-stylus where the pen-stylus engages with a display of a tablet device. The pen-stylus also includes a second antenna, wherein the first antenna and the second antenna communicate with the tablet device to enable a pen-stylus user to draw on the display of the tablet device. The pen-stylus additionally includes an insulating material between the first antenna and the second antenna that prevents interference between the first antenna and the second antenna. In some embodiments, the first antenna and the insulating material reside in a marker tip attached to the pen-stylus, the marker tip transmits axial forces received by engagement of the pen-stylus with the display on the tablet to a force sensor. The pen-stylus further includes a force sensor that converts axial forces received from the marker tip into an electrical signal and transmits the electrical signal to the tablet by at least one of the first antenna and the second antenna.

A new transaction barrier synchronization primitive enables executing threads and asynchronous transactions to synchronize across parallel processors. The asynchronous transactions may include transactions resulting from, for example, hardware data movement units such as direct memory units, etc. A hardware synchronization circuit may provide for the synchronization primitive to be stored in a cache memory so that barrier operations may be accelerated by the circuit. A new wait mechanism reduces software overhead associated with waiting on a barrier.

The invention belongs to the technical field of computers, and provides a video display and storage method and system based on a wayland protocol and a storage medium in order to solve the problems that an existing wayland video system is high in rendering delay, high in CPU load, low in storage efficiency and poor in cross-platform compatibility. Video frames are directly written into an Overlay layer through DRM-KMS and mixed by bypassing a synthesizer, meanwhile, CPU memory amplitude overhead is eliminated through zero copy transmission, an ISP-GPU-VPU direct transmission assembly line is constructed, full-link DMA-BUF direct transmission is achieved, and delay is greatly reduced; iSP preprocessing, GPU shader scaling and VPU coding are all executed by special hardware, so that the load is reduced, and the multi-path processing capability is improved; vPU dynamic code rate compression is utilized, segmented storage is carried out according to events / time, metadata is synchronized to a database, redundant storage is avoided, and space is saved.

The embodiment of the invention discloses an in-memory computing circuit based on a magnetic cache, and the circuit comprises at least one magnetic cache unit, at least one in-memory computing unit, and a timer. The magnetic cache unit in the at least one magnetic cache unit is used for caching data output by the corresponding in-memory computing unit as to-be-processed data within the corresponding data retention time; the timer is used for respectively setting data retention time for the at least one magnetic cache unit; and the in-memory computing unit in the at least one in-memory computing unit is used for extracting the data to be processed from the corresponding magnetic cache unit for calculation and outputting the computed data to other magnetic cache units. According to the embodiment of the invention, the invention achieves the flexible adjustment of the data retention time of the magnetic cache unit in various in-memory calculation scenes, and achieves the provision of a high-capacity cache for the data needed by in-memory computing under the lower power consumption.

An agricultural image analysis system comprising at least one vision sensor configured to view a seed trench; a storage module in communication with the at least one vision sensor; a processor in communication with the storage module, the processor executing at least one machine learning module for analysis of images from the at least one vision sensor. The system including at least one laser configured to emit a beam at an open seed trench and at least one vision sensor configured to view the open seed trench and the beam. The system including a thermal camera mounted to a row unit.

Neural network architectures for feature extraction from visual input. In at least one embodiment, a neural network architecture for a vision backbone includes hybrid stages with at least one state space model (SSM)-based block preceding at least one transformer block. In at least one embodiment, an SSM-based block includes parallel branches, one including an SSM and one without an SSM, and a concatenation layer for concatenating the output of each branch. In at least one embodiment, the SSM performs a parallel selective scan operation to efficiently map tokens of an input sequence to tokens of an output sequence via GPU acceleration.

The invention relates to the field of intelligent interaction, and discloses an intelligent hardware dynamic interaction system based on voice semantic fusion and multi-modal perception, which comprises the following steps of: constructing a context model of continuous operation by collecting continuous voice instructions, gesture actions and expression information of a user; semantic analysis and feature fusion are carried out on currently collected voice, gesture and expression features, meanwhile, credibility indexes of all modes are calculated through a weighting or deep learning model, weighting correction is carried out on a fusion result, a real-time feedback algorithm is adopted for weight adjustment for continuous optimization, the next operation intention of a user is predicted through deep learning, and the user experience is improved. And in combination with historical interaction data, online feedback and prediction errors, context management, modal weight and intention prediction strategies are adaptively optimized, and the updated strategies are used for next-round context acquisition and multi-modal fusion. The method has the advantage of improving the recognition accuracy in the continuous interaction scene.

An electronic device that has a user-interface locked state and a user-interface unlocked state communicates with an external device using wireless communication to facilitate unlocking of the electronic device.

According to the novel transponder and the Beidou short message-combined realization function and application method and system, multiple functions are realized by utilizing multiple combinations of ground and vehicle-mounted transponder system equipment, the novel transponder can be applied to multiple scenes, the equipment types can be simplified, the construction cost can be reduced, and the maintenance workload can be reduced; beidou positioning and short message functions, positioning and communication of wireless communication and the like are used as supplements to perfect train operation control and other functions, and the transportation efficiency and safety are improved.

The invention provides an image data secure transmission method, computing equipment and a computer storage medium. The method is applied to a data sender, and comprises the following steps: executing a first image encryption algorithm, and performing encryption processing on a transmission image through an image key to obtain a ciphertext of the transmission image; executing a first key encryption algorithm, and performing encryption processing on the image key through an encryption key to obtain an encrypted image key; the first image encryption algorithm is different from the first key encryption algorithm; and forming a transmission data packet from the ciphertext, the encryption key and the encrypted image key, and transmitting the transmission data packet to a data receiver. Therefore, a proper image encryption algorithm is adopted for the image data, and a proper key encryption algorithm is adopted for the image key, so that real-time performance and security are both considered in the image data encryption process through a mixed encryption mode.

The application discloses a pixel driving circuit, a display panel and a display device. The pixel driving circuit comprises a first pixel driving unit, a second pixel driving unit and a third pixel driving unit. The first pixel driving unit comprises a first driving transistor and a first light emitting element. The first driving transistor has a first threshold value adjustment gate and receives a first adjustment signal. The second pixel driving unit comprises a second driving transistor and a second light emitting element. The second driving transistor has a second threshold value adjustment gate and receives a second adjustment signal. The light emitting colors of the first light emitting element and the second light emitting element are different from each other. When the first light emitting element and the second light emitting element display a target gray scale, the voltage values of the first adjustment signal and the second adjustment signal are different.

A system for data collection related to a fluid conveyance environment includes a data acquisition circuit comprising inputs and outputs; input sensors to provide sensor data values, coupled to a component in the fluid conveyance environment; and a processor comprising the data acquisition circuit. The processor is configured to determine a data storage profile; responsive to the data storage profile, configure the data acquisition circuit to selectively couple at least one of the inputs to at least one of the outputs; interpret the at least one of the sensor data values; store at least a portion of the at least one of the sensor data values in response to the data storage profile; analyze a set of the sensor data values and determine a data quality parameter; and adjust at least one of the data storage profile and a data collection routine in response to the data quality parameter.

The invention relates to the technical field of display screens, in particular to a liquid crystal display screen backlight local dimming method and device, a terminal and a medium. Comprising the steps of obtaining brightness and color distribution data of a display picture; calculating a target brightness value of each backlight block through the dimming algorithm module based on a dynamic partition control strategy and a preset brightness mapping model; wherein the dynamic partition control strategy is used for dividing adjacent backlight blocks into dynamic dimming groups according to brightness characteristics of a picture area on the premise that the number of the backlight blocks is not increased; the backlight control device drives an LED backlight block of the backlight module according to the target brightness value; and monitoring a display effect in real time, and adjusting parameters of the brightness mapping model based on feedback. According to the invention, the problems of cost increase and related derivation caused by increase of the number of partitions in the prior art can be solved.

Systems, methods, apparatuses, and computer program products for enhancing dynamic CORESET adaptation with limited or no control channel overhead. One method may include receiving, by a UE, a plurality of PDCCH CORESET configurations associated with at least one SS; determining, by the UE, at least one of the PDCCH CORESET configurations is associated with a symbol or slot format from a corresponding set of symbols; and performing, by the UE, PDCCH monitoring on an active control resource set configuration associated with the set of determined slots or symbols.

A method applied to a network device includes: sending configuration information to a terminal device, where the configuration information indicates M sounding reference signal (SRS) resource sets, the M SRS resource sets include X first SRS resource sets and Y second SRS resource sets, the X first SRS resource sets include at least one first SRS resource, the Y second SRS resource sets include at least one second SRS resource, a time domain resource corresponding to the at least one first SRS resource is a subband full duplex (SBFD) type time unit, and a time domain resource corresponding to the at least one second SRS resource is a non-SBFD type time unit; and receiving an SRS from the terminal device based on the configuration information.

The invention relates to an LED intelligent lighting control method and device based on the Internet of Things, and the method can collect the environment perception data of a plurality of intelligent LED lamps, and carries out the dimming calculation, and obtains an initial dimming parameter. Performing instruction construction on the initial dimming parameters in combination with historical energy consumption records and environmental perception data of the intelligent LED lamp, and generating a target dimming instruction; controlling the intelligent LED lamp through an edge gateway based on the target dimming instruction, and obtaining lamp response data; and continuously judging the intelligent LED lamp according to the lamp response data to obtain fault judgment information, and triggering an operation and maintenance control instruction. According to the invention, the operation state of the intelligent LED lamp can be accurately judged, potential faults can be found in time, and automatic operation and maintenance can be triggered. According to the invention, the operation state of the intelligent LED lamp can be accurately judged, potential faults can be found in time, and automatic operation and maintenance can be triggered.

The invention provides a storage type time-depth logging method, and relates to the technical field of logging control, and the method comprises the steps: obtaining an encoder, tension and acceleration data, and drawing an encoding curve, a tension curve and an acceleration curve. And receiving an effective movement time interval of single complete drilling rod operation intercepted by the user according to the curve characteristics. And for the original coding curve section of each interval, the total variation and the total duration of the coding value are kept unchanged, and the coding value and the time point are matched again according to the layered scale relationship between the encoder data and the actual displacement of the hook, so that a corrected target coding curve is obtained. And all the target coding curves are converted into time-depth curves according to the depth interval corresponding to each drill rod, and a time-depth file is generated through splicing according to the operation sequence of the drill rod operation event interval. According to the scheme, the technical problem of how to improve the precision of storage type time-depth logging depth measurement and the reliability of the whole system is solved.

The invention belongs to the technical field of signal synchronization, and discloses a multi-camera anti-shake time sequence synchronization control system and method based on an FPGA. The method comprises the following steps: taking an FPGA as a core, generating an FSYNC signal as a camera exposure reference, and obtaining a delay value through a timestamp and differential measurement; acquiring I MU data and obtaining a global motion vector through a gradient descent algorithm; analyzing by combining the two to obtain phase deviation and feeding back the phase deviation to the FPGA, and adjusting the FSYNC signal by combining the global motion vector by the FPGA according to the phase deviation; according to the method, nanosecond timestamp recording is realized through a homologous clock reference and hardware-level signal binding mechanism, and the limitation of dependence on static time difference compensation in the prior art is broken through in combination with global motion vector analysis and dynamic phase offset adjustment.

A display substrate and a display device, relating to the technical field of display. The display substrate comprises a plurality of display units. Each display unit comprises a plurality of pixel units arranged in an array along a row direction and / or a column direction. The plurality of pixel units comprise a sharing pixel unit and a first anti-peeping pixel unit. The viewing angle of the first anti-peeping pixel unit in a first direction is smaller than the viewing angle of the sharing pixel unit in the first direction, and the viewing angle of the first anti-peeping pixel unit in the first direction is smaller than the viewing angle of the first anti-peeping pixel unit in a second direction, the first direction and the second direction intersecting each other.

The invention discloses an air-sea cross-domain network slice configuration and response method based on a CTC8180 chip, and belongs to the technical field of air-sea cross-domain communication and network slicing, and the method comprises the steps: S1, configuring and parallelly accessing NETCONF and CLI paths, and converting a configuration instruction into a CTC8180 chip call instruction; s2, creating a resource pool, a logic port, a binding interface and a VRF strategy based on a FlexE technology; s3, finishing forwarding and mapping configuration of a slicing strategy by combining SRv6 path programming, service level mapping and gport identification slice identification; s4, performance monitoring, data acquisition and fault detection are carried out through three protocols; s5, closed-loop control is formed through resource dynamic adjustment, path switching, strategy linkage and the like; and S6, multi-chip compatibility and stable adaptive deployment are realized through the steps of integrating S1 to S5. The invention provides a specific implementation method for constructing logic network slicing capability on high-performance forwarding hardware for air-sea cross-domain specific requirements, and provides reliable communication guarantee for high-dynamic heterogeneous services.

This invention relates to a modular sensing, communication, and analytics platform. The platform includes a modular device network having a communication module, a main module, and at least one modular device, where the communication module, the main module, and the at least one modular device use acoustic signals, visual signals, light signals, and / or radio frequency to establish a communication link between the communication module, the main module, and the at least one modular device.

The application provides a signal transmission method, a video encoder and a computer readable storage medium. A computer-implemented signal transmission method performed by an encoder comprises the following steps: a processor transmits a bitstream comprising weight information for a prediction coding unit (CU) to a video decoder, the weight information indicating that if weighted prediction is enabled for a bi-prediction mode of the CU, weighted averaging for the bi-prediction mode is disabled, and the weight information indicating that if weighted prediction is enabled for at least one of a luma component and a chroma component of a reference picture of the CU, weighted averaging for the bi-prediction mode is disabled, wherein the bitstream comprises a flag indicating whether weighted prediction is enabled for at least one of the luma component and the chroma component of the reference picture, and the flag comprises a flag luma_weight_lx_flag[i] transmitted for an i-th reference picture in a reference picture list Lx, wherein x is 0 or 1.

A mixed-signal in-memory computing sub-cell requires only 9 transistors for 1-bit multiplication. In one aspect, a computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and common transistors. As a result, the average number of transistors in each sub-cell is close to 6. Also proposed is a MAC array for performing MAC operations, which includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. Also proposed is an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain.

A video encoding method, a video decoding method and apparatus, and a storage medium are provided. The decoding method includes that: angular accuracy corresponding to the intra prediction mode candidate list is determined, the first angular accuracy is used for indicating a search range of an angular prediction mode in the intra-frame prediction mode candidate list; the intra prediction mode candidate list is constructed on the basis of the first angular accuracy; and the prediction for the current block is performed on the basis of the constructed intra prediction mode candidate list.

The invention discloses a home page multi-component parallel prefetching and rendering first screen acceleration method and device and a storage medium, and the method comprises the following steps: constructing a global dependency relationship model based on the metadata and dependency relationship of each component of a home page, and calculating the priority for each component according to a predefined priority evaluation strategy, generating a component scheduling sequence constrained by the priority and the dependency relationship; controlling a concurrency control strategy of the component; preferentially rendering a visual placeholder structure, and smoothly replacing the real content to a user visible area through a progressive rendering replacement strategy; when the variable quantity of the component data exceeds a preset threshold value, triggering an increment updating strategy based on the difference content; generating a cache identifier according to component granularity, reading and writing data in a multi-level cache structure based on the cache identifier, and ensuring data consistency by adopting a background asynchronous verification strategy; and collecting performance indexes in a page rendering process, and adjusting the priority evaluation strategy, the concurrency control strategy and the increment updating strategy according to the performance indexes.

The invention provides a chip verification method and device, equipment, a medium and a program product, and the method comprises the steps: receiving a first operation instruction of a to-be-verified module and a second operation instruction of a reference model in parallel, the reference model being a function model used for simulating the expected behavior of the to-be-verified module; searching a first instruction record matched with the first operation instruction from a request queue of the reference model, and searching a second instruction record matched with the second operation instruction from a request queue of the to-be-verified module; and determining a verification result of the to-be-verified module according to a comparison result of the first operation instruction and the first instruction record and / or a comparison result of the second operation instruction and the second instruction record. According to the invention, a structured and reusable universal chip verification method is realized, so that a tedious customized scoreboard design is replaced, and the efficiency and accuracy of verification work are greatly improved.

A system can include a memory device comprising a plurality of dynamic capacity devices and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations including receiving a host command to freeze first data associated with a first tag, wherein the first tag is associated with a first memory section of a plurality of dynamic capacity devices, and wherein the first memory section is allocated to a first host system to store the first data. The operations further include responsive to receiving the host command to freeze, making the first data inaccessible to the first host system; and responsive to determining that the host command indicates to free the first memory section, storing the first data in a second memory device, wherein the second memory device is not included in the plurality of dynamic capacity devices.