13 results about "Conventional memory" patented technology

A memory controller and an MCU chip are disclosed. The memory controller adds a second memory controller to a conventional memory controller architecture and is coupled to second NVM having first and second backup banks. In order to perform an OTA upgrade, one of the first and second backup banks of the second NVM is used as a default backup bank for supporting execution of an ongoing program of the system, and the other as an OTA upgrade backup bank for supporting OTA upgrade control.

The invention relates to the technical field of circuit design, and discloses a multi-intensity emotion enhancement memristor bionic circuit which comprises a language enhancement module, a fear emotion module, an happy emotion module, an emotion enhancement module and a high-intensity memory module. Parallel light / heavy processing paths are arranged in the fear and happiness emotion module, and emotion stimulation of different intensities is distinguished. The light emotion signals are processed and then fed back to the language enhancement module, and formation of conventional memory is adjusted; and the severe emotion signal is transmitted to an independent high-intensity memory module for special storage. The language enhancement module integrally processes language signals and feedback adjustment signals of all the modules. The high-intensity memory module forms stable memory for severe emotional events through a parallel memristor structure. Through grading processing and signal interaction, the differential influence of emotions with different intensities and the interaction of multiple emotions can be simulated, a grading memory mechanism is established, and the fidelity and authenticity of circuit simulation biological memory are improved.

A memory testing device uses a master control unit to concurrently operate multiple, intelligent, slave control units (SCUs). SCUs have one or more processing unit(s) (i.e. Finite State Machines, micro controllers, processors) capable of processing one or more firmware with or without operating system (i.e. bare-metal, embedded OS, RTOS (real time operating system)) to perform a series of task defined by firmware(s) for testing volatile and / or non-volatile memory devices connected into one or more DUT devices plus SCU has capability of having operating system and install and run host applications locally within each SCU units to mimic host applications environments along with performing regular memory testing.

The invention provides a memory method for supporting hybrid retrieval and dynamic update in large law model application. The memory method comprises the following steps: acquiring a question input by a user; performing mixed retrieval according to questions of the user, and obtaining related memory information through secondary retrieval of law article fields and mixed retrieval of a conventional memory library; performing memory evolution according to the current user input and the mixed retrieval result, judging whether the user input is matched with the retrieval result, updating the existing memory or creating new memory according to the matching result, and updating the link relationship between the memories; and filtering and screening the mixed retrieval result to obtain a final memory retrieval result. According to the method, the memory system can be adaptively optimized according to the actual use condition, the method has the advantages of combining multiple retrieval methods, the dual requirements of the legal field for accuracy and semantic understanding can be met at the same time, multiple application scenes such as legal consultation, case analysis and legal education are effectively supported, and then the efficiency and accuracy of legal services are improved.

A memory controller and an MCU chip are provided by the present application. The memory controller adds a second memory controller to conventional memory controller architecture and is coupled to second NVM storing a backup of content of first NVM in the memory controller. With this arrangement, one more memory access path is established, which takes full advantage of the fast reading characteristics of the first NVM, and once a system bus identifies an error in content read from the first NVM or a problematic address, the second memory controller can automatically read exactly corresponding backup content from the second NVM and provide it on the system bus, or use it to accurately correct the error in the first NVM. This ensures correctness of content that a central processing unit (CPU) or other master on the system bus reads, without interrupting execution of the system's program.

This application discloses a method, apparatus, computer device, and storage medium for saving and restoring a processor. The method includes: monitoring the occurrence of trigger events associated with saving or restoring the processor core during its operation; upon detecting a trigger event, determining a selected register from the processor core's register file based on the configuration state of the trigger control domain and the specific identifier of the register identifier domain, and determining whether to perform a save operation or a restore operation; and transmitting the data of the selected register to a storage unit in the block memory at high speed through multiple parallel data channels connecting the register file and the block memory to complete the save operation, or transmitting the data stored in the storage unit to the selected register at high speed to complete the restore operation, wherein the high-speed transmission rate is higher than the normal transmission rate of the processor core accessing the block memory through conventional memory access instructions.

To solve the problem that a refresh frequency is high and power consumption is large in a conventional memory display type liquid crystal display device.SOLUTION: The pixel includes a first memory circuit and a second memory circuit, a first transistor connected to the first memory circuit, and a second transistor connected to the second memory circuit, and the pixel electrode is connected to the first power supply line via the first transistor and connected to the second power supply line via the second transistor. The method includes: SELECTED DRAWING: Figure 1

The invention provides a limited-time programmable nonvolatile memory and a preparation and operation method thereof, a P-type pocket region and an N-type drain doping region are arranged in a drain region, and the P-type pocket region and the N-type drain doping region are provided with a longitudinal interface below a side wall laminated structure, so that electronic writing is realized when an N-type memory transistor is positively conducted; when the N-type storage transistor is not turned on in the forward direction, hole writing is achieved. Compared with a traditional memory, the limited-time programmable nonvolatile memory has the advantages that charges in the limited-time programmable nonvolatile memory are stored in the silicon nitride layer in the side wall laminated structure, and an additional MOS (Metal Oxide Semiconductor) capacitor is not needed, so that the area of a memory unit can be effectively reduced; meanwhile, the limited-time programmable nonvolatile memory provided by the embodiment of the invention only has the process of writing 0 and 1 to the memory unit, and does not need an erasing action, so that the circuit design is effectively simplified.

The present disclosure relates to devices and methods for single-ended global and local input / output architectures. Conventional memories can use local input / output (LIO) and global input / output (GIO) lines that are paired and carry complementary signals. The present disclosure includes single-ended LIO and GIO architectures in which, as part of an access operation, a single LIO couples a single GIO between a read / write amplifier and a bit line. This can reduce the footprint of the memory device.

To solve the problem that power consumption required for refreshing is large in a conventional memory display type liquid crystal display device.SOLUTION: A display device includes a pixel including a first memory circuit, a second memory circuit, and a display circuit that includes a liquid crystal capacitor and is connected to the first memory circuit and the second memory circuit, a first power supply line and a second power supply line that are connected to the display circuit, a refresh circuit that reads memory data stored in the first memory circuit and writes back the memory data to the first memory circuit in accordance with a result of the reading, and a control circuit that controls the refresh circuit.SELECTED DRAWING: Figure 1

The embodiment of the invention provides a memory and a control method, the memory at least comprises a redundant memory array and a conventional memory array, and word lines in the redundant memory array are used for repairing word lines in the conventional memory array. The capacitance of the minimum storage unit in the redundant storage array is greater than that of the minimum storage unit in the conventional storage array; and the sense amplifier is used for amplifying bit line voltages in the redundant storage array and the conventional storage array.

Semiconductor memory devices and methods of operating semiconductor memory devices are disclosed. One method includes replacing an address of a first regular memory cell in a first column of regular memory cells of a first memory block with a target address, the target address being an address of a second regular memory cell in a second column of regular memory cells of the first memory block; and reassigning an address of the second regular memory cell in the second column of regular memory cells of the first memory block to an address of a first redundant memory cell of a first redundant block of the at least one redundant block.

The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input / output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.