73 results about "Extended memory" patented technology

The invention discloses a memory access method based on a memory expansion controller, a memory expansion card and equipment, and relates to the technical field of computers, and the method comprises the following steps: carrying out twice address mapping on a target access address in a memory read-write instruction through the pre-created memory expansion controller, the target access address is mapped to a hard disk storage space from a processor memory physical address space, whether the mapped access address is hit in a preset cache space or not is judged, and if the mapped access address is hit, read-write operation is directly conducted on corresponding target data in the preset cache space; and if not, performing read-write operation on the corresponding target data in the solid state disk. By means of the mode, the solid state disk can be used as the extended memory of the host, the memory extension cost is remarkably reduced, ultra-large-capacity memory extension can be achieved, accordingly, the memory access cost is reduced, and meanwhile the access speed is taken into account in the mode of presetting the cache space.

The invention discloses a three-level cache replacement method based on dirty page perception and adaptive capacity, and belongs to the technical field of computer memory cache management. The method comprises the following steps of: constructing a short-time-efficiency queue, a medium-time-efficiency queue and a global queue in a CXL extended memory equipment side cache; executing object insertion, migration and metadata updating according to the hit condition of the access request in each queue; when the cache space is insufficient, the access count, the dirty page mark and the dirty page revival mark are combined to execute eviction judgment; and calculating a return visit ratio based on global queue identifier insertion times and return visit times, and dynamically adjusting short-time-efficiency and medium-time-efficiency queue capacities. According to the method, the problems of high dirty page write-back cost and inflexible cache space distribution in the CXL extended memory are solved, and the redundant write-back overhead is reduced, the utilization efficiency of the cache space is improved and the access delay is reduced through collaborative optimization of the access characteristics, the dirty page state and the elimination return visit behavior.

The invention discloses a cross-platform multi-environment compatibility test method and device, electronic equipment and a storage medium. Constructing an attribute set according to the acquired business terminal attribute information, and constructing a mirror image and an environment description vector according to the attribute set; obtaining a use case execution log, associating a log field with an environment description vector to generate a basic triple, and expanding the basic triple to obtain an expanded memory unit; maintaining the storage state of the extended memory unit by adopting a time decay strategy, calculating a load weighted average value for each pair of test targets and environment indexes, and generating a dependency matrix; splitting the dependency relationship matrix to construct a three-layer heterogeneous memory graph, analyzing the three-layer heterogeneous memory graph, and determining a test dependency graph; and performing fuzzy evaluation and analytic hierarchy process on the environment nodes in the test dependency graph, determining the comprehensive risk of each environment node, and executing mainstream priority and long-tail understanding test tasks according to the comprehensive risk of each environment node.

The invention provides a memory error processing method, system and device, a storage medium and a program product, an operating system kernel comprises a hardware error source driver, a first driver and a second driver, and the second driver is used for processing a memory error processing task of an extended memory area. The first driver is used for processing a memory error processing task of a standard memory area and distributing a memory error processing task of an extended memory area to a second driver, and the method comprises the following steps: acquiring a memory error processing task of a target page distributed by a hardware error source driver; memory errors exist in the target page; and if the target page is the memory page of the extended memory area, calling the second driver to carry out error processing on the target page. According to the method, the reliability of error processing is improved.

The present application discloses a heterogeneous acceleration method for a database, an electronic device, a storage medium, and a program product, and relates to the field of data processing technology. The method is applied to a host side, which is connected to an extended memory via an accelerator. An index of a variable-length column field of a data table is constructed before a query. During a query, the variable-length column field and page meta-information are sent to the accelerator. The accelerator calculates the position and length of the column field in a storage page based on the meta-information and the variable-length column field index, and performs filtering calculations to generate calculation results for characterizing that filtering conditions are met, as well as memory saturation of selected columns and filtered columns in the storage page. The host side obtains the selected column field based on the filtering calculation results to improve filtering calculation performance and reduce CPU computing consumption for searching column fields. At the same time, page migration is performed based on memory saturation to further reduce access latency and improve filtering calculation performance.

The application discloses a processor, a data processing method, a chip and an electronic device, and belongs to the electronic technical field. The processor comprises an exchange module, a processing module and a local memory, the processing module and the exchange module are connected with the local memory and an extended memory, and the processing module is connected with the exchange module. Wherein, the processing module sends an exchange instruction to the exchange module when determining that the first data meeting the condition is located in the extended memory. The exchange module reads the first data from the extended memory and the second data from the local memory based on the exchange instruction, writes the first data into the local memory, and writes the second data into the extended memory. By exchanging the data that may be accessed from the extended memory to the local memory, the subsequent processing module can read data from the local memory, and the data reading delay is reduced.

Disclosed are a network interface card device, a network data transmission method, apparatus, and system, a device, and a medium, which are applied to the field of Internet technologies. The network interface card device includes a programmable device, which constructs a network platform based on a memory expansion method, and the network platform includes a network interface, a target memory, and a network component. The programmable device is connected to a network through the network interface, and exchanges data with a host by the memory expansion method. The host, based on the memory expansion method, configures the target memory of the programmable device as an extended memory of the host, for storing received target network data belonging to a network interface card processed packet type, or to-be-sent network data of the host.

The application provides a data scheduling method and device and electronic equipment. The embodiment automatically identifies a cold unit memory (referred to as a cold unit memory) in a first memory, whose access frequency per unit time is less than a first set threshold, and a hot unit memory (referred to as a hot unit memory) in a second memory, whose access frequency per unit time is greater than or equal to a second set threshold, automatically schedules data in the hot unit memory in the second memory to move to an idle unit memory in the first memory, and automatically schedules data in the cold unit memory in the first memory to move to an idle unit memory in the second memory, so that data with high access frequency is stored in the local first memory of the system, and data with low access frequency is stored in the second memory which is expanded, the advantages of local memory high-speed access and memory capacity expansion are maximized, and the data access efficiency is improved.

A parallel processor assigns data for use by one or more tasks to a shared memory or memories associated with a plurality of compute units. A scheduler or other controller within or otherwise associated with the parallel processor assigns threads or groups of threads, which utilize the assigned data, to compute units as appropriate. Compute units utilize two sets of instructions, one specifying upper bits and one specifying lower bits of a memory address, to specify memory addresses that are larger than a number of bits an individual instruction can specify in a memory address field. Mode setting commands determine when and how lower bits in a memory address field of an instruction will be combined with upper bits in a previous instruction, e.g., through concatenation.

The application provides a virtual machine linear memory expansion method and device, a storage medium and electronic equipment, and applies to the technical field of virtual machine memory. When an application is started, a software development kit is initialized, and a preset capacity of a memory linear allocator corresponding to a system version is obtained. A memory mapping file of the SDK is parsed, a memory region range is determined, and a local method is called to find a memory starting address. According to the address, the memory linear allocator is expanded, and a target buffer is allocated by using a memory mapping function. The application effectively solves the problem of virtual machine method number limitation by improving the memory capacity, ensures stable operation in all scenarios including startup and runtime dynamic loading, and reduces the situation of crash and installation failure.

Described herein are systems and methods for dynamically configuring memory using Optical Circuit Switching (OCS). As electrical processing units such as accelerators are limited by their available bandwidth, providing disaggregated memory can help expand memory and enable better processing performance. Providing OCS devices to dynamically reconfigure processor-to-processor and processor-to-memory connections enables flexible reconfiguration of the disaggregated memory and improve performance of the system.

The present disclosure discloses a data read and write method. The method is applied to a logical management controller, where the logical management controller communicates with a central processing unit (CPU) and at least two expanded memory controllers respectively based on a compute express link (CXL) protocol, the logical management controller includes a request parsing module, an address decoding module, a request decomposition module and a request allocation module, and the method includes: parsing a received data read and write request for target data to obtain a local command; performing command parsing on the local command to determine location information for reading and writing data; generating a plurality of data read and write sub-requests based on the location information; sending the plurality of data read and write sub-requests to target expanded memory controllers; and controlling the target expanded memory controllers to perform data read and write operations in parallel according to the plurality of data read and write sub-requests.

The application discloses a data processing system, method, device, medium and program product in the computer technical field. In the application, the acceleration device provides a remote direct data access module and an extension memory module of a host computer, so that the host computer creates multiple queue pairs in the extension memory module to solve the problem of insufficient queue pairs and expand the number of queue pairs; when the host computer confirms that the queue pairs corresponding to a target port for communication with a third-party device are insufficient, the target queue pairs are selected from the extension memory module and configured to the target port, so that the on-demand dynamic allocation of the queue pairs is realized; after the target queue pairs are updated, the host computer synchronizes the target queue pairs to the acceleration device by using a cache consistency protocol, so that the acceleration device uses the remote direct data access module and the target queue pairs to improve the data transmission efficiency between the host computer and the acceleration device.

The application provides a memory expansion method, a memory access method, a device and a system, which are applied to a primary switch, and the method comprises the following steps: receiving an expansion memory resource application request initiated by a computing node server, establishing a routing connection between the computing node server and a secondary switch; and forwarding the application request and routing information of the computing node server and the secondary switch to the secondary switch, so that the secondary switch establishes a memory mapping table of a computing node server IP and a corresponding expansion memory address according to the routing information and the computing node server IP carried by the application request. Through the two-level switches, the application can construct expansion memory resources shared by multiple computing node servers, improve the overall memory utilization of the system, and through the two-level switches, the application can request the expansion memory resources, so that the memory capacity of the computing node server can be expanded in real time, and the total amount of available memory resources of a single computing node can be enhanced.

Provided in the present application are a data scheduling method and apparatus, and an electronic device. In the embodiment, a unit memory (which is referred to as a cold unit memory), an access frequency per unit time of which is lower than a first set threshold, in a first memory and a unit memory (which is referred to as a hot memory unit), an access frequency per unit time of which is greater than or equal to a second set threshold, in a second memory are automatically identified, data in the hot unit memory in the second memory is automatically scheduled and migrated into an idle unit memory in the first memory, and data in the cold unit memory in the first memory is automatically scheduled and migrated into an idle unit memory in the second memory, such that data with high access frequency is stored in the local first memory of a system, and data with low access frequency is stored in the extended second memory, so as to maximize the advantages of high-speed access performed by means of a local memory and memory capacity expansion performed by means of an extended memory, thereby improving the data access efficiency.

Disclosed are a device and method with memory request processing using an extension of a memory address space. An electronic device includes a host processor configured to generate a memory request and a memory address that is mapped to a target memory mode that is any one of available memory modes and is mapped to a physical memory address to which the memory request is to be applied, a memory controller configured to generate the physical memory address and a command according to the target memory mode mapped to the memory address based on the memory request and the memory address received from the host processor, and a memory configured to execute, at the physical memory address, the command received from the memory controller.

The invention provides an external expansion memory dynamic management method and device, which can realize dynamic distribution and release of an external expansion memory by creating a memory management control block structural body and a linear linked list node structural body and establishing a memory management linked list. According to the method, a continuous free memory area meeting conditions is searched by adopting a first-time adaptation algorithm, and a high-address large-block free memory is reserved for subsequent use, so that application failure caused by insufficient memory is effectively prevented. According to the method, the technical problems of low management efficiency and serious fragmentation of the external expansion memory in the embedded system are solved, and the utilization rate of system resources is remarkably improved.

Provided in the embodiments of the present disclosure are a device operation method, system and apparatus, and a non-volatile readable storage medium and an electronic device. The method comprises: during the process of executing a power-on self-test on a server, acquiring a plurality of peripheral devices connected to the server, and memories of expanded memories of respective ones of the plurality of peripheral devices; determining whether the memories of the expanded memories of the plurality of peripheral devices meet a preset memory condition of a basic input output system in the server; when the memories of the expanded memories do not meet the preset memory condition, determining a plurality of candidate device sequences according to the plurality of peripheral devices; and determining a target device sequence from among the plurality of candidate device sequences, and loading and running the multiple target devices in the target device sequence.

The invention discloses an available memory real-time display method and device driven by a task event of a mobile terminal. According to the method, an event monitoring mechanism is established, and when it is detected that a user enters a recent task interface, closes a task or executes all cleaning operations, memory information collection is triggered; available memory and total memory data in the system memory information file are read in a background thread, and re-collection is carried out through preset delay after task operation, so that the accurate memory release amount is calculated; a calculation result is converted into a readable format through a formatting module, and an interface is updated in real time through a main thread. Through the design of combining event triggering and delayed secondary acquisition, the accuracy of release amount calculation and the system response speed can be improved while high-frequency polling is avoided. The method further supports virtual extended memory display, a filtering and threshold judgment mechanism, a deep cleaning module and a low memory prompt function, and can effectively improve transparency of system resource management and user interaction experience.

The application discloses a storage cluster, a system, a data processing method, equipment, a medium and a product, relates to the technical field of data storage, and solves the technical problem of poor high availability of a storage system caused by poor scalability of the number of controllers and the number of data copies by controlling the number of devices in the controller unit, the switch unit and the extension memory unit, respectively, and respectively corresponding redundant devices existing in each unit, a plurality of switches of the switch unit being connected to a plurality of extension memories of the extension memory unit, and each of the plurality of extension memories storing copy data of a plurality of controllers. The memory cache data of the controller is decoupled from the DRAM memory inside the controller to the external extension memory, the deployment operation is simplified, and the data access processing can be completed in the case that N-1 controllers fail simultaneously, M-1 switches fail simultaneously and / or P-1 extension memories corresponding to the data copies fail, thereby improving the technical effect of the high availability of the storage system.

Various embodiments described herein provide for expanding the size of memory cells of a memory device, such as the size of codewords of a page of the memory device, where the memory device can be included in a memory system. In particular, some embodiments implement expanding (e.g., increasing) the size of the memory cells (e.g., codewords) to store more data, such as more host data (e.g., user data) and protection data (e.g., parity data) within the memory cells, while using memory cell storage slots (e.g., codeword storage slots in a page) that are smaller than the expanded memory cells.

A system including a scalable memory pool. In some embodiments, the system includes: a first memory node, including a first memory; a second memory node, including a second memory; and a memory node switching fabric connected to the first memory node and the second memory node, the memory node switching fabric being configured to provide access, via the first memory node: with a first latency, to the first memory, and with a second latency, greater than the first latency, to the second memory.

The application discloses a memory management method and a replaceable cache strategy and system under a DDR-CXL heterogeneous memory structure, and aims at the problem that an existing memory database lacks a NUMA-aware memory management and an efficient cache mechanism under a heterogeneous memory environment.The application constructs a hierarchical memory structure composed of a DDR memory and a CXL extended memory, wherein the DDR memory serves as a cache layer, and the CXL memory serves as a large-capacity data storage layer.On this basis, a NUMA-aware memory allocator is designed to realize unified abstract management of different memory nodes and support dynamic migration of data between the DDR and the CXL memory.Meanwhile, a pluggable cache strategy management mechanism is proposed to support multiple cache replacement strategies through a unified interface, and a cache admission strategy based on access statistics is introduced to reduce invalid data migration and improve cache utilization.The application realizes decoupling of memory management and cache strategy through a plug-in framework, and can improve system performance while enhancing flexibility and scalability of the system.

The application discloses a VPX mainboard based on D3000 and a bridge and a data processing method. The mainboard comprises a processor, a bridge connected with the processor through a first PCIe bus and used for interface expansion, a memory module connected with the processor and used for storing instructions and data, a network interface module connected with the processor through a second PCIe bus and used for realizing network communication, a display interface module connected with the bridge and used for outputting a video signal, and a serial interface module connected with the processor and the bridge respectively and used for realizing serial communication. The VPX mainboard of the application realizes the localization of hardware and software by adopting the domestic core processor, the bridge and other components and combining with the optimized interface circuit design, solves the problems of insufficient performance and low interface integration of the existing part-localized VPX mainboard, and has the advantages of high flexibility, high firmness and high cost performance.

The application discloses a kind of dynamic adjustment method and terminal of task memory, monitor and calculate the average task processing rate of each subtask of pending task under historical condition;When the real-time execution data of pending task is obtained, if pending task has not been set fast task label, whether the current pending task exceeds the average task processing rate of preset proportion subtask, if yes, set fast task label for pending task;If pending task has been set fast task label, then increase the memory threshold of pending task according to preset proportion. In this way, the real-time processing rate of a task can be compared with the historical average processing rate to identify tasks that can improve processing speed by expanding memory, and dynamically configure appropriate memory threshold for the task. The dynamic adjustment of task memory can improve task processing speed and efficiency.

A memory controller and method for controlling the allocation of blocks of a fungible memory for each of a plurality of packet forwarding engines (PFEs) to ingress instructions and / or egress instructions.

The invention provides a storage and calculation integrated chip architecture, a storage mode configuration method and a medium, the storage and calculation integrated chip architecture comprises a storage system and an AI calculation system, the AI calculation system is connected with a host CPU through a JEDEC standard interface, and when a use scene is a main memory scene, the AI calculation system is connected with the host CPU through a JEDEC standard interface. The storage space of the storage system is configured as a first main memory area or an extended memory area of a host CPU; when the use scene is a storage and calculation integrated scene, the storage space of the storage system is configured to be a second main memory area, a shared memory area and an NPU memory area. Core interfaces such as PCIe / CXL are saved, the problem that multiple devices (such as a network and an accelerator card) contend for interface bandwidth is avoided, resource contention is reduced, the system integration degree is improved, the chip area is saved, the design complexity is reduced, and flexible memory architecture configuration is supported.

Apparatus and methods for extending functionality of memory controllers using a loopback mode for testing are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit configured to receive a memory write request that is directed to and received by a memory controller. The memory access intercept circuit transmits proxy write data to the memory controller, and intercepts write data directed to the memory controller for the memory write request. The memory access intercept circuit stores the write data in a write data buffer, and, upon intercepting the proxy write data from the memory controller directed to a physical (PHY) interface circuit, retrieves the write data from the write data buffer and transmits the write data to the PHY interface circuit. The memory access intercept circuit subsequently receives, from the PHY interface circuit, loopback data, and stores the loopback data in a read data buffer.

The present application discloses a distributed computing method, apparatus, device and system and a readable storage medium. The distributed computing method is applied to a controller of a distributed accelerator cluster and includes: acquiring information of accelerators in the distributed accelerator cluster; establishing an accelerator direct-connection pair according to the information of the accelerators; and in response to receiving a service task, dividing the service task into computing tasks and distributing the computing tasks to an idle target accelerator having an application computing logic matching the type of the corresponding computing tasks, wherein the accelerator direct-connection pair includes two accelerators that are directly connected to each other, and at least one of the two accelerators is a first accelerator that supports a computer express link protocol and has an extended memory, and / or the two accelerators have the same application computing logic.

The invention discloses a host end-device end collaborative management method for guaranteeing data security of a heterogeneous memory system, which belongs to the field of computer storage, adopts a layered integrity verification mechanism, unloads verification and updating operations of an integrity tree to a device end for local execution, and additionally performs transmission integrity protection on a counter, so that the security of the data security of the heterogeneous memory system is guaranteed. The system overhead caused by frequent access of the host side to the nodes of the extended memory integrity tree is avoided; unloading the security computing task related to migration to the equipment side, and proposing an unloading scheduling mechanism with priority counter integrity to dynamically coordinate security computing resources of the equipment side; for a page which cannot complete instant re-encryption, according to a page migration direction, migration re-encryption state tables are respectively introduced into a host end and an equipment end for state management, and residual tasks are completed in a subsequent data access process in combination with a delay re-encryption strategy and a re-encryption strategy based on a state table water level line. The safety calculation burden in the page migration process is reduced, and the overall performance of the system is improved.