46 results about "Extended memory" patented technology

The invention discloses a three-level cache replacement method based on dirty page perception and adaptive capacity, and belongs to the technical field of computer memory cache management. The method comprises the following steps of: constructing a short-time-efficiency queue, a medium-time-efficiency queue and a global queue in a CXL extended memory equipment side cache; executing object insertion, migration and metadata updating according to the hit condition of the access request in each queue; when the cache space is insufficient, the access count, the dirty page mark and the dirty page revival mark are combined to execute eviction judgment; and calculating a return visit ratio based on global queue identifier insertion times and return visit times, and dynamically adjusting short-time-efficiency and medium-time-efficiency queue capacities. According to the method, the problems of high dirty page write-back cost and inflexible cache space distribution in the CXL extended memory are solved, and the redundant write-back overhead is reduced, the utilization efficiency of the cache space is improved and the access delay is reduced through collaborative optimization of the access characteristics, the dirty page state and the elimination return visit behavior.

The application discloses a processor, a data processing method, a chip and an electronic device, and belongs to the electronic technical field. The processor comprises an exchange module, a processing module and a local memory, the processing module and the exchange module are connected with the local memory and an extended memory, and the processing module is connected with the exchange module. Wherein, the processing module sends an exchange instruction to the exchange module when determining that the first data meeting the condition is located in the extended memory. The exchange module reads the first data from the extended memory and the second data from the local memory based on the exchange instruction, writes the first data into the local memory, and writes the second data into the extended memory. By exchanging the data that may be accessed from the extended memory to the local memory, the subsequent processing module can read data from the local memory, and the data reading delay is reduced.

Disclosed are a network interface card device, a network data transmission method, apparatus, and system, a device, and a medium, which are applied to the field of Internet technologies. The network interface card device includes a programmable device, which constructs a network platform based on a memory expansion method, and the network platform includes a network interface, a target memory, and a network component. The programmable device is connected to a network through the network interface, and exchanges data with a host by the memory expansion method. The host, based on the memory expansion method, configures the target memory of the programmable device as an extended memory of the host, for storing received target network data belonging to a network interface card processed packet type, or to-be-sent network data of the host.

The application provides a data scheduling method and device and electronic equipment. The embodiment automatically identifies a cold unit memory (referred to as a cold unit memory) in a first memory, whose access frequency per unit time is less than a first set threshold, and a hot unit memory (referred to as a hot unit memory) in a second memory, whose access frequency per unit time is greater than or equal to a second set threshold, automatically schedules data in the hot unit memory in the second memory to move to an idle unit memory in the first memory, and automatically schedules data in the cold unit memory in the first memory to move to an idle unit memory in the second memory, so that data with high access frequency is stored in the local first memory of the system, and data with low access frequency is stored in the second memory which is expanded, the advantages of local memory high-speed access and memory capacity expansion are maximized, and the data access efficiency is improved.

A parallel processor assigns data for use by one or more tasks to a shared memory or memories associated with a plurality of compute units. A scheduler or other controller within or otherwise associated with the parallel processor assigns threads or groups of threads, which utilize the assigned data, to compute units as appropriate. Compute units utilize two sets of instructions, one specifying upper bits and one specifying lower bits of a memory address, to specify memory addresses that are larger than a number of bits an individual instruction can specify in a memory address field. Mode setting commands determine when and how lower bits in a memory address field of an instruction will be combined with upper bits in a previous instruction, e.g., through concatenation.

The application provides a virtual machine linear memory expansion method and device, a storage medium and electronic equipment, and applies to the technical field of virtual machine memory. When an application is started, a software development kit is initialized, and a preset capacity of a memory linear allocator corresponding to a system version is obtained. A memory mapping file of the SDK is parsed, a memory region range is determined, and a local method is called to find a memory starting address. According to the address, the memory linear allocator is expanded, and a target buffer is allocated by using a memory mapping function. The application effectively solves the problem of virtual machine method number limitation by improving the memory capacity, ensures stable operation in all scenarios including startup and runtime dynamic loading, and reduces the situation of crash and installation failure.

Described herein are systems and methods for dynamically configuring memory using Optical Circuit Switching (OCS). As electrical processing units such as accelerators are limited by their available bandwidth, providing disaggregated memory can help expand memory and enable better processing performance. Providing OCS devices to dynamically reconfigure processor-to-processor and processor-to-memory connections enables flexible reconfiguration of the disaggregated memory and improve performance of the system.

The present disclosure discloses a data read and write method. The method is applied to a logical management controller, where the logical management controller communicates with a central processing unit (CPU) and at least two expanded memory controllers respectively based on a compute express link (CXL) protocol, the logical management controller includes a request parsing module, an address decoding module, a request decomposition module and a request allocation module, and the method includes: parsing a received data read and write request for target data to obtain a local command; performing command parsing on the local command to determine location information for reading and writing data; generating a plurality of data read and write sub-requests based on the location information; sending the plurality of data read and write sub-requests to target expanded memory controllers; and controlling the target expanded memory controllers to perform data read and write operations in parallel according to the plurality of data read and write sub-requests.

Provided in the present application are a data scheduling method and apparatus, and an electronic device. In the embodiment, a unit memory (which is referred to as a cold unit memory), an access frequency per unit time of which is lower than a first set threshold, in a first memory and a unit memory (which is referred to as a hot memory unit), an access frequency per unit time of which is greater than or equal to a second set threshold, in a second memory are automatically identified, data in the hot unit memory in the second memory is automatically scheduled and migrated into an idle unit memory in the first memory, and data in the cold unit memory in the first memory is automatically scheduled and migrated into an idle unit memory in the second memory, such that data with high access frequency is stored in the local first memory of a system, and data with low access frequency is stored in the extended second memory, so as to maximize the advantages of high-speed access performed by means of a local memory and memory capacity expansion performed by means of an extended memory, thereby improving the data access efficiency.

Disclosed are a device and method with memory request processing using an extension of a memory address space. An electronic device includes a host processor configured to generate a memory request and a memory address that is mapped to a target memory mode that is any one of available memory modes and is mapped to a physical memory address to which the memory request is to be applied, a memory controller configured to generate the physical memory address and a command according to the target memory mode mapped to the memory address based on the memory request and the memory address received from the host processor, and a memory configured to execute, at the physical memory address, the command received from the memory controller.

Provided in the embodiments of the present disclosure are a device operation method, system and apparatus, and a non-volatile readable storage medium and an electronic device. The method comprises: during the process of executing a power-on self-test on a server, acquiring a plurality of peripheral devices connected to the server, and memories of expanded memories of respective ones of the plurality of peripheral devices; determining whether the memories of the expanded memories of the plurality of peripheral devices meet a preset memory condition of a basic input output system in the server; when the memories of the expanded memories do not meet the preset memory condition, determining a plurality of candidate device sequences according to the plurality of peripheral devices; and determining a target device sequence from among the plurality of candidate device sequences, and loading and running the multiple target devices in the target device sequence.

The invention discloses an available memory real-time display method and device driven by a task event of a mobile terminal. According to the method, an event monitoring mechanism is established, and when it is detected that a user enters a recent task interface, closes a task or executes all cleaning operations, memory information collection is triggered; available memory and total memory data in the system memory information file are read in a background thread, and re-collection is carried out through preset delay after task operation, so that the accurate memory release amount is calculated; a calculation result is converted into a readable format through a formatting module, and an interface is updated in real time through a main thread. Through the design of combining event triggering and delayed secondary acquisition, the accuracy of release amount calculation and the system response speed can be improved while high-frequency polling is avoided. The method further supports virtual extended memory display, a filtering and threshold judgment mechanism, a deep cleaning module and a low memory prompt function, and can effectively improve transparency of system resource management and user interaction experience.

Various embodiments described herein provide for expanding the size of memory cells of a memory device, such as the size of codewords of a page of the memory device, where the memory device can be included in a memory system. In particular, some embodiments implement expanding (e.g., increasing) the size of the memory cells (e.g., codewords) to store more data, such as more host data (e.g., user data) and protection data (e.g., parity data) within the memory cells, while using memory cell storage slots (e.g., codeword storage slots in a page) that are smaller than the expanded memory cells.

The application discloses a memory management method and a replaceable cache strategy and system under a DDR-CXL heterogeneous memory structure, and aims at the problem that an existing memory database lacks a NUMA-aware memory management and an efficient cache mechanism under a heterogeneous memory environment.The application constructs a hierarchical memory structure composed of a DDR memory and a CXL extended memory, wherein the DDR memory serves as a cache layer, and the CXL memory serves as a large-capacity data storage layer.On this basis, a NUMA-aware memory allocator is designed to realize unified abstract management of different memory nodes and support dynamic migration of data between the DDR and the CXL memory.Meanwhile, a pluggable cache strategy management mechanism is proposed to support multiple cache replacement strategies through a unified interface, and a cache admission strategy based on access statistics is introduced to reduce invalid data migration and improve cache utilization.The application realizes decoupling of memory management and cache strategy through a plug-in framework, and can improve system performance while enhancing flexibility and scalability of the system.

The application discloses a VPX mainboard based on D3000 and a bridge and a data processing method. The mainboard comprises a processor, a bridge connected with the processor through a first PCIe bus and used for interface expansion, a memory module connected with the processor and used for storing instructions and data, a network interface module connected with the processor through a second PCIe bus and used for realizing network communication, a display interface module connected with the bridge and used for outputting a video signal, and a serial interface module connected with the processor and the bridge respectively and used for realizing serial communication. The VPX mainboard of the application realizes the localization of hardware and software by adopting the domestic core processor, the bridge and other components and combining with the optimized interface circuit design, solves the problems of insufficient performance and low interface integration of the existing part-localized VPX mainboard, and has the advantages of high flexibility, high firmness and high cost performance.

The application discloses a kind of dynamic adjustment method and terminal of task memory, monitor and calculate the average task processing rate of each subtask of pending task under historical condition;When the real-time execution data of pending task is obtained, if pending task has not been set fast task label, whether the current pending task exceeds the average task processing rate of preset proportion subtask, if yes, set fast task label for pending task;If pending task has been set fast task label, then increase the memory threshold of pending task according to preset proportion. In this way, the real-time processing rate of a task can be compared with the historical average processing rate to identify tasks that can improve processing speed by expanding memory, and dynamically configure appropriate memory threshold for the task. The dynamic adjustment of task memory can improve task processing speed and efficiency.

A memory controller and method for controlling the allocation of blocks of a fungible memory for each of a plurality of packet forwarding engines (PFEs) to ingress instructions and / or egress instructions.

The present application discloses a distributed computing method, apparatus, device and system and a readable storage medium. The distributed computing method is applied to a controller of a distributed accelerator cluster and includes: acquiring information of accelerators in the distributed accelerator cluster; establishing an accelerator direct-connection pair according to the information of the accelerators; and in response to receiving a service task, dividing the service task into computing tasks and distributing the computing tasks to an idle target accelerator having an application computing logic matching the type of the corresponding computing tasks, wherein the accelerator direct-connection pair includes two accelerators that are directly connected to each other, and at least one of the two accelerators is a first accelerator that supports a computer express link protocol and has an extended memory, and / or the two accelerators have the same application computing logic.

This application discloses an external vehicle instrument system, a vehicle instrument, and its function extender, applicable to the field of vehicle manufacturing technology. The system includes an instrument body and a function extender with a matching shape. The instrument body includes a controller, a main communication module, an electrical connection module, and a loop detection module. The function extender includes a secondary communication module and an extended memory. The instrument body and the function extender are connected via the electrical connection module, and the loop detection module detects whether the function extender is connected to the instrument body. The instrument body communicates with the secondary communication module of the function extender via the main communication module and reads data from the extended memory. The controller executes corresponding data update tasks based on the acquired information to be extended and / or data to be upgraded, effectively improving the practicality of the external vehicle instrument and meeting users' customization needs.

The invention discloses a memory-driven spacecraft inertia estimation method and system and a related product, and belongs to the technical field of spacecraft control. The method provided by the invention comprises the following steps: establishing an attitude motion model containing inertia uncertainty based on a spacecraft attitude motion dynamics relationship; tracking error variables are introduced and reconstructed into an attitude tracking error system motion model; processing the signal by using a fixed parameter linear filtering operator and eliminating a differential term to obtain a first algebraic equation; transforming a regression signal based on the equation to construct an expansion algebraic model; and a historical information accumulation mechanism is introduced in combination with the extended memory regression amount to complete inertia parameter online estimation. According to the method, extra continuous external excitation is not needed, estimation can be achieved only by utilizing the normal attitude motion inherent signals of the spacecraft, meanwhile, the requirement for high-precision speed differential information is avoided, high precision and online real-time performance of inertia estimation are taken into consideration, on-orbit inertia dynamic changes can be effectively tracked, and attitude control stability is guaranteed.

The application relates to a server and an electronic device, and relates to the technical field of computers. The application is used to solve the problem that the internal memory module of a server is difficult to expand, thereby limiting the processing performance of the server. The server comprises a mainboard, a CPU and an expansion memory module. The mainboard comprises an expansion memory connector. The CPU is located on the mainboard and is coupled with the expansion memory connector. The expansion memory module is located on one side of the mainboard and is arranged in a spaced mode with the mainboard; the expansion memory module is coupled with the expansion memory connector.

The application provides a memory error processing method, system, device, storage medium and program product. An operating system kernel comprises a hardware error source driver, a first driver and a second driver. The second driver is used for processing a memory error processing task of an extended memory area. The first driver is used for processing a memory error processing task of a standard memory area. The first driver is used for distributing the memory error processing task of the extended memory area to the second driver. The method comprises the following steps: obtaining a memory error processing task of a target page distributed by the hardware error source driver; the target page has a memory error; if the target page is a memory page of the extended memory area, calling the second driver to perform error processing on the target page. The method improves the reliability of error processing.

The application discloses a three-level cache replacement method based on dirty page awareness and adaptive capacity, and belongs to the technical field of computer memory cache management. The method comprises the following steps: constructing short-time queues, medium-time queues and global queues on the side of a CXL extended memory device cache; performing object insertion, migration and metadata update according to the hit condition of each queue; when the cache space is insufficient, performing eviction determination in combination with access count, dirty page flag and dirty page revival flag; calculating the revisit ratio based on the global queue identification insertion frequency and revisit frequency, and dynamically adjusting the short-time queue capacity and the medium-time queue capacity. The application solves the problems of high dirty page write-back cost and inflexible cache space allocation in the CXL extended memory, optimizes the access characteristics, dirty page state and elimination revisit behavior in cooperation, reduces the redundant write-back overhead, improves the cache space utilization efficiency and reduces the access time delay.

The invention discloses a hard disk data read-write method, a product, equipment and a medium, and relates to the technical field of computers, and the hard disk data read-write method comprises the following steps: reading and analyzing a read data command generated by a host from a submission queue of a solid state disk to obtain read command data; reading a flash translation layer mapping table from a first cache partition of the random access memory to determine a physical block address corresponding to a logic block initial address in the read command data from the mapping table; and reading target data corresponding to the physical block address from the flash memory according to the data length in the read command data, and writing the target data into a second cache partition of the memory. According to the method, the programmable logic device board card is used as an extended memory of the host, the board card has two partitions, one partition is used for storing the flash translation layer mapping table, and the other partition is used for storing the data to be read and written, so that the dependence of the solid state disk on the memory of the host can be reduced, and the data reading and writing efficiency is improved.

The application relates to the computer technical field and discloses a memory system, a control method and a server, the system comprising: a CPU and an FPGA acceleration card, the CPU and the FPGA acceleration card both supporting a CXL protocol; the CPU and the FPGA acceleration card being connected through a PCIe interface supporting the CXL protocol; the CPU being configured with a plurality of local memory strips through a memory strip slot; the FPGA acceleration card being configured with a plurality of extended memory strips through a memory connection component or a memory connector; and the FPGA acceleration card being used for receiving memory data sent by the CPU, and performing logical calculation on the memory data according to the attribute characteristics of the memory data based on the extended memory strips to obtain target memory data. The system provided by the above scheme realizes expansion of the memory capacity of the server by additionally arranging the FPGA acceleration card, reduces the difficulty of expansion of the memory capacity of the server, and improves the overall performance and response speed of the server.

This application discloses a resource sharing method, system, and electronic device, relating to the field of cloud platform resource pooling technology. The method includes an interconnected device receiving a request from a target tenant and writing the data and instruction information from the request into a data cache and an instruction cache in an extended memory device, respectively, so that the target device can read the request through the data cache and instruction cache. This application achieves resource sharing with the target device by setting up instruction and data caches in the extended memory device and establishing mapping relationships between the instruction and data caches and each tenant and device, enabling the target tenant to access the instruction and data caches through the interconnected device. This alleviates the overhead caused by relying on additional software protocols in related technologies, achieves consistent access to shared resources, improves access efficiency, and reduces data synchronization complexity.

The present disclosure relates to extended memory architectures. An example device can include a plurality of compute devices. Each of the compute devices can include a processing unit configured to perform an operation on a block of data and a memory array configured as a cache for each respective processing unit. The example device can further include a first communication subsystem coupled to a host and each of the plurality of compute devices. The example device can further include a plurality of second communication subsystems coupled to each of the plurality of compute devices. Each of the plurality of compute devices can be configured to receive a request from the host, send a command to perform at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.

The present application relates to the field of computer systems, and discloses a data processing system, a method, and a computer system. In order to solve the problems of long access path and high access delay for accessing an expanded memory, the data processing system comprises a processing board and a memory expansion board. The processing board is provided with a processing core and a first controller, and the memory expansion board is provided with a storage component and a control component. The present application can enable a processing board to directly access a storage component on a memory expansion board, and memory copying does not need to be performed by means of a server host, thereby reducing the degree of coupling between the processing board and the server host when accessing an expanded memory. While effectively expanding the memory of the processing board, an access path of the processing board for the expanded memory is shortened and access delay is reduced, thereby reducing a communication bottleneck in the training process of a pre-trained model.

A 3D bit cost scalable memory device includes a stack of layers and a via electrode extending vertically through the stack of layers. The layers include a controllable conductivity layer and an electrode layer. The electrode layer has a conductor portion and a separator portion that separates the via electrode from the conductor portion of the electrode layer. At least a storage portion of the controllable conductivity layer is in electrical series between the via electrode and the conductor portion of the electrode layer. The via electrode comprises, for example, tungsten (W). The controllable conductivity layer comprises, for example, an ovonic threshold switch material. The conductor portion of the electrode layer comprises, for example, carbon (C).

The application discloses a data migration method, system and device in the computer technology field. In the application, a target dynamic random storage area is used as an extension of a host dynamic random storage area, and a two-level cache structure is built for the host. In addition, data can be migrated from a storage disk to the target dynamic random storage area and from the target dynamic random storage area to the host dynamic random storage area according to data access heat, so that the migration of data in different storage media can be flexibly and finely realized in the granularity of a storage block size, and the hit rate of the host near-end storage is improved as much as possible. The adaptive adjustment of the migration threshold value can also improve the memory hit rate of the migrated data and the host access performance and read-write efficiency, and reduce the extension memory access delay.