366 results about "Bus interface" patented technology

The invention provides a graphic display agent device based on a PCIE (Peripheral Component Interface Express) bus, which is characterized in that an instruction analysis module receives a graphic drawing instruction containing an operation type and a corresponding coordinate parameter through a PCIE bus interface, and generates first pixel data based on the instruction; meanwhile, the data conversion module receives original image data containing pixel position information and sensor echo information through a radar video interface, analyzes the original image data and converts the original image data into second pixel data consistent with the first pixel data in format, and the format difference of the two types of data is eliminated to meet the superposition condition; a graph superposition processing module generates a primary and secondary clear composite image according to the logic that the first pixel data covers the second pixel data; then, the image output control module receives the synthesized image by using a first buffer area and a second buffer area which alternately work to ensure that a complete image frame is transmitted to a subsequent module; and finally, the video signal generation module converts the complete image frame into an analog video signal conforming to a preset video time sequence and outputs the analog video signal.

The invention discloses an elevator operation safety intelligent monitoring method and system, and relates to the technical field of elevator operation safety monitoring, and the method comprises the steps: collecting elevator multi-source operation data in real time through a bus interface, arranging sensors in a lift car, a shaft and a machine room, synchronously sampling various signals, building an operation state machine by combining position information and a door lock state, dividing the operation process into a plurality of working condition sections and organizing original data according to the working condition sections; calculating a multi-dimensional health index in a working condition section, and dynamically modeling an adaptability threshold by combining real-time characteristics and historical statistical data; and multi-dimensional indexes are compared in real time based on threshold values, and abnormal scores are calculated in a fused mode, so that fault sources are recognized, and intelligent monitoring of elevator operation safety is achieved. According to the method, through multi-source data real-time collection, working condition section division, dynamic threshold modeling and multi-index fusion analysis, refined monitoring of the elevator running state is achieved, the accuracy of anomaly detection and the fault positioning capacity are improved, and the safety and reliability of the elevator are improved.

The invention discloses a CAN bus activity detection and wake-up circuit and method, and belongs to the technical field of CAN bus communication, the CAN bus activity detection and wake-up circuit comprises a CAN bus interface circuit, a signal detection and processing circuit and a controller, the input end of the CAN bus interface circuit is connected with a CAN bus; the signal detecting and processing circuit comprises a voltage comparator, the non-inverting input end and the inverting input end of the voltage comparator respectively receive a CANH signal and a CANL signal which are electrically isolated by the CAN bus interface circuit, and the output end of the voltage comparator is connected to a wake-up pin of the controller; the controller is used for monitoring the level state of the wake-up pin, and when the level of the wake-up pin is in an effective state, the electronic equipment is controlled to be switched from the sleep mode to the normal working mode. By introducing an electrical isolation and voltage difference detection mechanism, the problem of false wake-up caused by common-mode interference or bus noise in the prior art is solved, and reliable wake-up under low power consumption is realized.

The invention relates to the technical field of embedded systems and signal acquisition, in particular to a high-speed AD acquisition system and method based on MCU and FPGA time division multiplexing. A change-over switch is integrated in an FPGA processor, the change-over switch is used for communicating an ADC SPI interface with an SPI interface of an MCU controller in a parameter configuration stage and communicating the ADC SPI interface with main control logic in the FPGA processor in a high-speed acquisition stage, and the FPGA processor is further provided with a high-speed parallel bus interface which is used for being connected with a parallel bus interface of the MCU controller in a data reading stage. And batch transmission of the cached data is realized. Physical path isolation is achieved through the change-over switch in the FPGA processor, it is ensured that the MCU controller is completely separated from the AD control bus in the high-speed collection stage, time sequence interference and bus conflict caused by the AD control bus are fundamentally avoided, and the stability and data integrity of the collection process are guaranteed.

The invention provides a multifunctional channel detection system based on a Zynq chip. The multifunctional channel detection system is characterized in that a system main control module is deployed at an ARM processor end of the Zynq chip; the protocol analysis control module, the fault-tolerant detection excitation module and the bottom hardware adaptation module are deployed at the FPGA programmable logic end of the Zynq chip; the system main control module communicates with each module of the FPGA programmable logic end through an AXI bus; the underlying hardware adaptation module receives the configuration from the system main control module and completes electrical adaptation and dynamic switching of various bus interfaces; the protocol analysis control module receives an instruction from the system main control module, and performs protocol analysis and feature verification on at least one of an SPI bus, an IIC bus and a 1553B bus; the fault-tolerant detection excitation module receives the trigger from the system main control module and injects a controllable fault into the tested bus interface; and the system master control module integrates the verification result and the injection feedback to complete the performance and reliability evaluation of the bus channel.

The application provides a virtual modeling-based flight control ICD protocol simulation verification system and a flight control system, comprising a network topology modeling module, a virtual bus modeling service module, an ICD modeling service module, a processing algorithm modeling service module and an ICD simulation running monitoring module, and each module cooperatively realizes a full-process closed loop from ICD analysis to virtual bus simulation verification. The application completes network construction of the system by simulating the commonly used system network bus in the design stage, and in combination with the data processing algorithm, the business data interaction between the system nodes can be simulated in the system design front end, the ICD design problem is identified, the compatibility verification of the ICD and the hardware bus interface is completed in the design front end, the rework waste caused by the design mismatch problem is reduced, and the reliability and delivery efficiency of the system are improved.

The invention discloses a verification system of an FSMC multi-memory interface based on a UVM, and belongs to the technical field of chip verification. The verification system of the FSMC multi-memory interface based on the UVM comprises a test layer, a simulation instruction definition layer, an AHB bus interface component, an assertion inspection component and an external memory interface component. The problems that in the prior art, a single memory is mainly connected for verification, only a single protocol can be verified, the verification means is limited, and the efficiency and the coverage rate are not high are solved, the transmission type of the AHB is defined in the environment configuration component, therefore, the verification diversity is improved, the verification requirements for verifying different memory interfaces are well met, and the verification efficiency is improved. According to the interface protocol verification method and device, the randomized excitation and self-checking function conforming to the protocol can be generated, the verification comprehensiveness is greatly improved, the pertinence and correctness of the verified module are greatly improved, the verification efficiency is improved, the code cost is reduced, and the accuracy of interface protocol verification is improved.

The embodiment of the invention provides a security control method, a baseboard management controller, a computer program product and a storage medium. A security subsystem and a function subsystem which are isolated from each other by hardware are arranged in the baseboard management controller, so that the defense capability of the security subsystem to hardware attacks can be effectively guaranteed. On the basis, security control firmware is arranged in the security subsystem, and the security subsystem can control the computing device to be safely started by executing the security control firmware; moreover, through a bus interface of the baseboard management controller, an access request which is initiated by each system-on-chip in the computing equipment and aims at the target storage component can be received, and the security subsystem can perform access control on the access request by executing the security management and control firmware. Therefore, the baseboard management controller can be used as a platform trust root in the computing equipment to control the computing equipment to be safely started and protect data stored in the target storage component in the computing equipment, so that the safety of the computing equipment is guaranteed.

A cryptocurrency miner includes a serial bus, compute modules, and a controller. Each compute module includes upstream ports, downstream ports, a pass-through buffer coupling the upstream ports to the downstream ports, and a serial bus interface coupled to the serial bus via the first upstream ports and the first downstream ports. The controller controls operation of the compute modules via commands on the serial bus. The serial bus includes bus segments between respective upstream and downstream ports of the compute modules.

The invention discloses a data transmission method and system for a secure real-time bus (SRB), and the method comprises the steps: enabling a central processing unit to transmit data to be transmitted to a secure real-time bus interface device through a real-time transmission type interface if the data to be transmitted belong to real-time data when the data needs to be transmitted through the secure real-time bus; the secure real-time bus interface device caches the current data to be transmitted to a real-time data queue, and sends the data to be transmitted in the real-time data queue to the secure real-time bus for transmission within the cycle time of the secure real-time bus; and if the to-be-transmitted data belongs to non-real-time data, sending the to-be-transmitted data to the safe real-time bus interface device through the standard Ethernet interface. And the secure real-time bus interface device caches the current data to be transmitted to the non-real-time data queue, and sends the data to be transmitted in the non-real-time data queue to the secure real-time bus for transmission within the non-periodic time of the secure real-time bus.

The invention provides a software online upgrading method of a DSP chip based on a CAN bus interface. The software online upgrading method comprises the steps that an OUT format file generated by compiling a source project is converted into a BIN file; the method comprises the steps that a BIN file is unpacked and subpackaged, generated data packets are sent to an FPGA, DSP software conducts CRC verification on each packet of data forwarded by the FPGA till all the data packets are received, and then the software moves all the data stored in an SDRAM and burns the data into a FLASH; reading data of the FLASH and source data stored in the SDRAM, and comparing the data and the source data one by one; the method comprises the following steps: reading an Entry Point of a Bin file, turning to circularly read an initial address and length of a program segment, moving effective data by a BOOT program according to data distribution in an mxp file, after all the data are read into a memory, calculating the cumulative sum of the read data, turning to an entry address of an APP program or a BACK program, and realizing booting of the program. The method can be used for improving the online upgrading function of the DSP.

1. The name of the design product: three interface protocol converter. 2. The use of the design product: for RJ45 network interface, CAN bus interface, USB interface between the protocol conversion to achieve three kinds of protocol between the two-way data remote intelligent conversion and transmission. 3. The design points of the design product: in shape. 4. The picture or photo that can best show the design points: perspective view.

The invention relates to the field of combined electric appliances, in particular to a double-bus GIS (gas insulated switchgear) extension structure with a reserved interval and a charged withstand voltage test method.The double-bus GIS extension structure with the reserved interval comprises a first bus, a second bus and early-stage equipment arranged on the first bus and the second bus, and the first bus and the second bus are provided with bus interfaces to be extended; the earlier-stage equipment comprises an earlier-stage line I, an earlier-stage line II, a bus coupler, a bus bar I PT, a bus bar II PT, an earlier-stage main transformer I and an earlier-stage main transformer II; the system further comprises extension equipment, and the extension equipment comprises a first extension bus and a second extension bus which are connected with the first bus and the second bus respectively, and an extension line, a reserved interval and an extension main transformer which are arranged on the first extension bus and the second extension bus. Power failure of the whole station is not needed, the consequence that early-stage equipment cannot operate is avoided, the cost is saved, and the flexibility of normal power supply is improved.

The invention provides an airborne 1394 acquisition card and a 1394 bus data acquisition method thereof, relates to the technical field of avionics and data acquisition, and solves the problems that an existing 1394 acquisition card is large in size, poor in environmental adaptability, weak in data processing capacity and the like. In the system, an FPGA module provides a logic control algorithm for acquisition of 1394 bus data, and the logic control algorithm comprises receiving, filtering, pipeline caching, data caching, output control and output caching; in the external interface module, a parallel bus interface establishes parallel bus communication connection between the FPGA module and the main control board card, and the main control board card is configured with a 1394 acquisition card and receives 1394 bus data acquired by the 1394 acquisition card; and the 1394 bus interface establishes bus communication connection between the FPGA module and the airborne equipment, so that the FPGA module receives 1394 bus data input from the airborne equipment. According to the invention, 1394 bus data can be stably and reliably collected and recorded in an airborne environment.

serial communications bus.20 25 28 73 31 24 D ec 2 02 5 A B S T R A C T 2 0 2 5 2 8 7 3 3 1 2 4 D e c 2 0 2 5 s e r i a l c o m m u n i c a t i o n s b u s . 400 Serial communications bus interface 220A 408A Upstream Serial communications receiver bus 412A 404A 410 402 Upstream transmitter Upstream control 414A Clock Upstream enable Lock-out Serial communications Downstream control control circuit bus interface 220B Electronic 404B 414B processor Downstream Downstream enable 408B transmitter 406B 3 / 5 Downstream Serial communications receiver bus 412B FIG. 4 20 25 28 73 31 24 D ec 2 02 5 2 0 2 5 2 8 7 3 3 1 2 4 D e c 2 0 2 5 b u s i n t e r f a c e 4 0 6 A 2 0 2 t r a n s m i t t e r U p s t r e a m c o n t r o l U p s t r e a m e n a b l e Downstream control c o n t r o l c i r c u i t b u s i n t e r f a c e E l e c t r o n i c p r o c e s s o r D o w n s t r e a m D o w n s t r e a m e n a b l e t r a n s m i t t e r D o w n s t r e a m

This application relates to the field of communication technology and discloses a hardware logic-based flow control circuit, chip, and flow control method. The flow control circuit is integrated inside the chip and is used to control multiple controlled modules. The flow control circuit includes: a bus interface for controlling multiple controlled modules or acquiring the status of multiple controlled modules; an instruction sequence execution controller for storing multiple sets of instruction sequences, each set of instruction sequences corresponding to a status index; the instruction sequence execution controller for executing the corresponding instruction sequence according to the input current status index, performing read / write operations or logical operations through the bus interface, and outputting an execution completion signal and a calculation result flag after all instructions in the corresponding instruction sequence have been executed; and a flow control state machine for outputting the current status index to the instruction sequence execution controller and receiving the execution completion signal and the calculation result flag, thereby controlling the flow while ensuring the robustness of the system.

A wireless communication system including an adapter is provided. The adapter is configured to connect with a host through a universal serial bus interface and connect with a handset through a Bluetooth interface to form a Bluetooth connection. After the adapter connects with the host through the universal serial bus interface and connects with the handset through the Bluetooth interface, the adapter is configured to provide a first IP address of the host to the handset to establish a Wi-Fi connection between the host and the handset. The Bluetooth connection is further configured to transmit an encryption key between the host and the handset. The Wi-Fi connection is not configured to transmit the encryption key.

Systems, apparatuses, and methods for saving power on a bus interface are described. A system includes a host, a device, and a repeater interposed between the host and the device. While the host and device are in a low-power state, the repeater monitors a first bus to determine if the device has woken up. When the repeater detects a remote wake-up event initiated by the device, the repeater generates an interrupt which is sent to the host. The host responds to the interrupt by initiating a resume wake-up event procedure that assumes the device is still asleep. In this way, the host is able to stay in the low-power state longer while also using a wake-up procedure that does not require the host to be aware of the existence of the repeater.

The application discloses a cross-clock domain register synchronization method and device. It relates to the technical field of digital integrated circuit design. The method comprises the following steps: when the target clock domain is unavailable, routing the bus read-write request to a shadow register array driven by a system clock, and writing a write transaction log into a log queue when the write transaction is completed, the write transaction log comprising a target address, write data and byte enable; when the target clock domain changes from unavailable to available and the log queue is not empty, setting the handshake signal of the bus interface to invalid, reading the write transaction log from the log queue according to the write sequence, and writing the write data into the target register through a byte mask circuit according to the target address in the write transaction log; when the target clock domain is available and the log queue is empty, routing the bus read-write request to the target register, and setting the handshake signal of the bus interface to valid. The method realizes register access integrity and sequential consistency in the target clock dynamic change scenario.

A data processing apparatus (100) and method. The data processing device (100) comprises a remote direct memory module access (RDMA) module (110), a local agent (HA) module (120) and a memory module (130), the HA module (120) calculates local data and operands in an RDMA message, and writes an obtained calculation result into the memory module (130) through a non-bus interface, so that the situation that the local data is read from the memory module (130) through a bus can be avoided, and the data processing efficiency is improved. And the calculation result is written into the memory module (130) through the bus, so that the processing device (100) can optimize the calculation part in the nodes performing the collective communication, and the communication delay between the nodes can be reduced. Meanwhile, since the processing device (100) can reduce the number of bus accesses, it is possible to contribute to reducing the bandwidth consumption of the bus.

A solid state device (SSD) includes two data storage controllers, each connected to a corresponding set of NAND chips. The SSD includes a Universal Serial Bus (USB)-C socket for receiving a USB-C plug in one of two mating orientations. One lane of the USB-C socket is connected to the first data storage controller. The second lane is connected to the second data storage controller. The two lanes are used for concurrent communications with a host, with lane communication protocols depending upon the mating orientation. In a first mating orientation, the first lane communication protocol may be USB 10 Gbps and the second lane communication protocol may be USB 2.0. In the second mating orientation, the protocols are reversed. The host thereby has concurrent access to both sets of NAND chips. Similar features are described for use with volatile memory devices such as dynamic random access memory (DRAM) devices.

The application relates to an embedded system signal fault-tolerant management system and method, which comprises a bus interface module, a bus state management module and a signal fault-tolerant management module. The bus interface module mainly realizes bus data receiving, bus data sending, bus state transient monitoring and data packet state transient monitoring; the bus state monitoring module realizes bus state judgment, bus state and data packet state monitoring and data packet state synthesis. The signal fault-tolerant management module completes signal self-monitoring synthesis according to the bus and data packet state transient monitoring results output by the bus interface module and other self-monitoring information, completes effective channel selection according to the bus and data packet state monitoring results output by the bus state monitoring module, and completes signal voting, fault monitoring and fault recovery according to the signal self-monitoring synthesis results and the effective channel selection results, and outputs the fault monitoring results and the voting value to subsequent functional modules.

This document describes techniques, methods, and apparatuses for logical memory repair. In some aspects, a memory built-in self-test (MBIST) controller can perform logical memory repair for a memory cluster including a shared bus interface that is coupled to the MBIST controller and configured to provide access to multiple logical memories. The memory cluster includes multiple physical memories that are coupled to the shared bus interface. At least one physical memory is configured to have two or more logical memories overlaid thereon. In example aspects, the physical memory includes arbitration logic coupled to a first address register and a second address register that are respectively configured to store a first faulty memory address and a second faulty memory address. The arbitration logic includes circuitry configured to arbitrate access to at least one spare memory portion responsive to the first faulty memory address conflicting with the second faulty memory address.

The utility model relates to a spaceborne interface expansion device and a satellite, through designing a spaceborne interface expansion circuit structure composed of four kinds of cables and two kinds of resistors, a device for circuit communication expansion of a signal bus hardware interface and connection change of a hardware interface channel is formed, the resistors at different positions are selected through welding and dismounting, and the communication expansion of the signal bus hardware interface is realized. According to the utility model, a bus interface line expansion function is realized, and the bus interface line expansion device is suitable for interface expansion of a dual-channel dual-wire CAN bus, an RS485 communication interface bus and a multi-wire LVDS / RS422 communication interface, and meets and adapts to the requirements of communication bus manufacturing of a whole-satellite cable network of an existing commercial satellite. The device is easy to manufacture, the difficulty in manufacturing the whole satellite cable network and the difficulty in wiring layout design of the cable network are reduced, the cost performance and the reliability are high, and a reliable, firm, convenient, rapid and attractive electrical connection structure is provided for the whole satellite-borne electrical link cable network.

The real-time video acquisition and processing board card of the PXIe specification comprises a connector assembly, a CameraLink Base receiver, a CameraLink Medium receiver, a CameraLink Full receiver, a TTL IO chip, a differential IO chip, an FPGA nonvolatile flash memory, a field programmable logic device, an FPGA high-speed dynamic random access memory, a DSP nonvolatile flash memory, a digital signal processor, a DSP high-speed dynamic random access memory, a PCIe bus interface and a power management module.

The invention relates to the technical field of software design, and provides a log recording method and device suitable for a single-chip microcomputer program. When the single-chip microcomputer system is started, the log system obtains the current storage state from the storage system; when the log recording event is detected, receiving original log data from the corresponding application module from the bus interface; according to the original log data, log information needing to be recorded is obtained; according to the current storage state, storing the log information to the storage system through the bus interface; according to the log recording method and system, the practicability of a log recording function is improved in a mode of constructing a log system and using software abstraction, the cost for realizing the log recording function is reduced, and the problem that various logs in a single chip microcomputer system cannot be efficiently, reliably, accurately and rapidly recorded is solved.

The invention discloses a general test system for electrical system equipment of a carrier rocket, and the system constructs a comprehensive test platform with high compatibility through a system-level scheduling control strategy, a modular combined algorithm collaborative design and an ultra-wide threshold hardware interface signal conditioning technology. Comprising a system logic processing platform, a system parallel computing platform, a system power supply module, a system analog quantity acquisition module, a system bus interface module and a system digital quantity receiving module. The test system can meet the test requirements of different models and different types of carrier rocket electrical system equipment, and can realize the general test of various mainstream carrier rocket electrical equipment.

Provided is a chiplet including an interconnect module for connecting to another chiplet, a bus interface for connecting to at least one functional module in the chiplet, and an address remapper block connected to the interconnect module and the bus interface, in which the address remapper block receives a transaction and remaps a destination address in the transaction.

The utility model relates to an accumulated water monitoring device which comprises a contact type water sensor, an ultrasonic water depth sensor, a temperature sensor, an MCU microprocessor, a 4G communication module and a power supply module. Wherein the output end of the contact type water sensor is connected with the ADC signal input end of the MCU microprocessor, the data output end of the ultrasonic water depth sensor is connected with the UART data receiving interface of the MCU microprocessor, the I2C data output end of the temperature sensor is connected with the I2C bus interface of the MCU microprocessor, and the data output end of the MCU microprocessor is connected with the UART instruction input end of the 4G communication module. The power module supplies power. According to the accumulated water monitoring device, a stepped contact structure is formed by the contact type water sensor and the ultrasonic water depth sensor, and deep dormancy control of the low-power-consumption main control chip is matched, so that high-accuracy, environment condition interference-resistant and low-power-consumption running accumulated water dynamic monitoring is realized.

The present disclosure relates to a Controller Area Network, CAN, transceiver, comprising: a CAN BUS interface, a transmit data, TXD, interface, a receive data, RXD, interface, a receiver, and a transmitter, wherein the transceiver is configured to receive, via the TXD interface, from a CAN controller, a digital TXD transmit signal representing a frame, wherein the transmitter is configured to generate, at the CAN BUS interface, a BUS signal representing the bits of the frame in a sequence, wherein the transceiver is configured to measure an electrical current of the transmitter, to detect each dominant bit represented by the BUS signal based on the transmitter current, to detect an error sequence of at least six consecutive dominant bits being detected based on the transmitter current, and to generate a control signal representing a fault of the transmitter in response to a detected error sequence.