792 results about "Bus interface" patented technology

The invention provides a fault rapid positioning method and device in an MGX system, and belongs to the field of server system management and fault diagnosis. The method comprises the following steps: determining an idle universal serial bus interface on a mainboard, and selecting a target USB interface and a fixed IP network segment configuration corresponding to the target USB interface from the idle USB interface; the BMC establishes a physical connection with a device where the HMC is located through the target USB interface, and constructs a virtual local area network channel; in the virtual local area network channel, performing out-of-band communication between the BMC and the HMC; the BMC obtains list information of each component in the MGX system from the HMC, and classifies the list information according to component types; the HMC pre-collects and stores the state information of each category according to the classification result; and the BMC periodically reads the state information based on the Redfish protocol, and identifies the fault in the MGX system according to the state information. According to the method and the device provided by the invention, the fault can be quickly and accurately positioned.

The invention provides a power domain control software architecture and a controller thereof, the software architecture comprises an application layer developed based on an AUTOSAR standard, a runtime environment and a basic software layer, the application layer comprises a plurality of modularized software components, the software components package service logic functions of the controller to be integrated, the software components are provided with an AUTOSAR-based ARXML file definition interface, and the AUTOSAR-based ARXML file definition interface is used for defining the service logic functions of the controller to be integrated. According to the method, the interface compatibility can be improved, seamless integration of application layers across controllers can be realized, and the development parallelism is enhanced by kernel deployment of independently packaged software components according to the real-time performance of functions. The runtime environment generates an inter-core communication agent code, constructs a virtual bus and routes a service request of an application layer component to the basic software layer, and the basic software layer provides system-level service for the application layer through a virtual bus interface of the runtime environment, so that the application layer does not need to directly operate hardware, software and hardware decoupling is realized, and the service performance of the application layer is improved. And smooth realization of software fusion and integration is promoted.

The invention belongs to the field of edge computing acceleration, and relates to a fast Fourier transform and neural network reasoning collaborative computing acceleration method, which comprises the following steps of: deploying a computing method which is based on butterfly computing merging and a tensor mapping strategy and is mixed with DFT (Discrete Fourier Transform) and FFT (Fast Fourier Transform) in an operator deployment level; on the interface integration level, a bus interface of a register access path in a tensor accelerator control path is subjected to lightweight reconstruction, so that the bus interface is adaptive to an edge computing platform; in an operation level, a user-defined instruction is introduced into a tensor calculation unit, and an accelerator is enabled to independently complete a whole-process task of FFT signal processing and NN intelligent identification. According to the method, an operation instruction set is expanded on hardware, and delay overhead caused by returning a large amount of intermediate data to a processor is avoided, so that efficient execution of FFT and neural network tasks on unified hardware is guaranteed, and multiple requirements of high real-time performance, high precision and low power consumption are met.

The invention discloses a self-calibration high-resolution PWM (Pulse Width Modulation) signal generating circuit, which belongs to the field of electronic circuits and comprises a PWM signal generating module, a high-resolution module, a calibration module, a register module and an AHB (Advanced High-performance Bus) interface. The PWM signal generation module generates a coarse adjustment PWM signal based on a comparison result of the comparison register and the counter; and the high-resolution module performs fine edge positioning on the coarse adjustment PWM wave to generate a fine adjustment PWM signal. Under the condition that the clock frequency is not changed, the high-resolution module can improve the resolution of the PWM signal. The calibration module has a high-resolution calibration function, and the high-resolution calibration function can avoid the deviation of a delay value caused by the environment and ensure the accuracy and stability of the high-resolution PWM. The register module is responsible for register read-write control. The AHB bus interface part is responsible for processing bus interface signals. The self-calibration high-resolution PWM signal generation circuit has the advantages of being high in precision, high in stability, easy to IP and the like.

The invention provides a server mainboard and a link management method, which can be applied to the technical field of servers. The server mainboard comprises: at least one server node, which comprises a host bus interface and a programming bus interface; the connector is electrically connected with the at least one expansion board through a cable; the first controller comprises a control bus interface and is used for receiving the link bit number information sent by the at least one expansion board and carrying out misplug verification on the at least one expansion board; the link control module is used for determining a service node bus interface from the host bus interface and the programming bus interface based on the received in-place signal of the at least one expansion board, and taking the service node bus interface as a target bus interface in a first time period; and taking the control bus interface as a target bus interface in a second time period different from the first time period, so that a target link for transmitting a target serial bus signal is formed between the target bus interface and the connector.

The invention discloses an equipment management system and a server, and relates to the technical field of servers, and the equipment management system is characterized in that a topology identifier storage assembly for storing slot position signal source identifiers is moved to a server mainboard end, so that the occupation of mainboard connector pins by information transmission is reduced; and meanwhile, the management control component establishes and stores a corresponding relation between the address of the arbitration component and the screen printing area of the case. The adapter card does not need to be pre-bound and configured, can automatically identify the screen printing area of the case through the relationship by inserting any communication interface of the mainboard, and generates slot screen printing information in combination with the pre-stored signal source identifier. The problems that a large number of pins are occupied due to the fact that the adapter card hardware address signal identification configuration needs to be transmitted through a connector, and the adapter card needs to be bound with the fixed configuration and lacks flexibility in the prior art are solved. The technical effects of reducing pin occupation, realizing flexible plugging of the adapter card and automatic identification of screen printing, reducing hardware development cost and meeting the requirement of the server for reserving more bus interfaces for the connector are achieved.

Scan testing features on a chip may include a streaming scan network (SSN) with core streaming scan hubs (CSHs). A CSH may include a parent bus interface, a child bus interface, and a streaming scan hub (SSH). A CSH may also include multiplexing logic configured to select whether the child bus interface is included in the SSN or excluded from the SSN. Multiple CSHs may be interconnected in a hierarchical topology through the child bus interfaces.

Certain examples described herein relate to at least a cryptographic system and a method of operating a cryptographic system. The cryptographic system may be implemented as a co-processor for performing post-quantum cryptographic functions. The cryptographic system has a set of bus interfaces for coupling to an external computing system, a cryptographic math unit and a control unit. The cryptographic math unit in certain examples is adapted to provide one or more masked modes of operation that secure the cryptographic operations against side-channel and non-invasive attacks. The method of operating a cryptographic system involves annotating secret data and tracking those annotations through one or more arithmetic operations.

The invention provides a simulation scene construction and simulation method and system for a large-scale unmanned cluster, and relates to the technical field of unmanned system simulation. The method comprises the steps of modeling a target task based on execution logic for the target task of the large-scale unmanned cluster to obtain an execution structure; decoupling the target task into a plurality of weak coupling subsystems based on the execution structure, and constructing a parallel simulation environment for the target task; based on the execution function category of the target task, constructing a bus interface of a corresponding category; constructing an intelligent algorithm plug-in corresponding to the execution function category based on the bus interface of each category; integrating the intelligent algorithm plug-in into the execution structure of the target task to form an execution model of the target task; and deploying the execution model to a parallel simulation environment to obtain a simulation scene of the target task. The problems that in large-scale unmanned cluster complex task simulation, the calculated amount is large, real-time simulation cannot be achieved, and the simulation accuracy and effect of cross-platform complex tasks are poor are solved.

A system and method of reducing data loss in a system utilizing a bus protocol that does not support flow control is disclosed. The peripheral device utilizes a spill buffer which is used to capture any data sent by the host before the peripheral device is able to properly configure the DMA controller. Additionally, the peripheral device includes a recovery routine, which is a software program that parses the spill buffer and extracts any headers or payloads that are contained therein. Using the spill buffer and recovery routine, the baud rate of the bus interface may be increases without incurring any increase in data loss.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention discloses a configurable peripheral interface and controller system, the interface comprises an APB bus interface and a PSC controller, and a UART module, an SPI module and an IIC module are connected between the APB bus interface and the PSC controller; according to the received control signal, the pin, connected with the PSC controller, of the UART module is controlled to be communicated with the external pin of the PSC controller, the pin, connected with the PSC controller, of the SPI module is controlled to be communicated with the external pin of the PSC controller, or the pin, connected with the PSC controller, of the IIC module is controlled to be communicated with the external pin of the PSC controller. According to the invention, UART, SPI and IIC functions can be realized through the configuration of the PSC controller, an independent UART module, an independent SPI module and an independent IIC module do not need to be integrated, and pins are greatly reduced.

The invention relates to a controller area network (CAN) transceiver comprising a transmit data (TXD) interface, a receive data (RXD) interface, a bus interface for coupling to a CAN bus, a receiver unit, a transmitter unit and a wake-up unit, in which the bus interface is configured to receive a first differential voltage signal, referred to as a bus signal, from the CAN bus via the bus interface, wherein the wake-up unit is configured to detect an end of frame (EOF) field representing the first CAN frame in the bus signal and / or a quiet section of an intermittent space (ITM) following the EOF field based on the bus signal, wherein the wake-up unit is configured to detect at least one wake-up pulse having a differential bus voltage less than a first predefined negative threshold voltage (TH1) in a silence section of the bus signal. The invention also relates to a CAN device, a CAN system and a method for a CAN transceiver.

The invention discloses an embedded SoC-level real-time monitoring and analyzing device. The embedded SoC-level real-time monitoring and analyzing device is composed of a bus comparator, a system event counter and a control register set. The bus comparator collects access signals of an address bus, a data bus and an instruction bus in real time, compares the access signals with a preset matching rule, generates a trigger signal for driving the event state register to record and output an interrupt signal or a debugging signal during matching, and takes the trigger signal as an input event of the system event counter; the system event counter monitors various events generated in the operation process, and when the monitoring result is equal to a preset reference value, a trigger signal is generated; and the control register group configures the matching condition of the bus comparator, sets the counting mode of the system event counter, and reads the comparison state, the event counting result and related monitoring information through the bus interface. According to the method, a configurable event capture mechanism and multiple counting modes are introduced in a hardware level, so that the dependence on software debugging is reduced, and the real-time performance of monitoring and analysis is improved.

The invention provides a graphic display agent device based on a PCIE (Peripheral Component Interface Express) bus, which is characterized in that an instruction analysis module receives a graphic drawing instruction containing an operation type and a corresponding coordinate parameter through a PCIE bus interface, and generates first pixel data based on the instruction; meanwhile, the data conversion module receives original image data containing pixel position information and sensor echo information through a radar video interface, analyzes the original image data and converts the original image data into second pixel data consistent with the first pixel data in format, and the format difference of the two types of data is eliminated to meet the superposition condition; a graph superposition processing module generates a primary and secondary clear composite image according to the logic that the first pixel data covers the second pixel data; then, the image output control module receives the synthesized image by using a first buffer area and a second buffer area which alternately work to ensure that a complete image frame is transmitted to a subsequent module; and finally, the video signal generation module converts the complete image frame into an analog video signal conforming to a preset video time sequence and outputs the analog video signal.

The invention discloses an elevator operation safety intelligent monitoring method and system, and relates to the technical field of elevator operation safety monitoring, and the method comprises the steps: collecting elevator multi-source operation data in real time through a bus interface, arranging sensors in a lift car, a shaft and a machine room, synchronously sampling various signals, building an operation state machine by combining position information and a door lock state, dividing the operation process into a plurality of working condition sections and organizing original data according to the working condition sections; calculating a multi-dimensional health index in a working condition section, and dynamically modeling an adaptability threshold by combining real-time characteristics and historical statistical data; and multi-dimensional indexes are compared in real time based on threshold values, and abnormal scores are calculated in a fused mode, so that fault sources are recognized, and intelligent monitoring of elevator operation safety is achieved. According to the method, through multi-source data real-time collection, working condition section division, dynamic threshold modeling and multi-index fusion analysis, refined monitoring of the elevator running state is achieved, the accuracy of anomaly detection and the fault positioning capacity are improved, and the safety and reliability of the elevator are improved.

The invention relates to the technical field of quantum computer control, and belongs to a quantum equipment instruction distribution system and method based on multi-thread parallel routing, the system comprises an upper computer, an instruction board, an instruction routing board and an equipment end, and the instruction distribution method comprises the following steps: S1, inputting a program instruction and a control instruction through the upper computer, the data is issued to the instruction board through the local bus interface; s2, multi-thread parallel execution of the program instruction is achieved in an instruction board FPGA chip, a control instruction is generated and output to a routing board through a high-speed radio frequency interface, and the control instruction comprises a target address code; s3, dynamically selecting an output port by the instruction routing board according to the target address code generated in S2, and distributing the instruction to specified equipment; and S4, each device in the device end receives the instruction through the SSMA sequence interface and executes the instruction. According to the invention, efficient synchronous control of quantum equipment is realized through multi-thread parallel execution and a dynamic routing mechanism.

The invention relates to the technical field of integrated circuits, in particular to an elliptic curve digital signature verification accelerator based on an ARM and FPGA integrated heterogeneous platform, which comprises an ARM processor used for executing a software program and connected with the elliptic curve digital signature verification accelerator on the FPGA through an AXI 4 bus interface; wherein the signature verification accelerator comprises a Hash calculation module, a large number reduction module, a public key decoding module and a double scalar multiplication module; the hash calculation module and the large number reduction module calculate and simplify a source operand; the public key decoding module converts operands into coordinates on an elliptic curve; and the double-scalar multiplication module verifies the reliability of the signature and returns a calculation result to the ARM processor, so that a verification task of one-time digital signature is realized. According to the system, the calculation speed of digital signature verification can be accelerated through hardware under limited hardware resource consumption, and the calculation burden of the ARM processor is relieved.

The invention discloses a request processing system and method for RISC-V and FPGA system-on-chip, the system comprises an RISC-V subsystem, an FPGA subsystem and an internet subsystem constructed based on RISC-V resources, and the internet subsystem comprises a bus matrix and an arbitration unit; the bus matrix comprises a plurality of bus interfaces and a plurality of protocol conversion mechanisms; the bus matrix is used for receiving a request initiated by the main equipment by utilizing a bus interface matched with the main equipment; the arbitration unit is used for arbitrating a target request; the bus matrix is also used for converting the target request into a target request adaptive to a second bus interface protocol of the target slave equipment by using a target protocol conversion mechanism, and sending the target request to the target slave equipment; and receiving the target request processing result, converting the target request processing result into a target request processing result adaptive to the first bus interface protocol, and returning the target request processing result to the target master device. Therefore, a cross-domain request processing mechanism is provided, and efficient processing of the cross-domain request can be realized.

The invention provides an SIMON encryption and decryption hardware acceleration system and method based on a Loongson soft core, and the system comprises a LoongArch processor soft core which is used for control, task scheduling and data interaction with external equipment; the SIMON encryption / decryption coprocessor module is used for executing an SIMON lightweight block encryption algorithm, completing key expansion and round function calculation and realizing encryption and decryption functions; the SRAM module is used for caching an original text, a ciphertext and intermediate data generated in the encryption and decryption process and supporting efficient data access; and the AXI bus interface module is used for high-speed data interaction between the SIMON encryption / decryption coprocessor module and the processor core and between the SIMON encryption / decryption coprocessor module and the SRAM module, and supports burst read-write operation. The method has high efficiency, flexibility and low power consumption, and can be widely applied to data encryption and transmission scenes of an embedded system and Internet of Things equipment.

The invention provides a firmware upgrading method, a field programmable gate array (FPGA) and a server, the firmware upgrading method is applied to the FPGA on the server, a first differential pin pair of the FPGA is connected with a BMC, and a plurality of second differential pin pairs are connected with universal serial bus (USB) interfaces of a plurality of board card devices in a one-to-one correspondence mode; the FPGA at least comprises a control unit and a switching unit; the method comprises the steps that a control unit receives an upgrading instruction sent by a BMC; the control unit controls the switching unit to switch to a target channel according to the upgrading instruction and establishes USB communication with the board card equipment to be upgraded through the target channel, and the target channel comprises a bottom transceiver of the switching unit, a target differential pin pair and a target USB interface connected with the target differential pin pair; and the control unit receives the upgrading data packet sent by the BMC, and sends the upgrading data packet to the to-be-upgraded board card equipment through the target channel, so that the to-be-upgraded board card equipment upgrades firmware based on the upgrading data packet, and the upgrading efficiency and stability are improved.

The invention discloses a CAN bus activity detection and wake-up circuit and method, and belongs to the technical field of CAN bus communication, the CAN bus activity detection and wake-up circuit comprises a CAN bus interface circuit, a signal detection and processing circuit and a controller, the input end of the CAN bus interface circuit is connected with a CAN bus; the signal detecting and processing circuit comprises a voltage comparator, the non-inverting input end and the inverting input end of the voltage comparator respectively receive a CANH signal and a CANL signal which are electrically isolated by the CAN bus interface circuit, and the output end of the voltage comparator is connected to a wake-up pin of the controller; the controller is used for monitoring the level state of the wake-up pin, and when the level of the wake-up pin is in an effective state, the electronic equipment is controlled to be switched from the sleep mode to the normal working mode. By introducing an electrical isolation and voltage difference detection mechanism, the problem of false wake-up caused by common-mode interference or bus noise in the prior art is solved, and reliable wake-up under low power consumption is realized.

The invention provides a satellite-borne basic mirror image and customized mirror image containerization deployment operation system and method, and the method comprises the steps: packaging a fixed basic service to form a basic mirror image, such as a satellite-borne hardware drive program, an AI resource interface program, a storage resource interface program, a telemetering and remote control bus interface program, and a PCIE / 10-gigabit network interface high-speed bus interface program; and subscribing to a distribution interface program among satellites and the like. The customized mirror image uses the basic mirror image through a docker FROM command; the customized mirror image comprises a remote sensing intelligent interpretation AI model mirror image, an inter-satellite cooperative task planning mirror image, a user data issuing broadcast mirror image and the like; the basic mirror image serves as factory software firmware of satellite development, the customized mirror image can be tested without binding during batch production of satellites, the basic mirror image is printed on the sky, and the customized mirror image is subjected to on-orbit programming according to user requirements, or a service operation mirror image is pulled from a space-based private mirror image warehouse.

A networking switch, including: a descriptor decoder configured to obtain descriptor data by decoding a direct memory access (DMA) descriptor packet encapsulated in a packet transferred, the packet from a host device; and a link power controller configured to adjust, based on the descriptor data, a power state of a link to be passed through in a bus interface connected to the networking switch.

The invention relates to the technical field of embedded systems and signal acquisition, in particular to a high-speed AD acquisition system and method based on MCU and FPGA time division multiplexing. A change-over switch is integrated in an FPGA processor, the change-over switch is used for communicating an ADC SPI interface with an SPI interface of an MCU controller in a parameter configuration stage and communicating the ADC SPI interface with main control logic in the FPGA processor in a high-speed acquisition stage, and the FPGA processor is further provided with a high-speed parallel bus interface which is used for being connected with a parallel bus interface of the MCU controller in a data reading stage. And batch transmission of the cached data is realized. Physical path isolation is achieved through the change-over switch in the FPGA processor, it is ensured that the MCU controller is completely separated from the AD control bus in the high-speed collection stage, time sequence interference and bus conflict caused by the AD control bus are fundamentally avoided, and the stability and data integrity of the collection process are guaranteed.

Provided is a chiplet including an interconnect module for connecting to another chiplet, a bus interface for connecting to at least one functional module in the chiplet, and a save and forward module connected to the interconnect module and the bus interface, in which the save and forward module includes a slave port that receives a transaction from one of the interconnect module or the bus interface, a data buffer that temporarily stores at least a portion of the transaction, and a master port that transmits the transaction stored in the data buffer to the other one of the interconnect module or the bus interface, and the transaction is divided into predetermined units and transmitted.

The invention discloses a cache controller for multi-control storage, a control method, a system and a server, is applied to the technical field of storage hardware, and aims to solve the problems of wiring complexity, cost reduction, cache utilization rate improvement and write-in delay of multi-control storage in related technologies. The cache controller comprises a switch supporting multi-host information sharing, a cache module connected with the switch and a central processing unit, the switch is provided with at least two first external bus interfaces used for being connected with storage controller nodes, and the central processing unit is connected with the cache module and the central processing unit. The division module is used for dividing a corresponding cache region for the storage controller node in the cache module under the condition that the switch detects that the storage controller node is accessed to the switch; the switch is used for acquiring the cache data sent by the storage controller node and writing the cache data into a cache region corresponding to the storage controller node in the cache module; the wiring complexity, the wiring cost and the writing delay can be reduced, and the cache utilization rate is improved.

Provided is a chiplet including an interconnect module for connecting to another chiplet, a bus interface for connecting to at least one functional module in the chiplet, and an address remapper block connected to the interconnect module and the bus interface, in which the address remapper block receives a transaction and remaps a destination address in the transaction.

A device connectable between a host computer and a computer peripheral over a standard bus interface is disclosed, used to improve security, and to detect and prevent malware operation. Messages passing between the host computer and the computer peripherals are intercepted and analyzed based on pre-configured criteria, and legitimate messages transparently pass through the device, while suspected messages are blocked. The device communicates with the host computer and the computer peripheral using proprietary or industry standard protocol or bus, which may be based on a point-to-point serial communication such as USB or SATA. The messages may be stored in the device for future analysis, and may be blocked based on current or past analysis of the messages. The device may serve as a VPN client and securely communicate with a VPN server using the host Internet connection.

Provided is an electronic device, including a first chiplet including a first bus interface, a first interconnect management module, and a first interconnect module, and a second chiplet connected to the first chiplet through the first interconnect module, wherein, in response to an occurrence of a request transaction associated with the second chiplet, the first interconnect management module stores, in a register, first information associated with the request transaction.