599 results about "Bus interface" patented technology

The invention provides a fault rapid positioning method and device in an MGX system, and belongs to the field of server system management and fault diagnosis. The method comprises the following steps: determining an idle universal serial bus interface on a mainboard, and selecting a target USB interface and a fixed IP network segment configuration corresponding to the target USB interface from the idle USB interface; the BMC establishes a physical connection with a device where the HMC is located through the target USB interface, and constructs a virtual local area network channel; in the virtual local area network channel, performing out-of-band communication between the BMC and the HMC; the BMC obtains list information of each component in the MGX system from the HMC, and classifies the list information according to component types; the HMC pre-collects and stores the state information of each category according to the classification result; and the BMC periodically reads the state information based on the Redfish protocol, and identifies the fault in the MGX system according to the state information. According to the method and the device provided by the invention, the fault can be quickly and accurately positioned.

The invention provides a power domain control software architecture and a controller thereof, the software architecture comprises an application layer developed based on an AUTOSAR standard, a runtime environment and a basic software layer, the application layer comprises a plurality of modularized software components, the software components package service logic functions of the controller to be integrated, the software components are provided with an AUTOSAR-based ARXML file definition interface, and the AUTOSAR-based ARXML file definition interface is used for defining the service logic functions of the controller to be integrated. According to the method, the interface compatibility can be improved, seamless integration of application layers across controllers can be realized, and the development parallelism is enhanced by kernel deployment of independently packaged software components according to the real-time performance of functions. The runtime environment generates an inter-core communication agent code, constructs a virtual bus and routes a service request of an application layer component to the basic software layer, and the basic software layer provides system-level service for the application layer through a virtual bus interface of the runtime environment, so that the application layer does not need to directly operate hardware, software and hardware decoupling is realized, and the service performance of the application layer is improved. And smooth realization of software fusion and integration is promoted.

The invention belongs to the field of edge computing acceleration, and relates to a fast Fourier transform and neural network reasoning collaborative computing acceleration method, which comprises the following steps of: deploying a computing method which is based on butterfly computing merging and a tensor mapping strategy and is mixed with DFT (Discrete Fourier Transform) and FFT (Fast Fourier Transform) in an operator deployment level; on the interface integration level, a bus interface of a register access path in a tensor accelerator control path is subjected to lightweight reconstruction, so that the bus interface is adaptive to an edge computing platform; in an operation level, a user-defined instruction is introduced into a tensor calculation unit, and an accelerator is enabled to independently complete a whole-process task of FFT signal processing and NN intelligent identification. According to the method, an operation instruction set is expanded on hardware, and delay overhead caused by returning a large amount of intermediate data to a processor is avoided, so that efficient execution of FFT and neural network tasks on unified hardware is guaranteed, and multiple requirements of high real-time performance, high precision and low power consumption are met.

Certain examples described herein relate to at least a cryptographic system and a method of operating a cryptographic system. The cryptographic system may be implemented as a co-processor for performing post-quantum cryptographic functions. The cryptographic system has a set of bus interfaces for coupling to an external computing system, a cryptographic math unit and a control unit. The cryptographic math unit in certain examples is adapted to provide one or more masked modes of operation that secure the cryptographic operations against side-channel and non-invasive attacks. The method of operating a cryptographic system involves annotating secret data and tracking those annotations through one or more arithmetic operations.

The invention provides a simulation scene construction and simulation method and system for a large-scale unmanned cluster, and relates to the technical field of unmanned system simulation. The method comprises the steps of modeling a target task based on execution logic for the target task of the large-scale unmanned cluster to obtain an execution structure; decoupling the target task into a plurality of weak coupling subsystems based on the execution structure, and constructing a parallel simulation environment for the target task; based on the execution function category of the target task, constructing a bus interface of a corresponding category; constructing an intelligent algorithm plug-in corresponding to the execution function category based on the bus interface of each category; integrating the intelligent algorithm plug-in into the execution structure of the target task to form an execution model of the target task; and deploying the execution model to a parallel simulation environment to obtain a simulation scene of the target task. The problems that in large-scale unmanned cluster complex task simulation, the calculated amount is large, real-time simulation cannot be achieved, and the simulation accuracy and effect of cross-platform complex tasks are poor are solved.

A system and method of reducing data loss in a system utilizing a bus protocol that does not support flow control is disclosed. The peripheral device utilizes a spill buffer which is used to capture any data sent by the host before the peripheral device is able to properly configure the DMA controller. Additionally, the peripheral device includes a recovery routine, which is a software program that parses the spill buffer and extracts any headers or payloads that are contained therein. Using the spill buffer and recovery routine, the baud rate of the bus interface may be increases without incurring any increase in data loss.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention discloses a configurable peripheral interface and controller system, the interface comprises an APB bus interface and a PSC controller, and a UART module, an SPI module and an IIC module are connected between the APB bus interface and the PSC controller; according to the received control signal, the pin, connected with the PSC controller, of the UART module is controlled to be communicated with the external pin of the PSC controller, the pin, connected with the PSC controller, of the SPI module is controlled to be communicated with the external pin of the PSC controller, or the pin, connected with the PSC controller, of the IIC module is controlled to be communicated with the external pin of the PSC controller. According to the invention, UART, SPI and IIC functions can be realized through the configuration of the PSC controller, an independent UART module, an independent SPI module and an independent IIC module do not need to be integrated, and pins are greatly reduced.

The invention discloses an embedded SoC-level real-time monitoring and analyzing device. The embedded SoC-level real-time monitoring and analyzing device is composed of a bus comparator, a system event counter and a control register set. The bus comparator collects access signals of an address bus, a data bus and an instruction bus in real time, compares the access signals with a preset matching rule, generates a trigger signal for driving the event state register to record and output an interrupt signal or a debugging signal during matching, and takes the trigger signal as an input event of the system event counter; the system event counter monitors various events generated in the operation process, and when the monitoring result is equal to a preset reference value, a trigger signal is generated; and the control register group configures the matching condition of the bus comparator, sets the counting mode of the system event counter, and reads the comparison state, the event counting result and related monitoring information through the bus interface. According to the method, a configurable event capture mechanism and multiple counting modes are introduced in a hardware level, so that the dependence on software debugging is reduced, and the real-time performance of monitoring and analysis is improved.

The invention provides a graphic display agent device based on a PCIE (Peripheral Component Interface Express) bus, which is characterized in that an instruction analysis module receives a graphic drawing instruction containing an operation type and a corresponding coordinate parameter through a PCIE bus interface, and generates first pixel data based on the instruction; meanwhile, the data conversion module receives original image data containing pixel position information and sensor echo information through a radar video interface, analyzes the original image data and converts the original image data into second pixel data consistent with the first pixel data in format, and the format difference of the two types of data is eliminated to meet the superposition condition; a graph superposition processing module generates a primary and secondary clear composite image according to the logic that the first pixel data covers the second pixel data; then, the image output control module receives the synthesized image by using a first buffer area and a second buffer area which alternately work to ensure that a complete image frame is transmitted to a subsequent module; and finally, the video signal generation module converts the complete image frame into an analog video signal conforming to a preset video time sequence and outputs the analog video signal.

The invention discloses an elevator operation safety intelligent monitoring method and system, and relates to the technical field of elevator operation safety monitoring, and the method comprises the steps: collecting elevator multi-source operation data in real time through a bus interface, arranging sensors in a lift car, a shaft and a machine room, synchronously sampling various signals, building an operation state machine by combining position information and a door lock state, dividing the operation process into a plurality of working condition sections and organizing original data according to the working condition sections; calculating a multi-dimensional health index in a working condition section, and dynamically modeling an adaptability threshold by combining real-time characteristics and historical statistical data; and multi-dimensional indexes are compared in real time based on threshold values, and abnormal scores are calculated in a fused mode, so that fault sources are recognized, and intelligent monitoring of elevator operation safety is achieved. According to the method, through multi-source data real-time collection, working condition section division, dynamic threshold modeling and multi-index fusion analysis, refined monitoring of the elevator running state is achieved, the accuracy of anomaly detection and the fault positioning capacity are improved, and the safety and reliability of the elevator are improved.

The invention relates to the technical field of quantum computer control, and belongs to a quantum equipment instruction distribution system and method based on multi-thread parallel routing, the system comprises an upper computer, an instruction board, an instruction routing board and an equipment end, and the instruction distribution method comprises the following steps: S1, inputting a program instruction and a control instruction through the upper computer, the data is issued to the instruction board through the local bus interface; s2, multi-thread parallel execution of the program instruction is achieved in an instruction board FPGA chip, a control instruction is generated and output to a routing board through a high-speed radio frequency interface, and the control instruction comprises a target address code; s3, dynamically selecting an output port by the instruction routing board according to the target address code generated in S2, and distributing the instruction to specified equipment; and S4, each device in the device end receives the instruction through the SSMA sequence interface and executes the instruction. According to the invention, efficient synchronous control of quantum equipment is realized through multi-thread parallel execution and a dynamic routing mechanism.

The invention discloses a request processing system and method for RISC-V and FPGA system-on-chip, the system comprises an RISC-V subsystem, an FPGA subsystem and an internet subsystem constructed based on RISC-V resources, and the internet subsystem comprises a bus matrix and an arbitration unit; the bus matrix comprises a plurality of bus interfaces and a plurality of protocol conversion mechanisms; the bus matrix is used for receiving a request initiated by the main equipment by utilizing a bus interface matched with the main equipment; the arbitration unit is used for arbitrating a target request; the bus matrix is also used for converting the target request into a target request adaptive to a second bus interface protocol of the target slave equipment by using a target protocol conversion mechanism, and sending the target request to the target slave equipment; and receiving the target request processing result, converting the target request processing result into a target request processing result adaptive to the first bus interface protocol, and returning the target request processing result to the target master device. Therefore, a cross-domain request processing mechanism is provided, and efficient processing of the cross-domain request can be realized.

The invention discloses a CAN bus activity detection and wake-up circuit and method, and belongs to the technical field of CAN bus communication, the CAN bus activity detection and wake-up circuit comprises a CAN bus interface circuit, a signal detection and processing circuit and a controller, the input end of the CAN bus interface circuit is connected with a CAN bus; the signal detecting and processing circuit comprises a voltage comparator, the non-inverting input end and the inverting input end of the voltage comparator respectively receive a CANH signal and a CANL signal which are electrically isolated by the CAN bus interface circuit, and the output end of the voltage comparator is connected to a wake-up pin of the controller; the controller is used for monitoring the level state of the wake-up pin, and when the level of the wake-up pin is in an effective state, the electronic equipment is controlled to be switched from the sleep mode to the normal working mode. By introducing an electrical isolation and voltage difference detection mechanism, the problem of false wake-up caused by common-mode interference or bus noise in the prior art is solved, and reliable wake-up under low power consumption is realized.

The invention relates to the technical field of embedded systems and signal acquisition, in particular to a high-speed AD acquisition system and method based on MCU and FPGA time division multiplexing. A change-over switch is integrated in an FPGA processor, the change-over switch is used for communicating an ADC SPI interface with an SPI interface of an MCU controller in a parameter configuration stage and communicating the ADC SPI interface with main control logic in the FPGA processor in a high-speed acquisition stage, and the FPGA processor is further provided with a high-speed parallel bus interface which is used for being connected with a parallel bus interface of the MCU controller in a data reading stage. And batch transmission of the cached data is realized. Physical path isolation is achieved through the change-over switch in the FPGA processor, it is ensured that the MCU controller is completely separated from the AD control bus in the high-speed collection stage, time sequence interference and bus conflict caused by the AD control bus are fundamentally avoided, and the stability and data integrity of the collection process are guaranteed.

The invention discloses a cache controller for multi-control storage, a control method, a system and a server, is applied to the technical field of storage hardware, and aims to solve the problems of wiring complexity, cost reduction, cache utilization rate improvement and write-in delay of multi-control storage in related technologies. The cache controller comprises a switch supporting multi-host information sharing, a cache module connected with the switch and a central processing unit, the switch is provided with at least two first external bus interfaces used for being connected with storage controller nodes, and the central processing unit is connected with the cache module and the central processing unit. The division module is used for dividing a corresponding cache region for the storage controller node in the cache module under the condition that the switch detects that the storage controller node is accessed to the switch; the switch is used for acquiring the cache data sent by the storage controller node and writing the cache data into a cache region corresponding to the storage controller node in the cache module; the wiring complexity, the wiring cost and the writing delay can be reduced, and the cache utilization rate is improved.

A device connectable between a host computer and a computer peripheral over a standard bus interface is disclosed, used to improve security, and to detect and prevent malware operation. Messages passing between the host computer and the computer peripherals are intercepted and analyzed based on pre-configured criteria, and legitimate messages transparently pass through the device, while suspected messages are blocked. The device communicates with the host computer and the computer peripheral using proprietary or industry standard protocol or bus, which may be based on a point-to-point serial communication such as USB or SATA. The messages may be stored in the device for future analysis, and may be blocked based on current or past analysis of the messages. The device may serve as a VPN client and securely communicate with a VPN server using the host Internet connection.

In a charging and discharging method for universal serial bus interface and an electronic device, whether a data line with dual universal serial bus connectors is connected to the electronic device is detected by a detection circuit; when the data line with dual universal serial bus connectors is detected to be connected to the electronic device, whether a voltage bus at one end of the data line connected to the electronic device has a voltage is determined; when the voltage bus at one end of the data line connected to the electronic device has no voltage is detected, role of the electronic device is assigned as a discharge device for discharging; and when the voltage bus at one end of the data line connected to the electronic device has the voltage is detected, the role of the electronic device is assigned as a charging device for charging.

The invention provides a multifunctional channel detection system based on a Zynq chip. The multifunctional channel detection system is characterized in that a system main control module is deployed at an ARM processor end of the Zynq chip; the protocol analysis control module, the fault-tolerant detection excitation module and the bottom hardware adaptation module are deployed at the FPGA programmable logic end of the Zynq chip; the system main control module communicates with each module of the FPGA programmable logic end through an AXI bus; the underlying hardware adaptation module receives the configuration from the system main control module and completes electrical adaptation and dynamic switching of various bus interfaces; the protocol analysis control module receives an instruction from the system main control module, and performs protocol analysis and feature verification on at least one of an SPI bus, an IIC bus and a 1553B bus; the fault-tolerant detection excitation module receives the trigger from the system main control module and injects a controllable fault into the tested bus interface; and the system master control module integrates the verification result and the injection feedback to complete the performance and reliability evaluation of the bus channel.

The application provides a virtual modeling-based flight control ICD protocol simulation verification system and a flight control system, comprising a network topology modeling module, a virtual bus modeling service module, an ICD modeling service module, a processing algorithm modeling service module and an ICD simulation running monitoring module, and each module cooperatively realizes a full-process closed loop from ICD analysis to virtual bus simulation verification. The application completes network construction of the system by simulating the commonly used system network bus in the design stage, and in combination with the data processing algorithm, the business data interaction between the system nodes can be simulated in the system design front end, the ICD design problem is identified, the compatibility verification of the ICD and the hardware bus interface is completed in the design front end, the rework waste caused by the design mismatch problem is reduced, and the reliability and delivery efficiency of the system are improved.

The invention discloses a verification system of an FSMC multi-memory interface based on a UVM, and belongs to the technical field of chip verification. The verification system of the FSMC multi-memory interface based on the UVM comprises a test layer, a simulation instruction definition layer, an AHB bus interface component, an assertion inspection component and an external memory interface component. The problems that in the prior art, a single memory is mainly connected for verification, only a single protocol can be verified, the verification means is limited, and the efficiency and the coverage rate are not high are solved, the transmission type of the AHB is defined in the environment configuration component, therefore, the verification diversity is improved, the verification requirements for verifying different memory interfaces are well met, and the verification efficiency is improved. According to the interface protocol verification method and device, the randomized excitation and self-checking function conforming to the protocol can be generated, the verification comprehensiveness is greatly improved, the pertinence and correctness of the verified module are greatly improved, the verification efficiency is improved, the code cost is reduced, and the accuracy of interface protocol verification is improved.

The embodiment of the invention provides a security control method, a baseboard management controller, a computer program product and a storage medium. A security subsystem and a function subsystem which are isolated from each other by hardware are arranged in the baseboard management controller, so that the defense capability of the security subsystem to hardware attacks can be effectively guaranteed. On the basis, security control firmware is arranged in the security subsystem, and the security subsystem can control the computing device to be safely started by executing the security control firmware; moreover, through a bus interface of the baseboard management controller, an access request which is initiated by each system-on-chip in the computing equipment and aims at the target storage component can be received, and the security subsystem can perform access control on the access request by executing the security management and control firmware. Therefore, the baseboard management controller can be used as a platform trust root in the computing equipment to control the computing equipment to be safely started and protect data stored in the target storage component in the computing equipment, so that the safety of the computing equipment is guaranteed.

The invention relates to an FRU equipment management method based on soft-hard decoupling of a soft bus, and the method comprises the steps: setting a distributed soft bus in a transmission layer, taking the distributed soft bus as a center, and achieving the access of at least one FRU equipment node and a management equipment node from a physical layer to a network layer of an OSI seven-layer architecture, according to the distributed soft bus, the FRU equipment node is connected with the management equipment node, discovery, connection, networking and establishment of a transmission channel between the management equipment node and the FRU equipment node are realized, so that equipment with a bus interface can be easily accessed, the access efficiency is greatly improved, and the interconnection flexibility and expansibility of the management equipment can also be improved by the self-discovery function of the distributed soft bus; and on the other hand, an RPC framework is arranged on the session layer, a hardware isolation development platform is provided for applications from the session layer to the application layer through the RPC technology, and software and hardware isolation development can reduce the complexity of development and design, reduce the design difficulty and improve the implementation efficiency and stability of application management.

The invention provides a flight control ICD protocol simulation verification system based on virtual modeling and a flight control system. The flight control ICD protocol simulation verification system comprises a network topology modeling module, a virtual bus modeling service module, an ICD modeling service module, a processing algorithm modeling service module and an ICD simulation operation monitoring module, and all the modules cooperate to achieve a whole-process closed loop from ICD analysis to virtual bus simulation verification. According to the method, network construction of the system is completed by virtually simulating a common system network bus in a design stage, service data interaction between system nodes can be simulated and ICD design problems can be identified at a system design front end by combining a data processing algorithm, compatibility verification of the ICD and a hardware bus interface is completed at the design front end, and the design efficiency is improved. Reworking waste caused by the design mismatching problem is reduced, and the reliability and delivery efficiency of the system are improved.

A system and a method are disclosed for improving memory chiplets. In an embodiment, a memory chiplet comprises a memory stack and a base die. The base die includes a thru-silicon via (TSV) coupled to the memory stack, a memory controller coupled to the TSV through a first interface, and a die-to-die (D2D) interconnect. The base die further includes a link layer coupled to the memory controller configured to map a bus interface from the memory controller to a D2D interface of the D2D interconnect. Data mapped by the link layer is transmitted to a second chiplet with a parallel link layer corresponding to the link layer.

A cryptocurrency miner includes a serial bus, compute modules, and a controller. Each compute module includes upstream ports, downstream ports, a pass-through buffer coupling the upstream ports to the downstream ports, and a serial bus interface coupled to the serial bus via the first upstream ports and the first downstream ports. The controller controls operation of the compute modules via commands on the serial bus. The serial bus includes bus segments between respective upstream and downstream ports of the compute modules.

The invention discloses a data transmission method and system for a secure real-time bus (SRB), and the method comprises the steps: enabling a central processing unit to transmit data to be transmitted to a secure real-time bus interface device through a real-time transmission type interface if the data to be transmitted belong to real-time data when the data needs to be transmitted through the secure real-time bus; the secure real-time bus interface device caches the current data to be transmitted to a real-time data queue, and sends the data to be transmitted in the real-time data queue to the secure real-time bus for transmission within the cycle time of the secure real-time bus; and if the to-be-transmitted data belongs to non-real-time data, sending the to-be-transmitted data to the safe real-time bus interface device through the standard Ethernet interface. And the secure real-time bus interface device caches the current data to be transmitted to the non-real-time data queue, and sends the data to be transmitted in the non-real-time data queue to the secure real-time bus for transmission within the non-periodic time of the secure real-time bus.

A mode sequencer circuitry for a time-of-flight system, the time-of-flight system including at least an imaging unit and an illumination unit, the imaging unit having a data bus interface for transmitting data to an application processor over a data bus.

The invention provides a software online upgrading method of a DSP chip based on a CAN bus interface. The software online upgrading method comprises the steps that an OUT format file generated by compiling a source project is converted into a BIN file; the method comprises the steps that a BIN file is unpacked and subpackaged, generated data packets are sent to an FPGA, DSP software conducts CRC verification on each packet of data forwarded by the FPGA till all the data packets are received, and then the software moves all the data stored in an SDRAM and burns the data into a FLASH; reading data of the FLASH and source data stored in the SDRAM, and comparing the data and the source data one by one; the method comprises the following steps: reading an Entry Point of a Bin file, turning to circularly read an initial address and length of a program segment, moving effective data by a BOOT program according to data distribution in an mxp file, after all the data are read into a memory, calculating the cumulative sum of the read data, turning to an entry address of an APP program or a BACK program, and realizing booting of the program. The method can be used for improving the online upgrading function of the DSP.

1. The name of the design product: three interface protocol converter. 2. The use of the design product: for RJ45 network interface, CAN bus interface, USB interface between the protocol conversion to achieve three kinds of protocol between the two-way data remote intelligent conversion and transmission. 3. The design points of the design product: in shape. 4. The picture or photo that can best show the design points: perspective view.