100 results about "Bus interface" patented technology

serial communications bus.20 25 28 73 31 24 D ec 2 02 5 A B S T R A C T 2 0 2 5 2 8 7 3 3 1 2 4 D e c 2 0 2 5 s e r i a l c o m m u n i c a t i o n s b u s . 400 Serial communications bus interface 220A 408A Upstream Serial communications receiver bus 412A 404A 410 402 Upstream transmitter Upstream control 414A Clock Upstream enable Lock-out Serial communications Downstream control control circuit bus interface 220B Electronic 404B 414B processor Downstream Downstream enable 408B transmitter 406B 3 / 5 Downstream Serial communications receiver bus 412B FIG. 4 20 25 28 73 31 24 D ec 2 02 5 2 0 2 5 2 8 7 3 3 1 2 4 D e c 2 0 2 5 b u s i n t e r f a c e 4 0 6 A 2 0 2 t r a n s m i t t e r U p s t r e a m c o n t r o l U p s t r e a m e n a b l e Downstream control c o n t r o l c i r c u i t b u s i n t e r f a c e E l e c t r o n i c p r o c e s s o r D o w n s t r e a m D o w n s t r e a m e n a b l e t r a n s m i t t e r D o w n s t r e a m

A wireless communication system including an adapter is provided. The adapter is configured to connect with a host through a universal serial bus interface and connect with a handset through a Bluetooth interface to form a Bluetooth connection. After the adapter connects with the host through the universal serial bus interface and connects with the handset through the Bluetooth interface, the adapter is configured to provide a first IP address of the host to the handset to establish a Wi-Fi connection between the host and the handset. The Bluetooth connection is further configured to transmit an encryption key between the host and the handset. The Wi-Fi connection is not configured to transmit the encryption key.

The application discloses a cross-clock domain register synchronization method and device. It relates to the technical field of digital integrated circuit design. The method comprises the following steps: when the target clock domain is unavailable, routing the bus read-write request to a shadow register array driven by a system clock, and writing a write transaction log into a log queue when the write transaction is completed, the write transaction log comprising a target address, write data and byte enable; when the target clock domain changes from unavailable to available and the log queue is not empty, setting the handshake signal of the bus interface to invalid, reading the write transaction log from the log queue according to the write sequence, and writing the write data into the target register through a byte mask circuit according to the target address in the write transaction log; when the target clock domain is available and the log queue is empty, routing the bus read-write request to the target register, and setting the handshake signal of the bus interface to valid. The method realizes register access integrity and sequential consistency in the target clock dynamic change scenario.

A solid state device (SSD) includes two data storage controllers, each connected to a corresponding set of NAND chips. The SSD includes a Universal Serial Bus (USB)-C socket for receiving a USB-C plug in one of two mating orientations. One lane of the USB-C socket is connected to the first data storage controller. The second lane is connected to the second data storage controller. The two lanes are used for concurrent communications with a host, with lane communication protocols depending upon the mating orientation. In a first mating orientation, the first lane communication protocol may be USB 10 Gbps and the second lane communication protocol may be USB 2.0. In the second mating orientation, the protocols are reversed. The host thereby has concurrent access to both sets of NAND chips. Similar features are described for use with volatile memory devices such as dynamic random access memory (DRAM) devices.

Systems and methods related to electronic communication system extender devices are disclosed. The device includes a control input / output interface, a first bus interface, a second bus interface, and an electronic processor. The processor is configured to, when operating in an extender mode, receive, at the control input / output interface, first communications according to a first communication protocol from a control panel and output, from both the first serial communication bus interface and the second serial communication bus interface, the first communications according to a second communication protocol, the second communication protocol being a wired communication protocol. The processor is further configured to, when operating in an extender mode, receive, at the first bus interface, second communications according to the second communication protocol from a first electronic communication device and output, via the second bus interface, the second communications according to the second communication protocol to a second electronic communication device.

The application discloses a video coding device, method, system, program product and storage medium, and relates to the technical field of video processing.In the application, the video coding device can be connected with a host through a bus interface, and at least two video channels are arranged between the video coding device and the host.A processor, a programmable logic device, a memory, a direct memory access controller and a channel management register can be arranged in the video coding device.The channel management register stores channel configurations of the video channels, and the programmable logic device is provided with processing units corresponding to the video channels.In actual application, the processor can set an encoder for the processing units of the video channels according to the channel configurations, and the direct memory access controller can allocate transmission bandwidth for the video channels according to the channel configurations.In this way, the original video data of the video channels can be subjected to different coding and transmission processing, so that the flexibility and scalability of multi-video stream processing can be improved.

A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

This disclosure provides systems, methods, and devices for interconnecting components of an electronic device through a serial bus interface that supports detecting input / output data lines that are not operating as expected. In a first aspect, a method includes scheduling data to be transmitted over a plurality of input / output lines (e.g., of the serial bus) in a queue. The method includes determining that the condition is met (e.g., input / outlines are all in a high state) for the plurality of input / output lines prior to transmitting the data over the plurality of input / output lines. The method includes transmitting the data over the plurality of input / output lines in the queue when the condition is met for the plurality of input / output lines. Other aspects and features are also claimed and described.

An open architecture product coupling analysis method, which establishes a component comprehensive correlation matrix according to the correlation between the functions and structures of the components of an open architecture product, identifies the common platform, customized module and individualized module structure types of the open architecture product, determines the bus interface of the common platform, the input / output interface of the customized module and the input interface of the individualized module, identifies the coupling mode between the customized modules and the correlation between their functions and structures, calculates the coupling degree between the modules according to the comprehensive correlation between the functions and structures of the components between the correlated modules and the correlation density of the interfaces, establishes a change propagation probability matrix between the modules according to the interface relationship between the modules and the component dependency relationship within the modules, and calculates the change influence degree between the correlated modules. The present application is simple to calculate, improves work efficiency and shortens the development cycle.

The application provides an electromechanical actuating system and a redundancy management method. The electromechanical actuating system comprises a filtering module, a secondary power conversion module, a bus interface, a main control module, a power drive module and an actuator, wherein the filtering module comprises EMI filter 1, EMI filter 2, EMI filter 3 and EMI filter 4; the secondary power conversion module comprises secondary power conversion module 1 and secondary power conversion module 2; the main control module comprises main control module 1 and main control module 2; the power drive module comprises power drive module 1 and power drive module 2; and the actuator comprises motor winding 1, motor winding 2, a motor position sensor, a speed reducer, an actuator position sensor and a ball screw.

A firmware update method through a bus interface and a system performing the same are provided. The method comprises: sending, by an update initiator to an update object to which a firmware image is to be transferred, an update command to start an update session; obtaining, by the update initiator from the bus interface, a data rate toward the update object; calculating a transfer time estimate by dividing an image size of the firmware image with the data rate; setting a transfer time limit to a default value; determining whether the transfer time estimate is longer than the transfer time limit; and in response to determining that the transfer time estimate is longer than the transfer time limit, setting the transfer time limit to the transfer time estimate.

The application provides a multifunctional test chip and method based on a PXI architecture, and relates to the technical field of test chips; the chip comprises a bus interface, a functional module group and an address controller; the bus interface interacts with an upper computer through a PXI bus; the functional module group comprises pulse sending, detection, analog quantity acquisition / output, serial communication, a storage controller and a temperature acquisition module, and can realize pulse signal transceiving, analog quantity processing, serial communication, data storage and temperature acquisition; the address controller divides an address space into eight subspaces, and precise control is realized. The control method comprises the steps of initializing an interface circuit, executing pulse sending and detection, analog quantity output and acquisition, EEPROM operation, UART communication and temperature acquisition and the like. The application integrates special modules, replaces traditional FPGA design, improves performance and reliability, reduces resource waste, reduces cost, shortens the development cycle, and is suitable for complex test scenes such as spaceflight measurement and control.

This invention discloses an elevator edge computing device, including a communication interface, a control and acquisition interface, and an AI processing unit. The communication interface includes dual Ethernet ports and onboard WiFi and Bluetooth modules. The control and acquisition interface includes a USB interface, a CAN bus, an RS485 or RS232 interface, digital input, and digital output interfaces. The CAN bus interfaces with the elevator control system, and the RS485 and RS232 interfaces interface with various sensors or peripherals. The AI ​​processing unit is equipped with a trained AI model that features adaptive parameter optimization. The elevator edge computing device is installed on the elevator car in a locally deployed manner, enabling data communication and cloud-edge collaboration with a cloud platform. This invention has significant value in processing dense sensor signal data in the elevator car and optimizing local performance and cost.

A solid-state switch includes a power board and a control board. The power board is operational to switch on / off a high-voltage current, measure the high-voltage current, and sense a high voltage. The control board includes a microcontroller unit and a bus interface circuit. The control board is operational to pass control signals from the microcontroller unit to the power board for switching of the high voltage current, and pass sensed data from the power board to the control board for the high voltage current and the high voltage. The microcontroller unit is operational to calculate a pre-charge detection, an ampere squared seconds detection, an over current detection, an over temperature detection, and a short circuit detection, and report the detections external to the control board via the bus interface circuit.

This provides a new power cutoff technology for semiconductor integrated circuit devices. [Solution] The present invention is a semiconductor integrated circuit device comprising a bus, a processor circuit module, and a circuit module to be power-off. The bus comprises a bus core including data signal lines and a predetermined bus interface circuit for connecting the circuit module to the bus core. The predetermined bus interface circuit comprises a transaction control circuit for controlling transactions related to data transmission via the bus core, and a power control circuit including a power control register, which controls the power supply to the circuit module according to the register value held by the power control register. The power control circuit, under the control of the processor circuit module, controls the power supply to the circuit module to be cut off in accordance with a power-off instruction from the transaction control circuit.

The application relates to the electronic information technical field and provides a universal serial bus Type-C interface protection method, a universal serial bus Type-C interface, a control arbitrator, a chip and a chip module. The method comprises the following steps: obtaining a hardware counting result; the hardware counting result is obtained by a hardware counter according to an external device insertion detection signal of a hardware switch; the external device insertion detection signal represents whether an external device is inserted into the universal serial bus Type-C interface; obtaining a software counting result; the software counting result is obtained by a software counter according to a software function calling signal; and in the case that the sum of the hardware counting result and the software counting result indicates that the universal serial bus Type-C interface is not inserted with the external device, the universal serial bus Type-C interface is controlled to be in a power-off state. By adopting the method, it can be ensured that in the universal serial bus Type-C interface protection scene, the universal serial bus Type-C interface can still work normally when one of the hardware aspect or the software aspect is invalid or has a problem.

This invention relates to the field of rehabilitation training equipment technology, and discloses a fine motor skill assessment glove based on a miniature nine-axis sensor, comprising a flexible glove substrate, a sensor network, and a signal acquisition and transmission module. The sensor network consists of multiple flexible printed circuit board branches with multiple miniature nine-axis sensors and flexible pressure sensors arranged in a row. The signal acquisition and transmission module integrates a microcontroller unit and a communication unit. The communication pins of multiple miniature nine-axis sensors are connected in parallel to a common I2C bus interface, and the power supply pins are connected to general-purpose input / output pins. This invention provides independent power to the sensors by changing the voltage level of the microcontroller unit in a time-division multiplexing manner, avoiding bus voltage level conflicts; it uses absolute time alignment timestamps to eliminate asynchronous time-domain deviations in time-division multiplexing power supply polling; and it converts the raw data of three-dimensional acceleration and three-dimensional angular velocity into a fixed-point number format, combining table lookup and shift processing to generate fixed-point attitude angle results, reducing the internal computing resource consumption of the microcontroller unit.

This application relates to the field of electromagnetic propulsion technology, specifically disclosing a double-sided long stator linear drive system, including multiple subsystems and a main controller. Each subsystem includes an equal number of linear motor stator segments, six-phase switches, position detection devices, a common AC bus for the subsystem, and a subsystem control bus. The linear motor stator segments are connected to the common AC bus of the subsystem through corresponding six-phase switches, and then connected to the system common AC bus formed by the subsystem bus interfaces, which is connected to a six-phase converter composed of three-phase converters distributed in each subsystem. Each position detection device is connected to the system control bus through the subsystem control bus, and then to the main controller. The main controller controls the switching of each linear motor stator segment according to the installation order of the subsystems and the running position of the linear motor mover measured by the position detection devices. The subsystems can be randomly ordered and assembled without affecting the system operation, exhibiting good mobility.

The application discloses a verification method, device and equipment and a readable storage medium. The method comprises the following steps: constructing a write attribute, a read attribute and a comparison attribute according to operation representation bus interface signals and time sequences corresponding to write data and read data; binding the operation representation bus interface signals with corresponding bus interface signals of a to-be-tested module; judging whether signals corresponding to write data in bus interface signals of the to-be-tested module satisfy the write attribute and whether signals corresponding to read data satisfy the read attribute according to a binding relationship, so as to verify whether the time sequence is correct; and comparing write data and corresponding read data of the to-be-tested module according to the comparison attribute, so as to verify the consistency of the read-write data. The technical scheme disclosed by the application constructs the write attribute, the read attribute and the comparison attribute, automatically verifies corresponding time sequences by using the write attribute and the read attribute, and automatically verifies read-write data by using the comparison attribute, so that the verification efficiency and the verification accuracy are improved.

This utility model relates to an M-Bus master-slave communication data monitoring circuit, device, and smart meter, including an M-Bus to UART communication circuit and a UART to USB communication circuit. The M-Bus to UART communication circuit includes an M-Bus interface chip, an M-Bus signal input interface, and an adjustment circuit. The M-Bus bus is connected to the M-Bus signal input interface, which is connected to the M-Bus interface chip via the adjustment circuit. The UART to USB communication circuit includes a signal conversion chip and a USB interface. The data signal input and data signal output terminals of the M-Bus interface chip are connected to the signal conversion chip, which is connected to the USB interface. By setting up a two-stage conversion circuit, M-Bus communication data can be converted into a data format recognizable by the USB interface in real time, thereby achieving seamless connection with terminal devices such as PCs.

The application discloses a method for reducing bus commands through an improved cache, and belongs to the technical field of bus interface conversion and cache control in an SOC system. The method comprises the following steps: first, configuring the bit width, cache size and address offset related parameters of the internal and external buses, receiving an access command of an axi-lite bus and processing the access command to obtain addr_offset; then, inputting the addr_offset into the improved cache to query the hit state and the flag state of cmd_flag, save_flag and bus_flag, merging valid requests through a command merging module, generating an access request of an axi-full bus and sending the access request to a storage medium; after receiving the returned data, storing the returned data into the improved cache and updating the flag, and then extracting corresponding valid data through an effective data module and returning the valid data to the axi-lite bus. The improved cache adopts an LRU priority scheduling mechanism, and the request and data states are accurately identified through the flag, so that the command merging and cache multiplexing are realized.

The application is suitable for the technical field of multi-processor power supply, and provides a mainboard multi-processor compatible power supply adjusting method, device, equipment and medium, which is applied to a mainboard provided with a first processor, a second processor and independent power supply modules of the first processor and the second processor. The method acquires a transaction layer data packet sequence on a processor bus interface, extracts time sequence characteristics of a transaction type and a queue depth, inputs a trained prediction model, and generates a future load prediction curve for the second processor. When it is determined that the second power supply module is insufficient, a cross-domain scheduling instruction is generated, and within a preset buffer time, the power supply arbitration control unit temporarily schedules part of the power supply capacity of the first power supply module to the power supply path of the second processor, and cancels the scheduling to restore the independent operation after the time window ends. The application realizes dynamic power supply resource borrowing, can effectively cope with transient power impact, and improves the power supply compatibility and stability of the multi-processor platform.

The application belongs to the technical field of device debugging, and relates to a general debugger of a computing device, a debugging system and a debugging method, wherein the debugging method comprises the following steps: a debugging host computer acquires input information and sends the input information to the general debugger; the general debugger performs debugging verification on the input information to determine debugging information; the general debugger selects a bus interface according to a bus type field of the debugging information; the general debugger performs register read and write on the computing device by using the bus interface, and generates debugging result data; and the general debugger acquires the debugging result data and sends the debugging result data to the debugging host computer. The application can independently debug the computing device by using the general debugger; the debugging function can be used to acquire the running condition of a connected device at an interface end of the debugging device; one set of bus interfaces can be used to simultaneously acquire all information of all on-board devices and all machine modules of the computing device, and the application is not limited by different chip address widths and different positions of the chips on the bus.

Systems and methods related to an electronic communications system expansion device. The device includes a control input / output interface, a first bus interface, a second bus interface, and an electronic processor. The processor is configured to, when operating in the expander mode, receive, from a control panel, a first communication according to a first communications protocol at the control input / output interface, and output, from both the first serial communications bus interface and the second serial communications bus interface, the first communication according to a second communications protocol, the second communications protocol being a wired communications protocol. The processor is further configured to, when operating in the extender mode, receive, at the first bus interface, a second communication according to the second communications protocol from a first electronic communications device, and output the second communication according to the second communications protocol to a second electronic communications device via the second bus interface.

The application discloses a self-diagnosis modular lightning arrester state monitoring system, which comprises a sensing module, an extension module, a power supply module, a communication module and a processing module; the sensing module is used for collecting full current signals, surface temperature signals and partial discharge signals of the lightning arrester; the extension module is used for accessing environmental humidity signals and internal pressure signals of the lightning arrester through a controller area network bus interface; the power supply module is used for extracting energy from induced current of a grounding down lead of the lightning arrester to provide electric energy required by system operation; the communication module is used for sending monitoring data to a remote operation and maintenance server; and the processing module is used for receiving various sensor signals, extracting a resistive current component by using a fast Fourier transform algorithm, constructing a three-dimensional feature vector containing a resistive current fundamental component, a partial discharge pulse number and a temperature change rate, and outputting a fault type recognition result through a honeybee algorithm optimization self-adaptive network fuzzy reasoning system classifier.