82 results about "Memory bus" patented technology

The invention relates to a ZNS SSD-based B + tree index construction method for dynamic placement of cold and hot data. A persistent memory PM, a dynamic random access memory DRAM and a ZNS SSD hard disk are included. The persistent memory PM and the dynamic random access memory DRAM are directly connected with a CPU memory bus and have the capability of being accessed by the CPU according to bytes; internal nodes of the B + tree are stored in a dynamic random access memory (DRAM), and the internal nodes only store index information used for positioning leaf nodes; the pseudo leaf nodes of the B + tree are stored in a persistent memory PM, and only the key index information of the leaf nodes is stored in the pseudo leaf nodes; leaf nodes really storing the key value pairs in the B + tree are divided into hot leaf nodes and cold leaf nodes according to the data access frequency, the hot leaf nodes are stored in a persistent memory PM, and the cold leaf nodes are stored in a ZNS SSD. According to the method, the leaf nodes are quickly positioned by using the DRAM, so that the query time is shortened; hot leaf nodes are stored in the PM, and the real-time service read-write requirement is met; and hot data is stored in a high-speed DRAM and PM, so that the random read-write delay is reduced, and the performance is excellent in scenes such as big data analysis and the like.

The invention belongs to the field of chip design, and provides a packet bus interconnection architecture of an SoC system, which comprises a system bus matrix SYSBUSMatrix, at least one processor bus matrix CBM, at least one high-speed peripheral bus matrix HPBM, at least one memory bus matrix RBM and one low-speed peripheral bus matrix SPBM, the CBM, the HPBM, the RBM and the SPBM are all connected with the SYSBUSMatrix through a bus bridge; the embedded processor is mounted on the CBM, and meanwhile, the CBM is connected with the RMB; a high-speed peripheral is mounted on the HPBM, and meanwhile, the HPBM is connected with the RMB; a random access memory (RAM) is mounted on the RBM, and meanwhile, the RBM is connected with the CBM and the HPBM; the SPBM is connected with a plurality of paths of AHB buses through an AXI-AHB bridge, the SPBM is connected with a plurality of paths of APB buses through an AXI-APB bridge, meanwhile, the SPBM is connected with SYSBUSMatrix, and a plurality of paths of low-speed peripherals are mounted on the AHB buses or the APB buses. According to the method, bus transmission among modules such as a processor, a high-speed peripheral and a storage can be balanced, bus competition among high-speed interfaces is effectively reduced, data transmission efficiency is improved, chip rear-end implementation is simplified, and therefore the performance of the whole SOC is optimized.

The embodiment of the invention provides a memory testing system and method, and relates to the technical field of embedded system hardware manufacturing. According to the memory test system disclosed by the invention, the physical layer interface of the memory controller is calibrated, the input / output interface of the memory bus is trained, and the optimized parameters are generated, so that the memory data of the memory unit (including memory particles) can be collected under the optimal condition corresponding to the optimized parameters. And then, carrying out a pressure test on the storage unit based on the optimized parameters, and recording fault information and abnormal information of the storage unit according to a pressure test result. Therefore, the memory test system provided by the invention not only can cover the test of the memory particles, but also can cover the test of the memory controller, and can ensure the stability and reliability of the whole memory unit.

Method and apparatus for detecting in impedance change in a transmission line, such as a line in a computer bus. A CMOS-compatible time domain reflectometer circuit comprising a comparator is embedded in one or more chips and connected to the transmission line. The circuit measures the impedance inhomogeneity pattern (IIP) of the transmission line prior to use, and then repeatedly measures the HP during operation of the transmission line to detect a change in IIP, without Interfering with data transfer through the transmission line. The present invention can detect and locate wire-tapping magnetic probing or snooping, and Trojan and cold boot attacks on interconnecting buses between computer chips or integrated circuits in a computer system, such as on external memory buses.

The present invention provides a system and method for realizing memory and bandwidth expansion by dynamically switching a single shared memory. The system includes: multiple processors, each processor is provided with a memory controller and a serial communication interface, and a high-speed serial data bus is connected between the serial communication interfaces of two adjacent processors; independent memory is mounted on the memory controller of each processor, and the shared memory is connected to the memory controller of each processor through a hardware switching unit, and a memory signal is transmitted between the shared memory and the memory controller of each processor through the memory bus, and the processor sends a control signal to the hardware switching unit to control the hardware switching unit to switch the memory signal. The present invention can utilize the dynamic switching of shared memory to realize the memory expansion of the processor and the communication bandwidth expansion between the processors, optimize and improve the performance of different task stages of the system, thereby improving the calculation processing and high-speed data transmission performance of the optimized system.

Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.

Provided is a memory resource sharing system including a first memory, a first memory subsystem configured to identify and distribute resources of the first memory and to control data transmission of the first memory, and a first processor unit including a first processor connected to the first memory subsystem, a second memory, a second memory subsystem configured to identify and distribute resources of the second memory and to control data transmission of the second memory, and a second processor unit including a second processor connected to the second memory subsystem, wherein the first memory subsystem and the second memory subsystem are communicatively connected to each other through a memory bus.

The invention provides a real-time monitoring and root cause positioning method and system for software defects. The method comprises the following steps: collecting real-time monitoring data of a software processing thread, and generating a thread competition thermodynamic diagram for identifying a shared resource contention point through time sequence association processing; triggering a server memory bus embedded hardware detection device based on a contention point to dynamically capture a locking state transition signal, and converting the locking state transition signal into a locking event sequence; constructing a locking contention track diagram according to timestamp sorting, and completely displaying a process path of a locking mechanism from obtaining to releasing; constructing a dependency topological structure of the thread and the lock based on the trajectory graph, and identifying a resource contention chain; and mapping the contention chain into an unsynchronized shared variable access path in the source code, and triggering a real-time alarm signal. According to the method, the access path of the unsynchronized shared variable is accurately positioned, the lock competition diagnosis efficiency is improved, and the system deadlock risk is zeroed.

The invention discloses a high-speed snapshot system and method, and relates to the technical field of image acquisition. The system comprises a trigger detection module, an image acquisition module, a processing and control module, a DDR cache chip and a storage and transmission module. The image acquisition module adopts a high-speed CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor and works in a high-frame-rate mode which is not lower than 120 frames per second under a preset resolution ratio; the processing and control module adopts a system-level chip integrated with an image signal processor and a hardware encoder; the DDR cache chip is connected with the processing and control module through a memory bus and serves as a high-speed data buffer pool. Through cooperative work of a high-frame-rate sensor and a hardware-level encoder and cooperation of independent DDR cache, clear, continuous and frame-loss-free snapshot of high-speed moving targets such as flying insects is realized, and the problems of image blurring and incomplete data caused by insufficient frame rate and limited data processing capability in the prior art are solved. The system is high in integration level, flexible in deployment and suitable for field monitoring and laboratory research.

This document describes technology for a runtime memory system that utilizes unpredictable multiplexing of memory bus lines. The technology dynamically reassigns data and / or address bus connections between a processor and its runtime memory during warm reset operations. The bus line assignments are made through a multiplexing mechanism—for example, data bus line 01 from the processor may be reassigned to link with bus line 23 at the runtime memory system interface. When a warm reset occurs, the physical mapping of memory locations changes due to this bus line reassignment. The system maintains standard memory operations while implementing this dynamic bus line configuration. Malicious software relying upon memory-resident exploit becomes inoperable after warm reset due to the changed physical memory topology created by the bus line reassignment process.

The invention discloses a universal control module, which belongs to the technical field of industrial field control and comprises a Loongson 2K0300 processor, a DDR4 (Double Data Rate 4) memory bus, a CAN (Controller Area Network) bus interface, a network PHY (Physical Layer) chip, an Ethernet interface, an Ethercat slave station interface, an Ethercat controller, a network transformer, an RS232 transceiver, a transceiver LTM2881 and an LCD (Liquid Crystal Display) interface. The Loongson 2K0300 processor comprises a memory controller, a CAN controller, an Ethernet controller and a UART controller. And the network PHY chip is connected with the Ethernet interface. And the Loongson 2K0300 processor, the Ethercat controller, the network transformer and the Ethercat slave station interface are sequentially communicated with one another. And the UART controller is communicated with the RS232 transceiver. And the UART controller is connected with the transceiver LTM2881 through a pin 1 and a pin 2 of the UART. The universal control module provided by the invention not only can be used as a subsystem single machine to realize corresponding functions in a relatively complex comprehensive control system, but also can independently realize the goal of comprehensive control of the system in small and medium-sized control systems, and realizes the balance of cost and power consumption and the high-efficiency cost ratio of simplicity and easiness in use.

An accelerator system includes an off-chip memory, a bus, and an accelerator. The off-chip memory includes a first buffer. The accelerator includes a second buffer, a third buffer, a fourth buffer, an instruction fetching module, a load module, a storage module, a convolution control module, and a computation module. The instruction fetching module fetches instructions from the off-chip memory via the bus. The load module loads input data from the off-chip memory via the bus. The storage module stores the output data to the off-chip memory via the bus. The computation module performs convolution computations based on the input map and multiple kernels allocated by the convolution module. In response to loading the input data or instruction from the off-chip memory, the requested input data or instruction is transferred from the off-chip memory and temporarily stored in the first buffer.

Embodiments of the present invention provide a memory bandwidth balancing method, a host machine, an electronic device, and a storage medium. The memory bandwidth balancing method comprises: determining memory bandwidth requirements of a plurality of virtual machines for at least one processing unit, different processing units performing memory access by means of different memory buses; and scheduling each virtual machine to a corresponding processing unit among the at least one processing unit in a balanced manner, so that the memory bandwidth occupied by the virtual machine on the memory bus of the corresponding processing unit matches the memory bandwidth requirement of the virtual machine. The solution of the embodiments of the present invention improves the reliability of memory bandwidth allocation, improves the operation performance of the virtual machines, and improves the experience of virtual machine tenants.

An integrated circuit includes a memory bus coupled to a random access memory (RAM). A plurality of ports enable hardware logic to access the RAM over the memory bus. A central processing unit (CPU) is coupled to the memory bus. A first hardware logic module is coupled to a first port, of the plurality of ports, to share access to the memory bus with the CPU. A plurality of hardware registers, coupled to the plurality of ports, include a first hardware register to store a number of accesses, by the first hardware logic module, to the memory bus over the first port.

The application relates to a B+ tree index construction method based on ZNS SSD cold and hot data dynamic placement, which comprises a persistent memory PM, a dynamic random access memory DRAM and a ZNS SSD hard disk; the persistent memory PM and the dynamic random access memory DRAM are directly connected with a CPU memory bus and have the ability of being accessed by the CPU by bytes; internal nodes of the B+ tree are stored in the dynamic random access memory DRAM, wherein the internal nodes only store index information for positioning leaf nodes; pseudo leaf nodes of the B+ tree are stored in the persistent memory PM, wherein the pseudo leaf nodes only store key index information of the leaf nodes; leaf nodes for actually storing key value pairs in the B+ tree are divided into hot leaf nodes and cold leaf nodes according to data access frequencies, wherein the hot leaf nodes are stored in the persistent memory PM, and the cold leaf nodes are stored in the ZNS SSD hard disk. The application utilizes the DRAM to quickly position the leaf nodes, reduces query time, stores the hot leaf nodes in the PM to meet real-time business read-write requirements, stores the hot data in the high-speed DRAM and the PM, reduces random read-write delay and performs well in big data analysis and other scenes.

The application provides a UCIe-based debugging information recording method, a storage medium and an artificial intelligence chip. The debugging information recording method comprises the following steps: setting the format of a debugging chain by a direct memory access module; updating the debugging chain by the direct memory access module; and sending the debugging chain to at least one of a memory bus and a control bus by the direct memory access module, wherein the debugging chain comprises a start mark, timestamp register information and an end mark, and further comprises at least one debugging register information or at least one error transmission information. The debugging information recording method, the computer readable storage medium and the artificial intelligence chip can effectively record debugging information.

The invention discloses a polar code decoder based on RISC-V instruction set architecture extension, which is integrated in a communication system, adopts a coprocessor form, is connected with a main processor and a memory through a memory bus, and designs a data cache region to reduce memory access pressure and improve data multiplexing efficiency. The decoder comprises seven sub-modules including an instruction fetching and writing back module, a data carrying module, an f operation module, a g operation module, a basic unit function operation module, an estimation bit operation module and a data cache region, and supports a user-defined RISC-V extension instruction. The invention also discloses a method for carrying out decoding operation on the polarization code serial cancellation (SC) by using the decoder disclosed by the invention.

Detailed herein are embodiments utilizing a cryptographically authenticated address bus (CAAB) protection that uses an intelligent memory design to prevent attacks on the address bus without detection and eliminate the memory bus as an observability surface for an attacker to do access pattern analysis. Embodiments detailed herein describe an intelligent memory module which has cryptographic capabilities. In some embodiments, a memory controller and an intelligent memory module exchange a key and using this key, the address (on the address bus) is encrypted and integrity protected using authenticated counter mode encryption. The memory controller on receiving a read or a write request encrypts the address (e.g., using pre-generated encrypted counters to minimize cryptographic overheads). A message authentication code (MAC) also gets generated along with the encrypted address to be able to detect modification to the encrypted address.

The invention relates to an electronic system (100) comprising: - a controller module (3), with a core (31), peripheral (33) and memory (32) mapped on a memory bus (36), configured for executing instructions, - a supply module (1), with one or more power inputs (11) such as an energy harvester input, one or more power outputs (12) such as a load output, one or more ports (13) for connecting a storage element, configured for of supplying energy to different elements of the system, - a power and energy monitoring module (2), the power and energy monitoring module (2) being coupled to the controller module (3) by a first communication channel, the power and energy monitoring module (2) being coupled to the supply module 1) by a second communication channel. According to the invention, the supply module (1) is configured to collect information on the source, load and / or storage element, and the power and energy monitoring module (2) is configured for further processing the power and energy information received from the supply module and to allow the microcontroller module (3) to modify the order of execution of its instructions as a function of the information collected by the supply module (1).

The application discloses a communication auxiliary system, a master control device and a method, and belongs to the technical field of communication. The system adopts a mediation double-agent architecture, the master control device is logically connected between a communication terminal and a headset device, and meanwhile, isolated physical connections are established by simulating hands-free (HF) device specifications and audio gateway (AG) device specifications. The master control device is internally provided with an uplink data decision module and a memory bus with a first buffer address and a backup buffer address. When a local trigger event (such as touch, action or external entity button pulse) is captured, the decision module forcibly switches the memory data reading pointer of the digital audio by using the bottom-layer hardware atomic operation in an instant, and replaces the headset pickup source with an external high-definition pickup source. The whole switching process does not trigger the bottom-layer audio routing redistribution (Audio Policy) of the communication terminal operating system, and the absolute continuity of the Bluetooth bottom-layer SCO synchronous link frame sequence is maintained. The system realizes the high-response seamless migration and injection of the external pickup source without invading the protocol stack of the host device, supports the double-track solidification of the multi-dimensional voice shunting of the communication link, and significantly improves the communication and pickup efficiency in modern mobile and complex scenarios.

One embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. The processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. The circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.

Multiple examples are disclosed of a multi-port SRAM system for a distributed memory pool and associated methods. In one example, a system comprises a memory bus switch coupled to a plurality of memory buses; a memory pool switch coupled to one or more memory arrays; and one or more SRAM blocks coupled to the memory bus switch and the memory pool switch to convert a first transaction received on one of the plurality of memory buses to a second transaction performed on the one or more memory arrays.

To provide a memory device and a system that provide high speed access to a memory in higher temperature applications.SOLUTION: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; and for each received command, determining if the command is an express read (NVR) command, determining if a next consecutive command is a NVR command, in which consecutive NVR commands form a NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells; and driving the read data on parallel data input / outputs (I / Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock.SELECTED DRAWING: Figure 16

The application discloses a kind of virtual machine vcpu hanging death detection method under cloud computing scenario, belong to cloud computing field, and its specific include: in the back end of VMM, MMIO region is created to carry out memory mapping, by increasing configuration file, so that VMM is identified to the region, carries out I / O hardware abstraction, and registers device on memory bus using device tree mode, provides memory region to virtual machine, starts internal clock, calculates internal clock decrement time, and adjusts internal clock according to extracted guest time, uses misc device, starts high-precision timer and periodically sends heartbeat message, after sending, virtual machine enters VMM, and judges vcpu state by VMM, registers CPU hot plug mechanism, ensures that the vcpu of suspended state is offline and enters deadlock state, can quickly analyze virtual machine run dead problem and quickly locate fault.

A computing system including: a processing device; a main memory; a memory bus (e.g., a double date rate (DDR) bus) coupled between the processing device and the main memory; a random access memory; and a compute express link (CXL) fabric coupled between the processing device and the random access memory. The system is configured to identify a ratio, using a reinforcement learning technique, to manage distribution of memory usage across the main memory and the random access memory. For example, the system can measure performance metrics of the computing system as a result of the managing according to the ratio, and update, based on the performance metrics, a reward model configured to identify a ratio for a given state of the computing system to manage memory for maximized reward.

A memory interface for interfacing between a memory bus and a cache memory. A plurality of bus interfaces are configured to transfer data between the memory bus and the cache memory, and a plurality of snoop processors are configured to receive snoop requests from the memory bus. Each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.

The embodiment of the invention provides a floating-point number processing method, a floating-point number processing device, electronic equipment and a storage medium, and the floating-point number processing method applied to a coprocessor comprises the steps that a floating-point addition operation instruction is received, the floating-point addition operation instruction comprises an accumulated value and a memory address, and the accumulated value is used for floating-point addition operation; a first operand is obtained, and the first operand is a numerical value stored in the memory address; performing floating point addition operation according to the first operand and the accumulated value to obtain a second operand; generating a comparison and exchange request according to the first operand, the second operand and the memory address, and sending the comparison and exchange request to the main processor; and in response to a processing result of the comparison and exchange request received from the main processor, determining whether the floating point add operation instruction is executed or not. According to the method, the memory bus is prevented from being occupied, the main processor can be prevented from falling into circulation, and the execution overhead of the main processor is reduced.

A system having: a compute express link fabric; a plurality of memory devices having random access memory cells, a memory bus; a main memory; at least one processing device connected to the main memory via the memory bus, and connected to the compute express link fabric; a peripheral bus; and a plurality of memory sub-systems connected to the at least one processing device via the peripheral bus. A plurality of portions of the random access memory cells in the plurality of memory devices are allocated respectively as a plurality of host memory buffers for the plurality of memory sub-systems. Each memory buffer can have random access memory cells allocated from more than one of the memory devices.

Systems, methods, and apparatus are described for accelerating access to borrowed memory via a network connection. For example, a memory management unit (MMU) of a computing device can be configured to connect to both random access memory via a memory bus and to a computer network via a communication device. The computing device can borrow an amount of memory from a remote device via a network connection using the communication device; and an application running in the computing device can use virtual memory addresses mapped to the borrowed memory. When a virtual address mapped to the borrowed memory is used, the MMU translates the virtual address to a physical address and instructs the communication device to access the borrowed memory.

Hardware-based training is described for synchronous dynamic random-access memory. In one aspect a memory includes a memory physical interface (PHY) of the memory coupled to a memory bus and configured to receive a received Pseudo-Random Binary Sequence (PRBS) through the memory bus at from a host PHY. A PRBS generator is configured to generate a generated PRBS and compare logic is configured to generate a score based on comparing the received PRBS to the generated PRBS. The memory PHY is further configured to send the score to the host PHY.