179 results about "Host adapter" patented technology

A Universal Serial Bus (USB) adaptor (16, 16', 16''), compatible with standard USB connectors, provides a simplified interface between a portable communications device (12) and a USB accessory (14, 14''). An encoder (28) provides an operating state to the portable communications device (12), enabling the portable communications device (12) to perform as either a USB host or a USB function accessory. A function adaptor (16') selects its DC power source and is capable of providing DC power to a function accessory (14'). The host adaptor (16) can obtain DC power from a host accessory (14), according to USB standards.

A method and host bus adapter for controlling failover and failback processes within a redundant data storage system. The method is carried out by a failover mechanism in a host bus adapter linked to a host server. The system includes a communication fabric providing data paths to pairs of redundant storage controllers managing access to storage devices (such as hard disk drives arranged as RAID). The method includes operating the host bus adapter to detect a failover condition and in response, to match the failover condition to a particular failover action. The failover conditions and corresponding actions are stored in a well-defined rule set accessed by the host bus adapter. The method continues with performing with the host bus adapter the matched failover action. The method is transparent to the host computer device, as the host is not required to participate in the failover processes.

A multi-port adapter having a single MAC chip has reduced logic circuits for transferring data between a host system and a TDM communication system. The MAC chip includes a transmit MAC and a receive MAC, each coupled at one end to a port multiplexer through an interface and at the other end to respective storage registers. The port multiplexer is coupled to the Physical Layer of each port. Transmit and receive state registers track the state of each port in the transfer of data in the transmit and receive directions. The storage registers are coupled through a host bus interface to a host bus and to the host system. Control logic is coupled to the storage register to control the transfer of data between the system and the storage registers. A port selector coupled between the multiplexer and the transmit and receive state registers selects ports for transfer of data in succession. On each chip clock cycle, the port selector selects a state machine register to determine the state of the MACs for processing the data and a section of the FIFO's to write or read data for the selected port. At the end of the cycle, the state registers are set and stay set until selected again. The process repeats for each port in a cyclic manner. Once data is accumulated in the receive storage register, control logic reads the data of the host bus. Once space is available in the transmit storage register, the control logic writes data from the host system to the transmit storage register.

A headset having a built-in memory to store parameter settings relating to headset performance characteristics such as headphone(s) and/or microphone performance characteristics. The performance characteristics can be measured during headset production and stored in the memory. A host adapter may communicate with the headset through a serial communications port of the headset. The host adapter may read the headset performance characteristics and adjust signals transmitted to and received from the headset in accordance thereto. When the headset is used in a system, the system parameters can be manually set and stored in the headset memory. When the headset is used again in the same system, the system parameters can be read from the memory and automatically set. The memory may also store product history information of the headset such as production date, serial and model numbers, and/or any service history.

Architecture that integrates an unmanaged application as a hosted application into a design environment in a coherent yet usable manner such that the developer can use the hosted application's native functionality yet leverage rich productivity features provided by the IDE. The IDE includes a hosting component that comprises an application adaptor for providing an interface from the unmanaged application to the IDE. The IDE further includes a designer framework that provides user access to designer capabilities of the IDE. The host adaptor interfaces to the designer framework either directly and/or through an integration interface. Thus, the developer/user can then access the native functionality of the unmanaged application as well as the IDE functionality. This provides rich integration between the development environment and the hosted application, the end result of which is the designer interacting with the IDE.

A Flash memory card system is disclosed. The Flash memory card system comprises a Flash memory wireless host adapter and a Flash memory bus wireless device. The Flash memory wireless host adapter comprises a Flash memory card connector and a Flash memory controller coupled to the Flash memory card connector. The Flash-52 memory card signals are converted to standard Flash memory internal bus signals by the Flash memory controller. The host adapter further comprises a Flash memory wireless module coupled to the Flash memory controller for receiving and transmitting the standard Flash memory bus signals wirelessly. The Flash-51 memory bus wireless device comprises a Flash memory bus wireless device adapter coupled to a Flash memory. The device adapter is paired to the wireless module for receiving and transmitting the standard Flash memory bus signals wirelessly. A host device storage capacity utilizing the Flash memory card system is expanded.

A host adaptor is configured to monitor operation of an optoelectronic transceiver. The host adapter includes a transceiver interface, memory, comparison logic and a host interface. The transceiver interface receives from the optoelectronic transceiver digital values corresponding to operating conditions of the optoelectronic transceiver. The memory includes one or more memory arrays for storing information related to the optoelectronic transceiver, including the digital values received from the optoelectronic transceiver. The comparison logic is configured to compare the digital values with limit values to generate flag values, wherein the flag values are stored in predefined flag storage locations within the memory during operation of the optoelectronic transceiver. The host interface enables a host device to read from host specified locations within the memory, including the predefined flag storage locations, in accordance with commands received from the host device.

A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.

An adapter unit operative to support access of an SATA storage device by a plurality of hosts associated with separate host adapters. The adapter unit includes a multiplexer coupled to an arbiter. The multiplexer receives a plurality of sets of communication signals, one signal set for each host adapter. The multiplexer then selects one of the signal sets based on a control signal and couples the selected signal set to its output. The arbiter receives requests from the hosts to access the SATA storage device, selects a particular requesting host, and provides the control signal indicative of the specific host granted access. The host adapter for the granted host and the SATA storage device are placed in a PHY READY power management state, prior to a read or write access, and are placed in a PARTIAL power management state after the read or write access.

A method and apparatus for assuring data consistency during certain operations involving dependent input/output sequences. During such operations a stall application blocks write operations to specified logical devices in a local consistency group while allowing read operations to all devices and write operations to non-specified logical devices. When a write command is directed to a logical device in local consistency group, the host adapter associated with the logical device returns a message to the host that initiates a write command retry. Retries generally continue until a write command is successful.

A system and method of booking an itinerary on at least one of a multiplicity of host environments include a plurality of host adaptor modules. Each host adaptor module is configured to interact with one of the plurality of host ticketing environments. A booking engine is provided for receiving commands related to booking the air travel itinerary and determining an appropriate host ticketing environment for processing the commands based on a number of predefined criteria. When the booking engine receives a command it forwards the command to a first host adaptor module which is associated with first host ticketing environment selected by the booking engine for processing the command. The host adaptor module receives the command and issues the command to said first host ticketing environment. The first host adaptor module in turn receives a response from the first host ticketing environment and determines whether the response comports with an expected response. If the response does not comport with the expected response, the booking engine identifies a second appropriate host environment for processing the command and forwards the command to a second host adaptor module associated with the second host ticketing environment. The second host adaptor module then issues the command to the second host ticketing environment.

A device is disclosed that allows a host device that is the source of data transfer to detect whether or not data have been correctly written to a memory device without interfering with the effective data transfer. When the host device issues a request to write sector data, a host adapter deblocks the sector data into data blocks and transfers the data in data block units to a memory adapter. The memory adapter not only memory-writes the data blocks to a memory device, but also generates block CRC code from the data blocks and returns the code as a write reply to the host adapter. The host adapter receives the block CRC code, carries out a CRC operation to reconstruct CRC code of complete sector data, performs a correspondence check with the CRC code of the original sector data, and reports the check results to the host device.

A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

An apparatus for providing a low cost, quick, and convenient automobile jump starting system and method. The jump start system comprises an adapter suitable to receive at least one hand held power tool battery. The adapter in certain embodiments comprises conductive metallic spring clips for making electrical connection(s) between the tool battery and the adapter. The adapter further comprises a plurality of connectible gauge wires (serving as booster cables) each having biasing connectors (alligator clips). The distal ends of the gauge wire(s) may be removably connectible to the adapter or may be rigidly fixed to the adapter. The Jump Start Adapter System may also be removably connected to the vehicle battery using biasing connectors or may be hard wired to the vehicle electrical system eliminating the need for biasing connectors. The proximate end(s) of the connectible gauge wire(s) comprise the biasing connectors for making connection to the dead battery of the vehicle when using a free-standing jump start adapter system. One of the connectible gauge wires is a red color-coded eight-gauge wire serving as a positive cable and the other connectible gauge wires is a black color-coded eight-gauge wire serving as a negative cable. The Jump Start Adapter system of the present invention allows individuals to jump-start various types of vehicle engines using a rechargeable battery from a power tool battery.

A method and apparatus for enabling a magnetic disk storage device that stores data according to a first data structure characterized by a fixed-length disk block size to respond to input/output requests from a host that define data according to a different data structure characterized by a different fixed-length host block size. A host adapter transfers requests and data between the host and a cache memory in the magnetic disk storage device as host blocks. A disk adapter transfers requests and data between the cache memory and magnetic disks as disk blocks. CRC data and a sector number are appended to each host block in a set of disk blocks.

A remote control system and a method thereof are provided. The remote control system includes a first host, an adapter, and a peripheral device. The first host converts a first serial signal into a first network packet, and then outputs the first network packet through a network. The adapter is connected to the network to receive the first network packet, and then converts the first network packet into a second serial signal complying with a universal serial bus (USB) format. The peripheral device is coupled to the adapter through the USB, and receives the second serial signal, so that the user can control the peripheral device at a remote site through the network.

The invention discloses a fiber channel-based general automatic test system, and belongs to the field of automatic test. The system comprises an automatic test system and an automatic test system network. The test system consists of automatic test equipment, a test adapter, a switching network, an extended resource module and a tested unit; and detection and analysis of the tested unit are realized together. The test system network consists of a local automatic test system and a non-local automatic test system network and realizes networked test system function. The system makes full use of two properties of a fiber channel, namely input/output (I/O) channel technology and network technology. The high-speed storage performance of the I/O channel technology is used as an internal communication protocol of the automatic test system, the network performance is used as a transmission protocol of the test system network, the structure of the traditional automatic test system is accommodated under the condition that the system construction is not changed, and good compatibility is realized.

A multi-host host bus adapter (HBA) can be connected to multiple host devices to allow the multiple host devices to communicate on a SAN fabric. More specifically, the multi-host HBA provides an interface for multiple SAN hosts without necessitating an HBA on each host, eliminating the need for an on-board HBA on each SAN host. The multi-host HBA interfaces to memory in each SAN host to which it is connected using PCI-Express (or a similar protocol), and communicates with other devices on the SAN fabric using Fibre Channel ports. The multi-host HBA communicates by receiving a command from a connected host, forwarding the command to a processor in the multi-host HBA, and sending the command to a device on a SAN. When the multi-host HBA receives a response from the device on the SAN, the multi-host HBA associates the response with the process and sends the response to the host.

In a data storage subsystem with disk storage and a pair of clusters, one set of DASD fast write data is in cache of one cluster and in non-volatile data storage of the other. In response to a failover of one of the pair of clusters to a local cluster, the local cluster converts the DASD fast write data in local cache to converted fast write data to prioritize the converted data for destaging to disk storage. In response to failure to destage, the local cluster allocates local non-volatile storage tracks and emulates a host adapter to store the converted fast write data by the local non-volatile storage, reconverting the converted fast write data of the non-volatile storage to local DASD fast write data stored in the local non-volatile storage and stored in the local cache storage.