75 results about "Datapath" patented technology

A scalable chiplet-based system for integrated electronic control within a vehicle comprises several central chiplets (220-223), with each central chiplet (220-223) being disposed along a substantially central axis of a substrate (200) for housing the central chiplets (220-223). Several systems on chip (230-237) perform vehicle operations of the vehicle, wherein each of the systems on chip (230-237) communicate with one of the central chiplets (220-223) through a respective die to die interconnect, and each die to die interconnect includes one or more main data paths and one or more side data paths. A chip to chip interconnect (225-229) is between each of the central chiplets (220-223) through which the central chiplets (220-223) communicate.

This application discloses a method, apparatus, electronic device, and storage medium for splitting a storage cluster, relating to the field of computer technology, particularly to artificial intelligence fields such as cloud computing, distributed storage, and big data processing. The specific implementation scheme is as follows: The data path of the target resource in the original storage cluster is adjusted so that requests to access the target resource are sent to the target node in the original storage cluster; the target node is network isolated; the target node is restarted, and in response to the target node's target startup parameter being set to the target value, the target node is split from the original storage cluster as a new storage cluster; wherein, the target startup parameter is a parameter used to force a node to start as a new single-node cluster; the target node is removed from the original storage cluster, and the network isolation of the target node is lifted.

The present disclosure relates to accelerating table lookups using decoupled lookup table accelerators in a system on a chip. In various examples, a VPU and associated components can be optimized to improve VPU performance and throughput. For example, the VPU can include a min / max collector, an auto store prediction function, a SIMD data path organization that allows inter-lane sharing, a transpose load / store with stride parameter function, a load with permute and zero insertion function, a hardware, logic, and memory layout function to allow two-point and two-point by one lookups, and a per memory bank load cache function. Further, a decoupled accelerator can be used to offload VPU processing tasks to improve throughput and performance, and a hardware sequencer can be included in a DMA system to reduce programming complexity of the VPU and DMA system. The DMA and VPU can perform a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

In an electronic device and an operating method thereof according to an embodiment, the electronic device may include a communication circuitry supporting short-range wireless communication and neighbor awareness network (NAN) communication; a memory storing at least one computer program; and at least one processor. The at least one computer program may include instructions that cause, when executed by the at least one processor individually or collectively, the electronic device to connect to a first access point (AP) through a non-dynamic frequency selection (non-DFS) channel, transmit, to an external electronic device, a first service discovery frame including information related to a DFS channel and information indicating a maximum bandwidth supportable by the electronic device, in a process of discovering the external electronic device to be connected via an NAN data path (NDP), connect to a second AP supporting the DFS through the DFS channel while maintaining a connection between the first AP and the electronic device, upon identifying, based on a second service discovery frame received from the external electronic device, that the external electronic device supports the DFS and a maximum bandwidth supportable by the external electronic device is greater than a bandwidth of the non-DFS channel, establish the NDP with the external electronic device, based on the first service discovery frame and / or the second service discovery frame, and perform NAN communication with the external electronic device, based on first schedule information related to performing the NAN communication through a frequency band of the non-DFS channel and a frequency band of the DFS channel. The first schedule information may enable the external electronic device and the electronic device to perform the NAN communication through the frequency band of the non-DFS channel and the frequency band of the DFS channel during a first period between discovery windows.

A system and method of processing Automotive Ethernet and High-Speed Ethernet signals. The method includes forming a first data path according to a first transmission protocol and a second data path according to a second transmission protocol. The method includes selecting the first data path to receive a first bitstream compliant with the first transmission protocol at a first data rate. The method includes encoding the first bitstream using a first encoding scheme to produce a first encoded bitstream. The method includes upsampling the first encoded bitstream to produce an upsampled bitstream at a different data rate. The upsampled bitstream aligns with transmission requirements of a Physical Medium Attachment (PMA) device. The method includes forwarding the upsampled bitstream to the PMA device.

A neural processing unit (NPU) may perform computations in integer domains to execute a floating-point model. The NPU may include an input delivery unit (IDU), a processing engine, and a post-processing engine. The IDU may convert floating-point weights to integers, e.g., by normalizing the floating-point weights, mapping the normalized floating-point values to normalized integer values using a look-up table, and scaling up the normalized integer values into integer values. The IDU may load the integer values into the processing engine through an integer datapath in the NPU. The processing engine may compute an output tensor of a neural network operation using the integer values. The post-processing engine may perform per-channel quantization of the output tensor using channel-specific quantization parameters stored in configuration registers of the post-processing engine. The look-up table and configuration registers may be programmed with configuration parameters determined by a compiler.

The present invention relates to a decentralized arbitration crossbar network. In the crossbar network of the present invention, arbitration units are not designed to configure data paths between circuits. In the crossbar network of the present invention, a data path can be established after a three-way handshake between two circuits.

Aspects of the disclosure are directed to dynamic power management. In accordance with one aspect, the disclosure includes determining a system state using real-time monitoring of a plurality of input / output (IO) rings; transitioning a subset of a plurality of processing engines to an offline state to decrease from a quantity of the plurality of processing engines in an active power state to a remaining quantity; determining if a software-based data plane is required in the plurality of processing engines that remain in the active power state; and transitioning a data path hardware mode and a plurality of packet data flows for the remaining quantity.

This invention discloses a non-intrusive master station monitoring information acceptance method and system based on real-time data slice analysis, belonging to the field of power system monitoring technology. This invention securely obtains equipment and point number information sequences by parsing master station slice files; establishes a standardized point number mapping table through cluster analysis; uses this table to associate master and substation data, forming aligned numerical description pairs; then performs a two-dimensional intelligent comparison of numerical differences and text similarity to identify configuration misalignments and inconsistencies in hidden descriptions, generating enhanced verification records; finally, it constructs a tamper-proof full-link traceability log and closed-loop verification result report, and adaptively optimizes mapping rules and data paths based on report feedback. This achieves a fundamental transformation in monitoring information acceptance from manual verification to automatic diagnosis, and from single operations to continuous optimization, significantly improving the security, accuracy, and intelligence level of the acceptance process.

This application provides a data exchange out-of-order suppression method and electronic device, belonging to the field of switch technology. This method can suppress out-of-order data exchange at each level of a switching system. The data exchange out-of-order suppression method provided in this application can be applied to multi-level switching systems. The method includes: a first scheduler transmitting first dequeue information to the data path; the first dequeue information includes a request number that the first scheduler dequeues from a waiting request queue; each request in the request queue carries a request number; the request number is used to identify the source and / or service from which each request originates, and requests from the same source or service carry the same request number; controlling the closure of a first switch among multiple first switches corresponding to the request number in the first dequeue information, and a second scheduler scheduling the dequeue of the request corresponding to the closed first switch.

A processor for executing neural network inference includes a CPU, weight and state memory, and a fabric comprising a plurality of programming elements. Each programming element comprises an ALU, having a controller and a core, and a sequencer configured to receive a sequencer program comprising at least one sequencer instruction, the at least one sequencer instruction comprising a compressed representation of one or more arithmetic ALU op codes; decompress the sequence instruction to produce the one or more ALU op codes; and provide the one or more ALU op codes thus produced to the ALU controller. The ALU controller is configured to output a control signal to configure a data path of the ALU for executing one or more operations in performing inference, for each op code received from the sequencer. The CPU controls execution of sequencer programs by the plurality of programming elements.

This invention discloses a method, apparatus, server, storage medium, and program product for managing virtual functional devices. The method is applied to a virtual data path acceleration server, which runs on a server equipped with a data processor card. The data processor card provides physical functional devices, each corresponding to at least two virtual functional devices. A one-to-one correspondence exists between one of the virtual functional devices and the virtual data path acceleration server. The method includes: receiving a virtual functional device management request; and, in response to the virtual functional device management request, managing the virtual functional devices represented by the one-to-one correspondence. The technical solution of this invention ensures that only one virtual functional device is affected in the event of a crash or / or upgrade of the virtual data path acceleration server.

An integrated circuit and associated method of operation are provided for a target component coupled over a bus having multiple data path lines and a clock path line to an initiator component which generates a plurality of data bit signals and a first clock timing signal for transmission in parallel over the bus, where the initiator component includes transmit circuitry to launch a first plurality of even data bit signals over a first subset of the plurality of data path lines in response to a rising clock edge of the first clock signal and to launch a second plurality of odd data bit signals over a second subset of the plurality of data path lines in response to a falling clock edge of the first clock signal.

An FPGA-oriented DSP placement optimization method for CNN accelerators includes the following steps: S1. DSP path information extraction: converting a designed netlist into a graph representation, and carrying out data-path DSP node identification and data-path DSP graph building; and S2. datapath-driven DSP placement: distributing data-path DSP nodes to specific positions on an FPGA according to an extracted data-path DSP graph. According to the invention, automated extraction and building of data-path DSP graphs are carried out by means of graph neural network (GCN)-based DSP node classification and min-cost flow (MCF) model optimization algorithms, and compact placement and cascade constraint optimization are used in combination, thereby greatly improving the timing performance and computing efficiency of the placement and also significantly improving the clock frequency and throughput. Therefore, the method provides a universal and efficient FPGA placement solution for multiple CNN accelerator architectures.

The application provides a unified metadata layer hybrid storage method and system, the method comprises receiving a storage access request of each node, parsing the protocol type and the target data path corresponding to the request; based on the preset directory table, the index node table and the object table, the metadata operation corresponding to the protocol type is executed; the metadata operation is encapsulated as an atomic transaction submission, and the corresponding records of the directory table, the index node table and the object table are synchronously updated, and the read and write operations of the target data are completed. The application not only solves the problems of semantic fragmentation, poor consistency and performance bottleneck existing in the traditional hybrid storage system for a long time, but also solves the problems of resource contention, business insecurity and poor cluster stability in the multi-training task parallel scene according to the special needs of the AI large model training scene.

An integrated circuit and associated method of operation are provided for a target component coupled over a bus having multiple data path lines and a clock path line to an initiator component which generates a plurality of data bit signals and a first clock timing signal for transmission in parallel over the bus, where the initiator component includes transmit circuitry to launch a first plurality of even data bit signals over a first subset of the plurality of data path lines in response to a rising clock edge of the first clock signal and to launch a second plurality of odd data bit signals over a second subset of the plurality of data path lines in response to a falling clock edge of the first clock signal.

A Software Defined Storage (SDS) system includes a memory system, an SDS client subsystem that is coupled to the memory system, and an SDS server subsystem that is coupled to the memory system. The SDS server subsystem establishes a first Transmission Control Protocol / Internet Protocol (TCP / IP) connection with the SDS client subsystem, and determines that the SDS client subsystem and the SDS server subsystem share the memory system. The SDS server subsystem then receives a first data read request via the first TCP / IP connection from the SDS client subsystem, determines the first data read request is associated with data stored in the memory system, and provides a first data read response via the first TCP / IP connection, that is configured to cause the SDS client subsystem to read the data from the memory system.

The present inventors devised techniques and technologies that streamline the protection of data stored on shared file storage e.g., on file servers, network-attached storage (NAS), share drives, network shares, etc., in a data storage management system. Some embodiments feature a proxy-less backup configuration in which backup services hosts are assigned to perform a secondary copy job, at job runtime, based on host attributes relative to the data source. Some embodiments are configured to, at job runtime, automatically resolve data paths to the source data, and automatically mount the data paths, rather than requiring data paths to be expressly pre-administered on all possible candidate backup machines. Some embodiments automatically protect data from shared file storage that was not expressly given a backup plan (“undefined” data) by applying default preferences for protecting undefined data.

This invention describes an integrated circuit and a method for designing an integrated circuit including error detection and correction circuitry. The integrated circuit includes a data path arranged between the output of a first register timed by a system clock and a second register. The integrated circuit includes timing error detection and correction circuitry (EDAC) having a clock unit configured to receive a reference clock and provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to corresponding nodes on the data path and error detection circuitry coupled to each transition detector. During design, the nodes are selected according to a desired timing window to be monitored. If a transition occurs during a snapshot of a time period between a transition corresponding to the reference clock and a corresponding transition of the delayed reference clock, the error detection circuitry flags an error. The timing correction circuitry coupled to the error detection circuitry outputs the system clock derived from the delayed reference clock.

Proxy-less connectivity may be established between logically isolated networks, such as virtual private clouds (VPCs), within a cloud environment using port based routing over a data path. When a consumer network is coupled to a producer network via a data path, each unique consumer transport layer port in the consumer network may be mapped to a unique producer transport layer port in the producer network, such that all ports in the consumer network are exposed on a single IP address which maps to different IP addresses in the producer network. In this regard, data from any port in the consumer network is transmitted through the single IP address and over the data path to a specific port in the producer network.

Systems and methods are provided for implementing mobile connectivity device wake detection and diagnosis. After detecting that a mobile connectivity device on a device has been awakened, an operating system (“OS”) control message support driver running on an OS determines a cause of awakening of the mobile connectivity device. The determined cause of awakening of the mobile connectivity device includes one of a control path reason, a firmware-based reason, a data path reason, or a peripheral component interconnect (“PCI”) bus-based reason. Based on each of these determined causes of awakening of the mobile connectivity device, a corresponding report (e.g., a control path wake reason report, a firmware-based wake reason report, a data path wake reason report, or a PCI bus-based wake reason report) is sent for further action (e.g., analysis of the wake reasons for subsequent system updates or patches to address the underlying issues associated with the wake reasons).

The present disclosure relates to flexible programmable processing units. A digital data processing unit comprises an input for receiving input data, an output for providing output data, one or more processing elements, and one or more switches. Each processing element has one or more inputs for receiving input data and one or more outputs for providing output data, and is configured to apply a mathematical operation on its input data during a time slot, thereby generating output data. Each switch has an output and at least one input for receiving a respective input value, and is operated based on control data to provide each received input value to a selected one of its outputs; wherein data paths are formed between the inputs of the processing unit and the outputs of the processing unit, wherein at least one data path is configured to provide, at a corresponding output of the processing unit, a final mathematical result from an intermediate mathematical result generated by one or more processing elements.

The application provides an access control method, system and device, storage medium and computer equipment, adopts RDMA-based QP transmission semantics to define logical conditions of an access control strategy, generates fine-grained access control strategies suitable for two types of paths by defining and distinguishing key semantic fields (such as QP numbers, virtual addresses, etc.) of RDMA messages on control paths and data paths. By converting the access control strategy into specific access control rules and distributing them to the host, fine-grained and accurate access control of the complete RDMA communication behavior of the communication parties from the establishment of the QP connection to the specific memory operation can be realized on the host side, effectively solving the problem of insufficient control accuracy and incomplete coverage caused by the lack of expression semantics in traditional methods, and significantly improving the accuracy of access control of tenant RDMA communication behavior.

Connectors as essential components for transmitting data in communication networks come in different types. Utilizing a common connector capable of transmitting different types of data protocols can save space and energy. A device utilizes a common connector and a detector that detects the data protocol and transmits the data over a proper data path. Thus, smaller devices can be deployed by substituting different connectors by a single common connector. Data which is transmitted from the common connector is passed through a detector logic which detects a protocol associated with the data. The detected protocol is used to determine which data path is a proper data path to transmit the data. Depending on the number of pins of the common connector and the native connector of the receiving device, several methods are used to transmit the data, which ensure the entire data is transmitted via the proper data path.

This application discloses a computing device, system, and method based on memory expansion, relating to the field of computer technology. The device includes: flash memory, a flash memory controller, a data stream processing module, a sub-protocol multiplexing and arbitration module, a protocol controller, memory, and a memory controller. The flash memory stores file data, enabling direct file loading into memory within the computing device. The flash memory controller is connected to the data stream processing module via a data path. The flash memory controller acquires file read or write tasks sent by the host processor and initiates file read or write operations via a memory-mapped bus. The data stream processing module accesses the flash memory through the flash memory controller and / or accesses the memory through the memory controller according to the computing task. This shortens the data exchange path, improves the flexibility of computing tasks on memory data, avoids latency caused by frequent file loading, and improves computing efficiency.

Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.

Aspects of the subject disclosure address the traditional trade-off between performance and area, in relation to circuit and system design, together with power as an additional factor of consideration. Circuits and systems of this disclosure may realize a datapath of data in respect of memory state elements (e.g., registers, flops, etc.) that is dependent on multiple qualifiers. Aspects of this disclosure enhance (e.g., optimize) area and reduce leakage power associated with circuits and systems. Furthermore, aspects of this disclosure enable and enhance an insertion of clock-gating circuits or mechanisms to reduce dynamic-power consumption depending on states of the qualifiers.

A memory device comprises a plurality of backend interfaces that are each configured to connect to a respective media device (e.g., DDR, LPDDR DRAM), a plurality of reliability, availability and serviceability (RAS) channel datapaths with each RAS channel datapath connected to one or more backend interfaces, one or more caches that are each connected to at least one RAS channel datapath, and control circuitry. The control circuitry is configured to: in response to receiving a memory access request for a memory location, search a cache of the one or more caches for the requested memory location; and when, in response to the search, the requested memory location is not found in the cache, obtain the requested memory location from a media device connected to the at least one RAS channel datapath. Corresponding methods are also described.