9 results about "Timing results" patented technology

The present disclosure provides a timing method, device, resource distribution system, computer device and storage medium. The method comprises: in response to a triggered timing event, in each timing period, performing the following process: determining a current target timing duration corresponding to the current timing period; wherein the current target timing duration is determined based on a pre-designed timing duration or a timing result of a previous timing period corresponding to the current timing period; timing based on the current target timing duration; in response to the timing reaching the current target timing duration, determining rendering state change information of the terminal device in the current timing period, and determining a timing result of the current timing period based on the rendering state change information, and entering a next timing period.

This disclosure provides a method for determining channel delay, a delay calibration system, and a testing device. The method includes: in response to the transmission of a measurement signal, starting to time the transmission delay of a transmission channel using a first timing granularity; determining a first timing result based on the first timing granularity upon receiving a measurement feedback signal through the transmission channel; determining a second timing result based on a delay of a second timing granularity within the timing period of the first timing granularity at which the measurement feedback signal is received, based on the difference between the measurement feedback signal and the expected feedback signal; increasing the transmission delay of the transmission signal using a third timing granularity until the received measurement feedback signal meets a preset condition, and determining a third timing result based on the third timing granularity; wherein the third timing granularity is smaller than the second timing granularity and smaller than the first timing granularity; and determining the transmission channel delay based on the first timing result, the second timing result, and the third timing result. This method for determining channel delay is simple in design and cost-effective.

The present invention discloses an adaptive high-precision timing method and system based on deep learning, which monitors low-frequency time code signals and Beidou signals collected in real time by user equipment and saves key parameters of the low-frequency time code signal; when the low-frequency time code signal and the Beidou signal are both normal, or when the low-frequency time code signal is normal and the Beidou signal is abnormal, the quality of the low-frequency time code signal is scored using a signal quality evaluation model and key parameters; when the scoring result is not less than a preset value, the timing result corresponding to the low-frequency time code signal is compensated based on a timing error predicted by a long short-term memory model with attention and the key parameters, and the timing is completed through a low-frequency time code timing mode using the compensated timing result; when the low-frequency time code signal is normal and the Beidou signal is abnormal and the scoring result is less than a preset value, the timing result corresponding to the low-frequency time code signal is compensated using the timing error and a window sliding average, and the timing is completed through the low-frequency time code timing mode using the compensated timing result.

The utility model provides a timing platform of the internet of things. The timing platform comprises operation buttons, a buzzer, a display screen, a wireless communication module, a controller and a power supply, the operation button is connected with the controller and is used for controlling starting or ending of timing; the buzzer is connected with the controller and is used for performing buzzing alarm according to the working instruction sent by the controller; the communication module is connected with the controller and is used for carrying out Internet of Things communication and realizing transmission and sending of timing information; the display screen is connected with the controller and is used for displaying a timing result; the power supply is connected with the controller and is used for supplying power to the Internet of Things timing platform; and the controller is used for controlling the Internet of Things timing platform to carry out timing work and processing a control instruction. The game time can be accurately recorded, and the authenticity and the reliability of game data are ensured. And the plurality of timers can be monitored in real time, so that each competition item can be monitored.

The present invention discloses a method and device for improving the efficiency of FPGA prototype verification. The method comprises: running a design synthesis command to obtain a netlist file after the design synthesis is completed; running a report_qor_assessment command to obtain a current report; detecting a report score and determining the relationship between the score and a preset threshold; if the score is less than the preset threshold, detecting the design and repeating the above steps; and if the score is greater than or equal to the preset threshold, continuing to perform clock relationship judgment, timing result judgment, combinational logic chain level threshold judgment, and fan-out threshold judgment to generate a new synthesis strategy and implementation strategy. In the FPGA prototype verification implementation process, after design synthesis, this method can automatically analyze and report the fan-out, logic level, clock relationship, and timing results, compare them with set parameters, and generate an effective implementation strategy, thereby improving the correctness of FPGA prototype verification implementation and improving the efficiency of prototype verification.

The one or more embodiments of the specification provide a single-epoch timing method, device and system based on Beidou satellite signals, obtain GEO satellite observation values, IGSO satellite observation values and MEO satellite observation values, utilize a GEO timing model, an IGSO timing model and a MEO timing model to obtain GEO timing results, IGSO timing results and MEO timing results, calculate multi-satellite timing results according to the single-satellite timing results of the three types, and utilize a variance component estimation method to determine comprehensive timing results according to the multi-satellite timing results. The Beidou-3 system is utilized to provide accurate timing for the smart grid, and the safe and reliable operation of the smart grid can be ensured.

The present invention discloses a method for analyzing the influence of satellite-ground synchronization accuracy on user timing deviation. The method includes: superimposing noise on clock difference data and simulating satellite-ground synchronization data to obtain satellite-ground clock difference simulation data; modeling the satellite-ground clock difference simulation data to obtain a clock difference model; calculating the estimated value of the clock difference parameter of the satellite-ground clock difference simulation data; and calculating the clock difference prediction error according to the estimated value of the clock difference parameter and the clock difference model. The present invention is used to analyze the influence of satellite-ground synchronization accuracy on user timing deviation. The method is simple and effective, has low cost, has a wider application range, and can specifically analyze the influence of satellite-ground synchronization accuracy on user timing results.

The present application provides a compilation control method, device, medium and electronic device. The compilation control method includes obtaining a project to be compiled; performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled; obtaining a tcl script based on N preset synthesis strategies and M preset implementation strategies; performing parallel operation processing on the preset synthesis strategies based on the tcl script to obtain a synthesis dcp file of the preset synthesis strategy; performing parallel operation processing on the preset implementation strategies based on the synthesis netlist in the synthesis dcp file to obtain a timing result associated with the preset implementation strategy; terminating the operation of the preset implementation strategy, otherwise continuing to operate the preset implementation strategy until the implementation dcp file is obtained after the operation of the preset implementation strategy is completed. The compilation control method can improve the timing convergence efficiency of FPGA, greatly speed up the iteration speed of engineering development, and improve the efficiency of engineering development debugging.

The application provides a multi-mode neural network timing method, a timing processor and a storage medium. The timing processor comprises a processing unit, a global cache unit, an input logic unit and an output logic unit, data transmission is performed through on-chip interconnection, and the processing unit array is divided into processing unit clusters according to application scenarios, and the processing units in each processing unit cluster after division share a feature map cache; wherein the processing unit array is a collection of all processing units in the timing processor; the processing unit is used for caching feature map and convolution kernel data and performing relevant operations; the global cache unit is used for caching convolution kernel data required for timing; the input logic unit is used for inputting a sampling pulse point signal; and the output logic unit is used for outputting a timing result. The scheme can realize timing of multiple neural networks in different application scenarios under low-cost conditions.