614 results about "Hardware circuits" patented technology

The invention relates to an experimental data processing method and device, an AI analysis module and computer equipment, and belongs to the field of data processing.The method comprises the steps that multi-dimensional original data are partitioned according to types, and formats are unified; generating a similarity matrix based on time and space neighborhood information, and marking abnormal fluctuation points; effective signals are separated through a time-frequency feature matching noise library; extracting multi-layer features of basic statistics, time sequence correlation and trend change; and dynamically screening core features to update the tracking type experimental model. The matched AI analysis module integrates hardware circuits of data partitioning, similarity calculation, anomaly marking, noise matching, feature extraction and model updating, and whole-process acceleration is achieved. According to the method, through multi-dimensional data compatibility processing, accurate anomaly detection, multilayer feature fusion and model adaptive optimization, the experimental data processing efficiency and conclusion reliability are remarkably improved, and the method is suitable for real-time analysis of multiple scenes such as scientific research and industry.

The invention discloses a nanosecond-order delay transistor reliability test system and method, and belongs to the technical field of transistor test. The test system is divided into three parts, namely a voltage stress value and stress duration control module, a current control module and a hard switch transient and on-resistance test module. The drain voltage stresses are respectively used for controlling the drain voltage stress value and the drain voltage stress duration of the transistor to be tested; the current during hard switch testing is determined; and the conduction time is long. The test system processes signals through a hardware circuit, can convert an input single-path pulse signal into two paths of inverted pulse signals with dead time, and improves the safety of the test system. The voltage stress duration, the current and the conduction duration of the drain electrode of the transistor to be tested can be flexibly regulated and controlled only by inputting a pulse signal to each of the three modules. Simulation and experiments prove that the measurement delay of switching to the test state after the drain electrode voltage stress is ended is nanosecond magnitude, and the method has important significance for monitoring performance degradation after the transistor drain electrode voltage stress is monitored in real time.

Described herein are systems and methods for programmable, hardware-accelerated congestion monitoring and / or control. At least one circuit can configure a plurality of hardware circuits with one or more rules that, when satisfied, cause the plurality of hardware circuits to generate one or more congestion events indicative of congestion in a network. The at least one circuit can receive the one or more congestion events generated by the plurality of hardware circuits based on one or more network signals in the network satisfying the one or more rules. In response to receipt of the one or more congestion events from the plurality of hardware circuits configured with the one or more rules to detect the congestion in the network, the at least one circuit can analyze the one or more congestion events to address the congestion in the network. Various other methods, systems, and computer-readable media are also disclosed.

The invention discloses a multi-turn memory optomagnetic encoder hybrid system, belongs to the technical field of position and angle measurement encoders, and aims at solving the problems that an existing optomagnetic hybrid encoder is complex in signal processing, long in axial length, insufficient in precision stability and prone to losing the number of turns and the position. The system comprises an optical encoder, a gallium arsenide magnetic signal acquisition sensor, a multi-antipode unequal magnetic ring, a processor, a hardware circuit, an ultra-low power consumption circuit, a signal acquisition module, a signal processing module and the like, integrates self-developed magnetic angle analysis, turn number memory correction and other algorithms, and adopts dual-redundancy design and intelligent signal mode switching. The method simplifies the signal processing flow, shortens the axial length, improves the measurement precision and stability, enhances the environmental adaptability and fault-tolerant capability, prolongs the endurance, and is suitable for the position angle measurement in a high-precision and severe environment.

An apparatus to facilitate hardware acceleration of resource barriers in a graphics environment is disclosed. The apparatus includes resource barrier hardware circuitry for processing cores and a graphics pipeline to: receive a resource barrier instruction to transition a resource utilized by the graphics pipeline from a first usage to a second usage; responsive to the resource barrier instruction, cause a draw group marker having a current draw group count to be sent to an end of the graphics pipeline to track completion of each stage of the graphics pipeline; increment the current draw group count to a new draw group count for each new draw group of the graphics pipeline; and determine that a current signal stage of the graphics pipeline is complete for a current draw group responsive to a done count for the current signal stage being less than or equal to the current draw group count.

The embodiment of the invention provides an interlaced PFC circuit and a phase locking method of the interlaced PFC circuit, the interlaced PFC circuit comprises n PFC circuits, n driving circuits and a processor, and the n PFC circuits comprise a main phase PFC circuit and a slave phase PFC circuit. The phase locking method comprises the steps that a processor obtains a master phase driving signal input to a master phase PFC circuit and obtains a slave phase driving signal input to a slave phase PFC circuit; capturing a first rising edge of the slave phase driving signal after the first rising edge of the master phase driving signal occurs to obtain first time; capturing a second rising edge of the master phase driving signal after the first rising edge of the slave phase driving signal occurs to obtain a second time; and controlling the conduction duration of the slave phase driving signal according to the difference value between the first time and the second time. Therefore, quick closed-loop phase locking of the multi-phase interleaving parallel circuit is realized, full-range quick phase locking is realized under the conditions of non-valley bottom opening and valley bottom opening, meanwhile, the circuit design is simplified, and accurate phase locking can be realized without redundant hardware circuits.

The invention relates to the technical field of power electronics, and discloses a dielectric barrier discharge high-voltage series resonance system and a control method thereof. The system comprises a high-voltage series resonance circuit, an upper computer and a hardware circuit. The upper computer is electrically connected with the hardware circuit, and the hardware circuit is electrically connected with the high-voltage series resonance circuit; wherein the high-voltage series resonance circuit comprises a PFC circuit, a Buck circuit, an LC series resonance circuit, a high-voltage pulse transformer and a dielectric barrier discharge load which are connected in sequence, the high-voltage series resonance circuit converts alternating current into high-frequency high-voltage pulse voltage and provides the high-frequency high-voltage pulse voltage for the dielectric barrier discharge load, and stable dielectric barrier discharge is generated; the upper computer is used for setting parameters, the hardware circuit controls the on-off state of the Buck circuit and the LC series resonance circuit according to the parameters set by the upper computer, accurate generation and control of high-voltage pulse voltage in the dielectric barrier discharge process are achieved, and the response speed and the control precision of the system are also improved.

The invention belongs to the technical field of hardware circuit board design, and discloses a PCIe Switch board downlink port compatible uplink port structure, which comprises a CPU (Central Processing Unit), a PCIe Switch chip, a PCIe port, PCIe equipment, a downlink port Root end and a Clock Buffer, the PCIe expansion system constructs a tree topology through a PCIe Switch chip, a single PCIe channel of a CPU is branched into a plurality of independent channels, and parallel access of multiple devices is achieved. The Switch chip comprises an uplink port and a plurality of downlink ports, and the uplink port is directly connected with the PCIe controller of the CPU through a special connector and bears a data signal and a key clock signal; clock signals are transmitted by adopting high-speed differential pairs. According to the PCIe Switch board, high-efficiency expansion is achieved through the design that a downlink port of the PCIe Switch board is compatible with an uplink port and multi-dimensional technological innovation, the core of the PCIe Switch board adopts a CPLD dynamic configuration technology, a BPTYPE level and a 2W-CLK mode are switched in real time through an onboard dial switch, the same physical port can be flexibly configured to be an I2C master equipment clock source or a data channel, and the switching delay is smaller than 50 ns.

The invention discloses a variable frequency phase shift control DAB type single-stage inverter reactive power control method, system and device and a medium, and belongs to the technical field of power electronic converter control, and the method comprises the steps: setting a reactive power instruction as zero; when the reactive power instruction changes, the active power instruction and the reactive power instruction at the current moment are decomposed into a direct-axis current reference value and a quadrature-axis current reference value respectively; comparing the reference value with an actual sampling value, calculating an error compensation amount by using a PI controller, and determining the amplitude and phase of the AC side current according to the compensation amount; according to the amplitude and the phase of the voltage and the current, a DAB frequency conversion phase shift control curve is calculated; and generating a PWM (Pulse Width Modulation) signal according to the frequency conversion phase shift control curve obtained by calculation, wherein the PWM signal is used for driving a DAB inverter to carry out power transmission. According to the invention, on the premise that no extra hardware circuit is introduced, dynamic adjustment and accurate control of the instantaneous reactive power of the AC output side can be realized.

The invention relates to the technical field of chip packaging, in particular to a PCIe (peripheral component interface express) equipment function number border crossing prevention method supporting ARI (automatic repeat interface). The hardware layer protection process is as follows: S1-1, hot plugging; s1-2, if it is detected that the equipment declarates to support ARI, the PCIe controller hardware circuit immediately sets an equipment number register to zero; s1-3, only allowing the PCIe controller of the system to read the configuration space unidirectionally during the low level period of the reset signal PERST #; the interception process of the driving layer is as follows: S2-1, in an equipment enumeration stage, an operating system drives to dynamically read an ARI capability register; s2-2, if the equipment declarates to support ARI, forcing an equipment number register to be equal to 0, and releasing an original equipment number bit space for function number expansion; s2-3, border crossing access is blocked; and S2-4, synchronizing the state register. Compared with the prior art, correctness of device function numbers is guaranteed through two dimensions of hardware register state solidification and driver layer access truncation, and'perception-free 'fault tolerance of the PCIe device under ARI / traditional mode switching is achieved for the first time.

The invention relates to the field of cell analysis, and provides a multi-mode digital micro-fluidic system and method for cell sorting analysis, the system comprises an active digital micro-fluidic platform, the active digital micro-fluidic platform comprises a micro-fluidic chip, an upper computer control system and an FPGA hardware circuit, an upper computer generates a liquid drop path planning instruction, the FPGA hardware circuit converts the liquid drop path planning instruction into an electrode driving signal, and the electrode driving signal is transmitted to the micro-fluidic chip; the nanoliter-grade liquid drops are driven to change between the electrodes; the optical tweezers platform comprises a laser device, an optical microscope and a CMOS camera, laser beams are generated by the laser device to form a three-dimensional optical potential well, the laser beams are transmitted into the micro-fluidic chip through the optical microscope to realize non-contact control on cells, and the CMOS camera records images and transmits the images back to the upper computer; the objective table clamp is used for realizing cooperative control of the optical tweezers and the active digital microfluidics; and the image recognition system is used for recognizing morphological characteristics of cells in the liquid drops based on a convolutional neural network and screening target cells. According to the invention, integration of high-throughput nondestructive cell sorting and in-situ multi-modal analysis is realized.

The embodiment of the invention discloses a ripple component extraction method, a ripple signal suppression method, a ripple component extraction device and power equipment, and the method comprises the steps: inputting a target bus voltage signal and an instantaneous angular frequency into an SOGI filter for processing, enabling the SOGI filter to output an instantaneous in-phase component and an instantaneous quadrature component, and controlling a PI controller to extract a ripple signal based on an instantaneous feedback quantity, and performing closed-loop control on the instantaneous angular frequency, and when the instantaneous angular frequency converges to the target angular frequency, outputting an instantaneous in-phase component of the target angular frequency by the SOGI filter. The ripple component is extracted in a software mode, no hardware circuit needs to be additionally arranged, the size miniaturization of the energy storage system is facilitated, and the hardware cost is reduced. The instantaneous feedback quantity provides the tracking direction and size of the real angular frequency of the ripple component for the PI controller, so that the instantaneous angular frequency output by the PI controller is accurately and reliably converged to the target angular frequency, and the extraction of the ripple component to be solved is adaptively completed.

The invention discloses a microprocessor dynamic power consumption optimization system based on deep learning, which belongs to the technical field of microprocessor power consumption management, and comprises a working load feature extraction module, a neural network prediction module, a dynamic core distribution module and a particle size power supply management module, the working load feature extraction module extracts feature parameters of calculation intensity, memory access intensity and input and output intensity of an application program in real time through a hardware circuit; the neural network prediction module predicts future power consumption and performance requirements based on a deep reinforcement learning network; the dynamic core distribution module intelligently selects an optimal core combination; the particle size power supply management module independently executes dynamic voltage frequency regulation on each core; according to the invention, accurate power consumption optimization of the heterogeneous multi-core processor is realized through deep coupling and closed-loop cooperation of the four modules, and compared with the prior art, the energy efficiency ratio is improved by more than 40%, and the power consumption prediction error is reduced to be within 5%.

Example storage systems, storage devices, and methods provide peer configuration of hardware compute resources among peer storage devices. Data storage devices may include hardware circuits, such as graphics processor units, media processor circuits, compute accelerator circuits, and neural processing units, configured for compute operations targeting host data associated with that storage device. One of the storage devices is configured to act as a master storage device for determining firmware configurations for the other storage devices and sending an indication of the firmware image to be used for some operating period. The storage device receiving the firmware image loads the firmware image for the hardware circuit and reboots the hardware circuit to configure it with the firmware image.

The invention discloses a DAC (Digital-to-Analog Converter) output voltage control method, system and equipment based on stepping delay and a medium. The method comprises the following steps: acquiring the current output voltage of the DAC as an initial voltage value; receiving a target voltage value and a set value of a target slope parameter; the target slope parameter comprises a target step length and a target delay; and controlling the initial voltage value to gradually change from the target slope to the target voltage value through the target slope parameter. The method is realized without depending on a hardware circuit, the DAC can change the output voltage according to the set slope parameter through a software implementation process, and the requirements on the DAC output voltage slope in different scenes can be met. According to the method, the target slope parameter and the target voltage value can be changed at any time in the DAC output voltage adjusting process, the DAC output voltage is controlled to be changed into the new target voltage value according to the new slope parameter, and no error exists in the software running process. The method is easy to modify and migrate and has high universality.

The invention discloses a deformation rolling stone integrated road slope radar monitoring system and a detection method, and belongs to the field of radar detection, the deformation rolling stone integrated road slope radar monitoring system comprises a signal processing module, a multi-channel radio frequency module and an antenna array module, the multi-channel radio frequency module is connected with the signal processing module through a hardware line, and the antenna array module is connected with the signal processing module. The antenna array module is connected with the multi-channel radio frequency module through a hardware line; the signal processing module comprises a programmable main control chip, a data memory, an analog-to-digital converter and a direct digital frequency synthesizer, a line of the signal processing module is also connected with a camera, and the system also comprises a power supply module for supplying power to the signal processing module, the multi-channel radio frequency module and the camera. According to the deformation and rolling stone integrated road slope radar monitoring system and the detection method, deformation and rolling stone integrated monitoring is realized, two sets of equipment do not need to be arranged, the cost and the arrangement difficulty are reduced, early warning is reliable, the environmental adaptability is high, and the requirement for long-term field road monitoring is met.

The invention discloses an active current sharing circuit and a control method thereof. The active current sharing circuit comprises a signal processing circuit, a driving circuit and a grid voltage adjusting circuit. The control method corresponds to the active current sharing circuit. According to the application, the switching speed of the power device is adjusted through the auxiliary driving current applying circuit, and the dynamic current balance degree of the parallel power device can be effectively improved; through a method of connecting a high-precision resistor in series with a source electrode loop of the power device, simple and accurate measurement of the current of the power device can be realized, and an analog current signal is converted into a pulse signal containing current information through a hardware circuit; the auxiliary driving current and the auxiliary driving current applying circuit grid voltage are calculated through the active current sharing control algorithm, dynamic current balancing of the parallel power devices can be achieved in a short switching period, the control method is simple, the response speed is high, and the method is not affected by line transmission delay.

The invention discloses a navigation hardware fault diagnosis system based on an adaptive clustering algorithm, relates to the field of satellite navigation systems, and solves the technical problems that multi-dimensional feature extraction and comprehensive evaluation value calculation are difficult to carry out, and a new fault type is difficult to verify by setting multiple judgment results. Comprising the following steps: collecting multi-source data from a satellite, a user receiver and a ground control system; key features are extracted from each type of processed data, and signal, positioning and hardware circuit comprehensive evaluation values are calculated; feature vectors are constructed, after standardization, Eps parameters of the DBSCAN are dynamically determined through the K distance, and self-adaptive clustering is achieved; based on a clustering result, defining a similarity calculation rule, constructing a known fault type library, identifying fault types through a matching rule, and analyzing clusters which cannot be matched; and if the clustering cannot be matched and meets various judgment conditions, identifying the fault type as a new fault type, updating the characteristics of the fault type to a known fault library, and triggering model retraining at the same time.

The invention discloses a model prediction control method for a low-common-mode-voltage dual three-phase motor with improved steady-state performance, and belongs to the technical field of dual three-phase permanent magnet synchronous motor control. The method comprises the following steps: firstly, suppressing harmonic current by synthesizing virtual voltage vectors with a specific duty ratio, and synthesizing a candidate output voltage vector by using two adjacent virtual voltage vectors according to a predefined duty ratio; designing a value function without a weight coefficient to select an optimal voltage vector; designing a dual duty ratio technology to calculate the duty ratios of the two virtual voltage vectors for synthesizing the optimal voltage vector; a specific switching sequence in which virtual zero vectors are arranged on two sides and in the middle of a control period is designed, and the switching sequence is generated by using a phase-shifting carrier method. According to the invention, the common-mode voltage can be effectively reduced without adding any hardware circuit, the current harmonic wave and the torque ripple are obviously reduced by expanding the modulation range, the steady-state performance of the system is improved, and the method is suitable for a dual three-phase motor driving system with high requirements on performance and reliability.

The invention provides a cross-platform brain-computer interface normal form system suitable for natural state monitoring, and the system comprises a cross-platform development module which achieves the operation of a set of codes on a plurality of platforms through an owner-drawing engine; the task integration and expansion module is used for integrating various brain-computer interface normal form tasks; establishing a local material library management mechanism, and performing association configuration on task types and stimulation materials through a data configuration file; according to the multimedia precise synchronous control module, an asynchronous programming mechanism and a timer function of a Flutter are adopted, when audio and video materials are played or ended, a hardware circuit or streaming data of an electroencephalogram collecting device, a physiological multi-guide instrument or a network camera is labeled, alignment of multi-device and multi-modal data is achieved, and the multi-device and multi-modal data are integrated. Generating a task log containing a timestamp mark; and the natural stimulation task module is used for incorporating a task for simulating a natural scene into a brain-computer interface normal form. And a brain-computer interface system which gives consideration to cross-platform consistency and flexible configuration of natural scene tasks is provided.

A high-speed trigger device disclosed by the present invention comprises an ARM module and an FPGA module, the FPGA module comprises an encoder signal input interface, a high-speed input interface and a high-speed output interface, the ARM module is in communication connection with an upper computer, the ARM module is in communication connection with the FPGA module, and the ARM module is used for receiving parameter instruction information provided by the upper computer and transmitting the parameter instruction information to the FPGA module. The parameter instruction information comprises operation mode configuration information. According to the high-speed triggering device, the architecture that ARM and FPGA are processed separately is adopted, setting of parameter instruction information and the like are processed by the ARM module, counting of triggering signals, output of control signals of the high-speed output interface and the like are processed by the FPGA module, parallel processing is achieved through the FPGA module, the processing logic can be completely achieved by a hardware circuit of the FPGA module, and low-delay triggering is achieved.

The invention relates to the field of integrated circuit design, and discloses a processor preamble and mantissa continuous bit parallel counting device and method. The device comprises a 32-bit bit sequence flipping module, a 32-bit bit negation module, eight 4-bit leading zero detection modules, four 8-bit leading zero processing modules, two 16-bit leading zero processing modules, a 32-bit leading zero processing module and a 32-bit result output module. According to the invention, parallel counting can be carried out on leading zeros, leading 1, mantissa zeros or mantissa 1 of various data with different precisions in a single processor clock period, so that the required time sequence path length is greatly shortened, the higher processor clock frequency is realized, the multiplexing of a hardware circuit is realized, and the cost is reduced. The circuit greatly reduces the use of transistor resources, reduces the area of a chip, reduces the cost and power consumption of the chip, improves the operation efficiency, universality and adaptability of the processor, and is suitable for being applied to application scenes such as a high-performance digital signal processor and a CPU (Central Processing Unit).

The invention belongs to the technical field of signal generation and acquisition, and particularly relates to an RFSOC-based multichannel broadband signal transmitting and receiving device, which comprises an upper computer unit, an intermediate frequency signal transmitting and receiving unit, a down-conversion unit and a local oscillator unit, and is characterized in that the upper computer unit, the intermediate frequency signal transmitting and receiving unit, the down-conversion unit and the local oscillator unit cooperatively realize signal transmission and acquisition; the upper computer unit adopts an ARM chip, communicates with the intermediate frequency signal transceiving unit through a PCIE interface, and is used for parameter configuration, flow control, state monitoring and collected data storage. The integration level can be greatly improved, complex external connection and compatible debugging are omitted, software and hardware design is remarkably simplified, and the maintenance cost is reduced; different application scenes can be adapted without changing a hardware circuit, so that the configuration flexibility is greatly improved; the power consumption is reduced, and the application requirements of miniaturization and light weight are better met; and the requirements of multi-channel synchronous transceiving and high-precision signal processing can be met.

Systems and methods for faster BVH building that requires repeated sorting and partitioning of are described. Specific hardware circuitries are programmed to sort partitioned data and make reductions for each partition. The hardware units perform the initial sorting along a split axis and calculation of bounding box extents. The solutions presented herein improve performance of BVH builds, especially for cases where the geometry is comprised of many small BVH treelets. The most expensive processing steps in BVH construction are delegated to hardware thereby minimizing memory access latencies and increasing overall system efficiencies.

The scheme discloses a low-cost high-side over-current protection circuit and an over-current protection method thereof, and the circuit comprises a sampling resistor which is connected in series with a positive wire of a bus; the light-emitting diode is connected in parallel with the sampling resistor; a photosensitive device coupled to the light emitting diode; the signal processing circuit is connected to the photosensitive device and is used for outputting a latch signal representing overcurrent based on the overcurrent signal; the PWM driving hardware circuit is connected to the photosensitive device; and the control circuit is connected to the signal processing circuit and the PWM driving hardware circuit and is used for controlling the PWM output to be turned off based on the latch signal. According to the scheme, a high-speed and reliable response effect is achieved, firstly, PWM is rapidly turned off on the hardware level based on an overcurrent signal, and high-speed hardware response is achieved; and secondly, the overcurrent signal is latched for a period of time through the latch logic, so that on one hand, the PWM turn-off time is prolonged, the current is prevented from instantly recovering work after rapid drop, and on the other hand, enough time is provided for the control circuit for logic processing, and the response reliability is realized.

A multi-sensor integrated intelligent tool holder real-time monitoring and anti-collision system, comprising: an intelligent tool holder device, an external PLC controller, a built-in relay, a numerical control machine tool and a PC signal processing and display module; the intelligent tool holder device comprises: a handle cone structure, a force sensor structure, a resistance strain gauge group, a protective shell, a plurality of supporting copper columns, a first hardware circuit board, a second hardware circuit board, a vibration sensor, a lithium battery, a fixed upper shell, a fixed bottom shell, a draw stud, a clasp spring, a compression cap and an end mill. The application is based on the collected cutting signals for real-time analysis and rapid judgment and response, is not affected by the machining environment and the shape and size of the workpiece, is accurate in measurement, greatly reduces the influence of the external sensor arrangement distance on the cutting data accuracy, and is suitable for the monitoring of cutting force and vibration and the anti-collision monitoring link in the part machining process, and improves the cutting automation, intelligence and safety level.

The invention discloses a novel elevator light curtain which comprises an all-plastic shell and a circuit board arranged in the all-plastic shell. The circuit board adopts a cascade multi-path switching module to gate a plurality of photoelectric units, and a grounding filter network is arranged at the output end of each photoelectric unit for source filtering; an active filtering buffer unit with a PNP triode as a core is introduced into a signal path, and a signal processing module comprising a four-stage operational amplifier and a gradient RC filtering network is adopted for step-by-step amplification and conditioning. Through systematic hardware circuit design, on the premise of not depending on metal shielding, internal and external electromagnetic interference is actively and multiply inhibited from the source to the terminal, meanwhile, the structure is simplified, the cost is reduced, the short circuit and failure risks possibly caused by shell grounding are thoroughly avoided, and higher reliability, environmental adaptability and economical efficiency are achieved.

The utility model discloses an intelligent manual brake fastener which comprises a fastener body and a hardware circuit, and the hardware circuit comprises a master control module, a wireless communication module, a card reading module, a detection module and a power module. The main control module comprises an MCU and a storage sub-module, the storage sub-module is electrically connected with the MCU, and the MCU is electrically connected with the wireless communication module and the card reading module; the detection module comprises a tension and pressure detection sub-module and an acceleration detection sub-module, the output end of the tension and pressure detection sub-module is connected with the input end of the MCU, and the output end of the acceleration detection sub-module is connected with the input end of the MCU; the power supply module comprises a solar charging sub-module, a wireless charging sub-module, an electric quantity detection sub-module and a battery. According to the utility model, the locking state of the fastener can be detected in real time, workers do not need to inspect, accidents caused by human factors are reduced, brake driving detection is realized, and timely alarming and stopping are realized.

The application discloses a kind of charging and discharging control device, equipment and system, including power management module, central processing module, power supply information acquisition module and charging and discharging control module integrated on substrate;Substrate is equipped with power supply bus;The input end of power management module is used to connect direct-current power supply, and the output of power management module is connected with power supply bus;Power supply information acquisition module is used to acquire input power supply information and output power supply information of power management module;Charging and discharging control module is used to connect charging and discharging gun;Central processing module is used to control power management module and charging and discharging control module work according to input power supply information and output power supply information.This technical scheme integrates power management module and charging and discharging control module on the same substrate, and is uniformly controlled by the same central processing module, reduces the repeated design and manufacture of hardware circuit, and reduces hardware cost.

The application discloses a kind of method and device that SSD control chip self-adapting abnormal stop IO, it is related to SSD technical field, comprising: obtaining the fatal error interrupt signal generated by multiple function modules in SSD control chip, global stop flow enable signal is generated by hardware logic circuit;In response to this signal, synchronously control host interface side stops transmitting data to host, and control flash interface side stops reading and writing NAND flash to erase operation.By pure hardware circuit, the fast convergence of error signal and the generation of global stop flow instruction are realized, the extremely fast response of nanosecond to microsecond level is achieved, and the defect of large delay of software dependent scheme is fundamentally overcome.Two ends stop flow are triggered synchronously using single enable signal, the atomicity and cooperativity of operation are ensured, and the risk of data inconsistency is eliminated.The mechanism is independent of central processing unit and firmware operation, and can still be independently and reliably executed in the extreme case of core component failure, significantly improving the data integrity and system reliability of SSD.