1133 results about "Hardware circuits" patented technology

The invention relates to an experimental data processing method and device, an AI analysis module and computer equipment, and belongs to the field of data processing.The method comprises the steps that multi-dimensional original data are partitioned according to types, and formats are unified; generating a similarity matrix based on time and space neighborhood information, and marking abnormal fluctuation points; effective signals are separated through a time-frequency feature matching noise library; extracting multi-layer features of basic statistics, time sequence correlation and trend change; and dynamically screening core features to update the tracking type experimental model. The matched AI analysis module integrates hardware circuits of data partitioning, similarity calculation, anomaly marking, noise matching, feature extraction and model updating, and whole-process acceleration is achieved. According to the method, through multi-dimensional data compatibility processing, accurate anomaly detection, multilayer feature fusion and model adaptive optimization, the experimental data processing efficiency and conclusion reliability are remarkably improved, and the method is suitable for real-time analysis of multiple scenes such as scientific research and industry.

An apparatus to facilitate lossless and lossy automatic hardware compression in graphics-to-graphics network links is disclosed. The apparatus includes compressor / decompressor circuitry (CDC) integrated with physical layer (PHY) intellectual property (IP) hardware circuitry for a graphics processor unit (GPU)-to-GPU communication link communicably coupling a first GPU to one or more other GPUs, the CDC to: receive a data message from the first GPU, wherein the data message is in an uncompressed format; determine that a compression process is to be applied to the data message; apply the compression process to the data message to generate a compressed data message; and cause a GPU link IP hardware circuitry that comprises the PHY IP hardware circuitry to transmit the compressed data message over the GPU-to-GPU communication link.

An apparatus providing tensor core matrix multiplication and accumulation (MMA) with hardware-based statistics collection and outlier suppression is disclosed. The apparatus includes processor circuitry comprising at least one processor core comprising matrix multiplication circuitry to: execute a matrix multiplication operation on first input data from a first set of registers and on second input data from a second set of registers; collect, as part of executing the matrix multiplication operation via statistics collection hardware circuitry of the matrix multiplication circuitry, output statistics data corresponding to the matrix multiplication operation; and output the output statistics data along with a result of the matrix multiplication operation; and output statistics storage to store the output statistics data.

Vector-scaled hierarchical codebook quantization reduces precision (bitwidth) vectors of parameters and may enable energy-efficient acceleration of deep neural networks. A vector (block array) comprises one or more parameters within a single dimension of a multi-dimensional tensor (or kernel). For example, block array comprises 4 sub-vectors (blocks) and each sub-vector comprises 8 parameters. The parameters may be represented in integer, floating-point, or any other suitable format. A vector cluster quantization technique is used to quantize blocks of parameters in real-time. Hardware circuitry within a datapath identifies an optimal codebook of a plurality of codebooks for quantizing each block of parameters and the block is encoded using the identified codebook. During processing, the identified codebook is used to obtain the quantized parameter and perform computations at the reduced precision.

The invention belongs to the technical field of motor control, and relates to a permanent magnet synchronous motor sensorless control method, system and hardware circuit, angular velocity estimation is designed based on a q-axis current model under a two-phase rotating coordinate system, angular velocity estimation compensation is designed based on a d-axis current model, and a rotating speed correction coefficient is introduced. And dynamic compensation of the estimated angular velocity value is realized. An accurate angular velocity estimated value and an accurate rotor angle estimated value are obtained by constructing a Romberg observer with an angular velocity estimated value and a rotor angle estimated value as outputs based on a dq rotating coordinate system. Taking an angular velocity error obtained by a motor angular velocity given value and a motor angular velocity estimated value as input of an outer ring PI controller, so as to ensure that the angular velocity estimated value tracks the motor angular velocity given value and output a q-axis current reference value; taking the difference value between the q-axis current reference value and the q-axis current sampling value and the difference value between the d-axis current reference value and the d-axis current sampling value as the input of an inner ring PI controller so as to ensure the bandwidth and the influence capability on the load, and outputting a d-axis voltage reference value and a q-axis voltage reference value; and converting the d-axis voltage reference value and the q-axis voltage reference value into voltage reference values under a two-phase static coordinate system based on the rotor angle estimation value so as to divide SVPWM drive circuit sectors, select voltage vectors, calculate action time, control on and off time of a permanent magnet synchronous motor switching device, and control on-off time of the permanent magnet synchronous motor switching device. And the alternating current speed regulation performance of the permanent magnet synchronous motor without the position sensor under the Romberg observer method is ensured.

The invention relates to the technical field of intelligent electric control systems, and discloses an intelligent electric control system and a control circuit board with the intelligent electric control system. The system comprises a signal acquisition module used for acquiring an input signal and judging a signal partition; the mode mapping module is used for constructing a mapping relation between the signal partition and the control partition; the parameter combination module is used for extracting key partitions and judging a parameter combination matching degree to obtain a bias combination; the state updating module is used for updating the mapping relation based on the deviation combination; and the control management module generates a control management library. The control circuit board integrates each module hardware circuit unit to realize signal transmission and data interaction. Accurate processing, dynamic mapping, optimal parameter combination, state real-time updating and scientific control management of the input signals are achieved, the intelligence, adaptability and reliability of the electronic control system are improved, and the system is suitable for electronic control scenes of various intelligent devices.

The invention discloses a nanosecond-order delay transistor reliability test system and method, and belongs to the technical field of transistor test. The test system is divided into three parts, namely a voltage stress value and stress duration control module, a current control module and a hard switch transient and on-resistance test module. The drain voltage stresses are respectively used for controlling the drain voltage stress value and the drain voltage stress duration of the transistor to be tested; the current during hard switch testing is determined; and the conduction time is long. The test system processes signals through a hardware circuit, can convert an input single-path pulse signal into two paths of inverted pulse signals with dead time, and improves the safety of the test system. The voltage stress duration, the current and the conduction duration of the drain electrode of the transistor to be tested can be flexibly regulated and controlled only by inputting a pulse signal to each of the three modules. Simulation and experiments prove that the measurement delay of switching to the test state after the drain electrode voltage stress is ended is nanosecond magnitude, and the method has important significance for monitoring performance degradation after the transistor drain electrode voltage stress is monitored in real time.

Described herein are systems and methods for programmable, hardware-accelerated congestion monitoring and / or control. At least one circuit can configure a plurality of hardware circuits with one or more rules that, when satisfied, cause the plurality of hardware circuits to generate one or more congestion events indicative of congestion in a network. The at least one circuit can receive the one or more congestion events generated by the plurality of hardware circuits based on one or more network signals in the network satisfying the one or more rules. In response to receipt of the one or more congestion events from the plurality of hardware circuits configured with the one or more rules to detect the congestion in the network, the at least one circuit can analyze the one or more congestion events to address the congestion in the network. Various other methods, systems, and computer-readable media are also disclosed.

The invention discloses a multi-turn memory optomagnetic encoder hybrid system, belongs to the technical field of position and angle measurement encoders, and aims at solving the problems that an existing optomagnetic hybrid encoder is complex in signal processing, long in axial length, insufficient in precision stability and prone to losing the number of turns and the position. The system comprises an optical encoder, a gallium arsenide magnetic signal acquisition sensor, a multi-antipode unequal magnetic ring, a processor, a hardware circuit, an ultra-low power consumption circuit, a signal acquisition module, a signal processing module and the like, integrates self-developed magnetic angle analysis, turn number memory correction and other algorithms, and adopts dual-redundancy design and intelligent signal mode switching. The method simplifies the signal processing flow, shortens the axial length, improves the measurement precision and stability, enhances the environmental adaptability and fault-tolerant capability, prolongs the endurance, and is suitable for the position angle measurement in a high-precision and severe environment.

Methods, apparatuses, and systems related to securing memory data are described. A hardware circuit is configured to encrypt and decrypt memory data using a scrambling key unique to a computing process processing the memory data. In writing the memory data, the hardware circuit generates scrambled memory data based on encrypting the memory data according to the security key. The scrambled memory data is stored for the write operation instead of the memory data. When the same process reads back the scrambled data, the same security key can be used to decrypt the scrambled data and recover the initial unscrambled memory data.

The invention provides a method and a device for generating testability design scripts, electronic equipment and a storage medium, and belongs to the technical field of testability design, the method comprises the following steps: determining a test technology of a to-be-tested target according to test technology indication information in to-be-tested demand parameters; according to the test technology of the to-be-tested target and to-be-tested target information in the to-be-tested demand parameters, script design information is determined; and according to the script design information, generating an automatic script file for testing the to-be-tested target. The test script for the chip hardware circuit can be automatically generated.

An apparatus to facilitate hardware acceleration of resource barriers in a graphics environment is disclosed. The apparatus includes resource barrier hardware circuitry for processing cores and a graphics pipeline to: receive a resource barrier instruction to transition a resource utilized by the graphics pipeline from a first usage to a second usage; responsive to the resource barrier instruction, cause a draw group marker having a current draw group count to be sent to an end of the graphics pipeline to track completion of each stage of the graphics pipeline; increment the current draw group count to a new draw group count for each new draw group of the graphics pipeline; and determine that a current signal stage of the graphics pipeline is complete for a current draw group responsive to a done count for the current signal stage being less than or equal to the current draw group count.

The invention relates to the field of measurement, in particular to an intelligent concrete aggregate moisture content rapid determinator, which comprises a signal transmitting and receiving module, which transmits electromagnetic waves at a series of set frequencies and collects reflection signals at each frequency; the signal processing module is used for carrying out signal processing on the collected reflected signals; and the dielectric constant calculation module is used for calculating the dielectric constant of the measured medium under each frequency according to the signal characteristic parameter and the relationship between the signal and the dielectric constant of the medium. The method has the advantages that the water content of the concrete aggregate can be continuously and rapidly measured, the damage degree to the concrete aggregate is small, a hardware circuit is simple, and the cost of corresponding measuring equipment is low. Compared with other various methods for measuring the water content of the concrete aggregate, the method has the advantages that portability is achieved, and the FDR has obvious advantages from the comprehensive characteristics of accuracy, continuity, equipment cost and the like.

The invention discloses a WAPI, CCMP and GCMP encryption and decryption coexisting parallel processing system and method for a wireless local area network. The system comprises a transmitter and a receiver. The transmitter is used for reading a plaintext data frame to be encrypted from an application layer, and the plaintext data frame to be encrypted comprises a first MAC frame header, a first security header and a first frame body; reading plaintext data from the first frame body to enable the MAC layer to carry out encryption processing through an encryption module, send encrypted information to a physical layer and then transmit the encrypted information through an air interface; the receiver is used for receiving a to-be-decrypted ciphertext data frame from the air interface, and the to-be-decrypted ciphertext data frame comprises a second MAC frame header, a second security header and a second frame body; reading the ciphertext data and the integrity check MIC ciphertext value from the second frame body, so that the MAC layer sends decryption information to the application layer after carrying out decryption processing through a decryption module; the encryption module encrypts plaintext data; and the decryption module decrypts the ciphertext data. Therefore, the hardware circuit scale is remarkably reduced, and the space occupancy rate is remarkably reduced.

The invention provides a memory management method, and the method is realized by a processor core through executing program codes so as to manage data in a memory. In this way, whether the data stored in the memory is changed due to the memory reliability problem or not can be recognized through a software means. Compared with the ECC technology needing a controller and / or a DDR chip to support the ECC characteristics, the memory management method provided by the invention does not need to change the design of a hardware circuit, is beneficial to reducing the requirement of memory management on DDR hardware, and expands the use scene of the memory management method. ECC particles of a CPU small system can be removed in some scenes, and hardware cost reduction is achieved. The invention further provides a management device corresponding to the management method, computer equipment, a computer readable storage medium and a computer program product.

The embodiment of the invention provides an interlaced PFC circuit and a phase locking method of the interlaced PFC circuit, the interlaced PFC circuit comprises n PFC circuits, n driving circuits and a processor, and the n PFC circuits comprise a main phase PFC circuit and a slave phase PFC circuit. The phase locking method comprises the steps that a processor obtains a master phase driving signal input to a master phase PFC circuit and obtains a slave phase driving signal input to a slave phase PFC circuit; capturing a first rising edge of the slave phase driving signal after the first rising edge of the master phase driving signal occurs to obtain first time; capturing a second rising edge of the master phase driving signal after the first rising edge of the slave phase driving signal occurs to obtain a second time; and controlling the conduction duration of the slave phase driving signal according to the difference value between the first time and the second time. Therefore, quick closed-loop phase locking of the multi-phase interleaving parallel circuit is realized, full-range quick phase locking is realized under the conditions of non-valley bottom opening and valley bottom opening, meanwhile, the circuit design is simplified, and accurate phase locking can be realized without redundant hardware circuits.

The invention relates to the technical field of power electronics, and discloses a dielectric barrier discharge high-voltage series resonance system and a control method thereof. The system comprises a high-voltage series resonance circuit, an upper computer and a hardware circuit. The upper computer is electrically connected with the hardware circuit, and the hardware circuit is electrically connected with the high-voltage series resonance circuit; wherein the high-voltage series resonance circuit comprises a PFC circuit, a Buck circuit, an LC series resonance circuit, a high-voltage pulse transformer and a dielectric barrier discharge load which are connected in sequence, the high-voltage series resonance circuit converts alternating current into high-frequency high-voltage pulse voltage and provides the high-frequency high-voltage pulse voltage for the dielectric barrier discharge load, and stable dielectric barrier discharge is generated; the upper computer is used for setting parameters, the hardware circuit controls the on-off state of the Buck circuit and the LC series resonance circuit according to the parameters set by the upper computer, accurate generation and control of high-voltage pulse voltage in the dielectric barrier discharge process are achieved, and the response speed and the control precision of the system are also improved.

The invention discloses an ion source current control device and system, and relates to the field of circuits, the ion source current control device comprises a sampling circuit, a control circuit and a power supply circuit, the control circuit is connected with the sampling circuit, the ion source current of a neutron tube can be detected in real time, and power supply of a hot wire is controlled in real time by adopting a hardware circuit feedback mode. The current stability of the ion source is rapidly maintained, the calculation delay of a software mode is eliminated, and the control circuit can realize the adjustment of the duty ratio of the output pulse signal through the difference value between the first voltage value and the second voltage value, so as to realize the accurate control of the neutron tube hot wire power supply process. The whole control process is realized through a hardware circuit, the response speed is high, the output is stable, the stability of the output ion source current is ensured, the situations such as jitter are avoided, the application range of the neutron source is expanded, and wide popularization of the neutron source is facilitated.

The invention discloses a channel-configurable liquid particle pulse amplitude detection method and a related device, and relates to the field of digital signal processing, and the method comprises the following steps: eliminating a background noise reference value of a digital pulse signal, presetting a dynamic threshold value, filtering a noise signal of which the amplitude value is lower than the dynamic threshold value in the digital pulse signal, and obtaining a channel-configurable liquid particle pulse amplitude detection result; obtaining a baseline correction digital pulse signal; when the amplitude of the baseline correction digital pulse signal exceeds a dynamic threshold for the first time, pulse counting is started, peak detection is carried out on the baseline correction digital pulse signal, and a pulse peak value and a peak value position corresponding to a pulse event are obtained; a channel threshold parameter is preset through an upper computer, a plurality of independent channels are divided, pulse events are loaded into the corresponding independent channels to be accumulated, a channel count value and corresponding particle size distribution data are obtained, and liquid particle pulse amplitude detection is completed. The problem that the number of channels and threshold parameters cannot be dynamically adjusted when a current hardware circuit is used for liquid particle pulse amplitude detection is solved.

The invention belongs to the technical field of hardware circuit board design, and discloses a PCIe Switch board downlink port compatible uplink port structure, which comprises a CPU (Central Processing Unit), a PCIe Switch chip, a PCIe port, PCIe equipment, a downlink port Root end and a Clock Buffer, the PCIe expansion system constructs a tree topology through a PCIe Switch chip, a single PCIe channel of a CPU is branched into a plurality of independent channels, and parallel access of multiple devices is achieved. The Switch chip comprises an uplink port and a plurality of downlink ports, and the uplink port is directly connected with the PCIe controller of the CPU through a special connector and bears a data signal and a key clock signal; clock signals are transmitted by adopting high-speed differential pairs. According to the PCIe Switch board, high-efficiency expansion is achieved through the design that a downlink port of the PCIe Switch board is compatible with an uplink port and multi-dimensional technological innovation, the core of the PCIe Switch board adopts a CPLD dynamic configuration technology, a BPTYPE level and a 2W-CLK mode are switched in real time through an onboard dial switch, the same physical port can be flexibly configured to be an I2C master equipment clock source or a data channel, and the switching delay is smaller than 50 ns.

The embodiment of the invention discloses a PWM signal generation method. The generation method comprises the following steps: determining setting delay time and reset delay time of an nth PWM delay signal, and determining a first comparison result of the setting delay time and a preset clock period and a second comparison result of the reset delay time and the preset clock period, and allocating a first delay time to the delay module and allocating a first comparison threshold to the first comparator according to the first comparison result, and allocating a second delay time to the delay module and allocating a second comparison threshold to the second comparator according to the second comparison result. According to the embodiment of the invention, the method does not need to depend on a high-precision clock chip, can achieve the delay processing of the PWM signal through the fine adjustment operation on a low-cost hardware circuit, can achieve the delay of the duty ratio, can also achieve the delay of the signal period, is higher in time resolution, and is higher in precision. And more accurate and stable PWM signals can be output.

An apparatus includes a host interface; a network interface; and a programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors to implement network interface functionality and to: determine portions of a set of computer vision (CV) processes to be deployed on the programmable circuitry and a host device, wherein the host device to be communicably coupled to the programmable network interface device; access instructions to cause the portions of the set of the CV processes to be deployed on the host device and the programmable network interface device; and wherein a media processing portion of the set of the CV processes is to be deployed to the programmable circuitry, and wherein the programmable circuitry is to utilize media processing hardware circuitry hosted by the apparatus to perform the media processing portion.

The invention discloses a variable frequency phase shift control DAB type single-stage inverter reactive power control method, system and device and a medium, and belongs to the technical field of power electronic converter control, and the method comprises the steps: setting a reactive power instruction as zero; when the reactive power instruction changes, the active power instruction and the reactive power instruction at the current moment are decomposed into a direct-axis current reference value and a quadrature-axis current reference value respectively; comparing the reference value with an actual sampling value, calculating an error compensation amount by using a PI controller, and determining the amplitude and phase of the AC side current according to the compensation amount; according to the amplitude and the phase of the voltage and the current, a DAB frequency conversion phase shift control curve is calculated; and generating a PWM (Pulse Width Modulation) signal according to the frequency conversion phase shift control curve obtained by calculation, wherein the PWM signal is used for driving a DAB inverter to carry out power transmission. According to the invention, on the premise that no extra hardware circuit is introduced, dynamic adjustment and accurate control of the instantaneous reactive power of the AC output side can be realized.

The invention provides a task sending method and device and a task execution method and device, relates to the field of computers, and solves the problem that the time delay of a processor running program is relatively large. According to the specific scheme, multiple tasks and task issuing modes are obtained; and if the task issuing mode is non-list issuing and the sending task descriptor satisfies a memory barrier-free condition, sending the sending task descriptor to the hardware circuit, the sending task descriptor being used for indicating processing information of at least one task in the plurality of tasks, and the memory barrier-free condition being used for indicating a data volume that can be processed by the processor core in one period. Therefore, the time consumption caused by executing the memory barrier operation can be reduced, and the time delay when the processor runs the program is reduced.

The invention relates to a distributed calculation method and system for DCS system data based on a multi-task CPU, and the method employs the cooperation of a kernel operation CPU unit, an I / O communication unit and a diagnosis unit, and can achieve the purposes: improving the stability of the system through avoiding the occurrence of a parking event caused by a non-hardware fault of the DCS system; based on a DCS intelligent diagnosis model, the system is responsible for completing software and hardware intelligent diagnosis of a DCS control module and outputting a control strategy to monitor each hardware circuit and software operation condition of the control module so as to realize real-time and accurate diagnosis of the system state, realize intelligent diagnosis of the DCS system and reduce the management difficulty of the DCS system. The multiple CPUs work cooperatively, tasks are processed in a partitioned mode, the operation load of the single CPU can be reduced, work of other parts cannot be affected after the single CPU breaks down, and the operation capacity and stability of the DCS system control module are improved.

The invention relates to the technical field of chip packaging, in particular to a PCIe (peripheral component interface express) equipment function number border crossing prevention method supporting ARI (automatic repeat interface). The hardware layer protection process is as follows: S1-1, hot plugging; s1-2, if it is detected that the equipment declarates to support ARI, the PCIe controller hardware circuit immediately sets an equipment number register to zero; s1-3, only allowing the PCIe controller of the system to read the configuration space unidirectionally during the low level period of the reset signal PERST #; the interception process of the driving layer is as follows: S2-1, in an equipment enumeration stage, an operating system drives to dynamically read an ARI capability register; s2-2, if the equipment declarates to support ARI, forcing an equipment number register to be equal to 0, and releasing an original equipment number bit space for function number expansion; s2-3, border crossing access is blocked; and S2-4, synchronizing the state register. Compared with the prior art, correctness of device function numbers is guaranteed through two dimensions of hardware register state solidification and driver layer access truncation, and'perception-free 'fault tolerance of the PCIe device under ARI / traditional mode switching is achieved for the first time.

An apparatus to facilitate redundant parallel computing structures as a cache is disclosed. The apparatus includes redundant parallel computing hardware circuitry comprising redundant sets of computing combinatorial logic and register-based storage circuitry; and crossbar fabric connected to the registers of the redundant parallel computing hardware circuitry, wherein the crossbar fabric to cause register state of the register-based storage circuitry to be selected based on a tagged cache model.

The invention relates to the field of cell analysis, and provides a multi-mode digital micro-fluidic system and method for cell sorting analysis, the system comprises an active digital micro-fluidic platform, the active digital micro-fluidic platform comprises a micro-fluidic chip, an upper computer control system and an FPGA hardware circuit, an upper computer generates a liquid drop path planning instruction, the FPGA hardware circuit converts the liquid drop path planning instruction into an electrode driving signal, and the electrode driving signal is transmitted to the micro-fluidic chip; the nanoliter-grade liquid drops are driven to change between the electrodes; the optical tweezers platform comprises a laser device, an optical microscope and a CMOS camera, laser beams are generated by the laser device to form a three-dimensional optical potential well, the laser beams are transmitted into the micro-fluidic chip through the optical microscope to realize non-contact control on cells, and the CMOS camera records images and transmits the images back to the upper computer; the objective table clamp is used for realizing cooperative control of the optical tweezers and the active digital microfluidics; and the image recognition system is used for recognizing morphological characteristics of cells in the liquid drops based on a convolutional neural network and screening target cells. According to the invention, integration of high-throughput nondestructive cell sorting and in-situ multi-modal analysis is realized.

The invention relates to a power device driving fault detection circuit and a use method thereof. The power device driving fault detection circuit comprises a control circuit, an inverter circuit, a first comparator, a second comparator and a detection circuit, the control circuit outputs a complementary signal to drive a power device in the inverter circuit, and the inverter circuit supplies power to post-stage equipment and provides a voltage signal for the comparator; the first comparator detects grid and source voltage of the upper bridge power device, the second comparator detects grid and source voltage of the lower bridge power device, and results are input into the detection circuit. The detection circuit uses a logic gate to determine whether the upper and lower bridge arm power devices are simultaneously conducted or not so as to realize dead zone detection. According to the system, hardware circuits and excessive controller pins do not need to be added, the detection process is safe, and large current cannot be generated.

The invention provides a protocol decoding and triggering method based on envelope detection, a digital oscilloscope and a medium, relates to the technical field of digital signal processing, and is used for solving the problems of speed, accuracy and cost in a protocol decoding and triggering process. The method is applied to the digital oscilloscope. The digital oscilloscope comprises a hardware circuit and upper computer software; the method comprises the following steps: a hardware circuit performs envelope detection on a collected original signal to obtain an effective data packet; the upper computer software performs level conversion on the effective data packet according to a preset level threshold value to obtain a binary data packet; the upper computer software searches protocol frame headers of the binarized data packets according to frame header characteristics of different protocols; and the upper computer software performs protocol decoding and protocol triggering on the binarized data packet by taking a protocol frame header as a starting point. According to the method, based on hardware pre-triggering of envelope detection, analysis on invalid data packets can be reduced, the protocol decoding and triggering efficiency and accuracy are improved, and extra hardware cost is not needed.