155 results about "Hardware description language" patented technology

The invention discloses a Multi-Point CTS-based chip clock design optimization method, and relates to the technical field of chip clock design optimization, and the method comprises the following steps: using a hardware description language VHDL to compile RTL codes describing circuit behaviors, using a DC EDA tool of Synopsys to convert the RTL codes into a logic netlist, using a standard algorithm H-Tree to construct a preliminary clock tree structure layout, and using the standard algorithm H-Tree to construct the logic netlist. Obtaining a primary clock tree topological graph; a Multi-Point CTS method is introduced, a plurality of clock sources are adopted to optimize the initial clock tree topological graph, and an optimized clock tree topological graph is obtained; a static time sequence analysis tool PrimeTime is adopted to analyze the optimized clock tree topological graph, and a time sequence analysis result is obtained; identifying the longest path from a clock source to a register in the optimized clock tree topological graph according to a time sequence analysis result, marking the longest path as a critical path, and finding the optimal position for placing a buffer in the critical path by adopting a heuristic search algorithm; and calculating a difference value between the actual delay and the maximum allowable delay of the optimized clock tree topological graph by using PrimeTime again.

The invention provides a digital-analog hybrid simulation method and simulator based on a QEMU, a SystemC and a SystemC-AMS. The digital-analog hybrid simulation method comprises the following steps: adding an external memory access interface and a time sequence synchronization interface in the QEMU; the method comprises the following steps: constructing a virtual CPU (Central Processing Unit) device in a SystemC; a register interface function and a logic signal function are realized by adopting a systemc model in the equipment, and a port analog signal function is realized by adopting a systemc-am model; the starting parameters are analyzed in the main program, and the simulation component is loaded; executing a virtual target machine instruction in the instruction core environment; switching to a systemc running environment, changing the value of an on-chip device register, and updating the logic function state and the port state of the device; and exiting from the systemc operation environment, and entering the operation environment of the instruction core again. The technical advantages of the QEMU, the SystemC and the SystemC-AMS are combined, a QEMU instruction set is reused, meanwhile, the hardware description language characteristics of the SystemC and the analog signal processing capacity of a simulation scheduler and the SystemC-AMS are utilized, digital-analog hybrid simulation is achieved, and the verification efficiency and accuracy of SoC design are improved.

The invention provides a multilayer substrate via hole electrothermal coupling model construction method considering temperature change parameter change, and relates to the technical field of microelectronics. Comprising the following steps: constructing a # imgabs0 # lumped parameter equivalent circuit model corresponding to a multi-layer substrate via hole structure according to a size parameter, a material parameter and a multi-layer equivalent circuit network cascade mode of the multi-layer substrate via hole structure; constructing an equivalent thermal circuit model corresponding to the multi-layer substrate via hole structure according to the size parameters, the material parameters and the temperature nodes between the adjacent layers of the multi-layer substrate via hole structure; and connecting the # imgabs1 # lumped parameter equivalent circuit model with the equivalent thermal circuit model by utilizing a hardware description language, and establishing a multilayer substrate via hole electrothermal coupling model, so as to obtain the steady-state temperature of the substrate via hole by utilizing the multilayer substrate via hole electrothermal coupling model. Therefore, the temperature change of the via hole can be accurately obtained, the occupied computing resource + is less, and the computing time is shorter.

The invention belongs to the technical field of cross application of an artificial intelligence large language model and hardware design, and provides a hardware design-oriented special large model aided design method and system, and the method comprises the steps: obtaining an original code data set; the original code data set is preprocessed, and a hardware description language code database meeting the hardware design requirement is constructed and obtained; generating a multi-level code description pair data set based on the hardware language code database meeting the hardware design requirements and the constructed multi-level description mechanism; wherein the construction process of the multi-level description mechanism comprises the step of constructing a special large language model designed for hardware on the basis of a multi-level code description pair data set. The large language model can better meet the requirements of the hardware design field, the accuracy and reliability of the generated content are improved, and powerful support is provided for development of hardware design.

The invention relates to a GPU system verification method and device, electronic equipment, a storage medium and a program product. The method comprises the following steps: obtaining a target random test excitation sequence; respectively inputting the target random test excitation sequence into the GPU function model and the register transfer level model; wherein the GPU function model is a software model used for simulating functions of the GPU; the register transfer level model is a model written based on a hardware description language, and the register transfer level model is used for describing hardware implementation and behaviors of the GPU; obtaining a function simulation result output by the GPU function model in response to the target random test excitation sequence and a simulation result output by the register transfer level model in response to the target random test excitation sequence; and comparing the function simulation result with the simulation result to obtain a first random verification result of the GPU system. According to the method and the device, the GPU system verification flexibility can be remarkably improved.

A computer-implemented technique for generating program code includes receiving a natural language description of a hardware module, generating a first plan based on the natural language description, extracting first circuit information from the natural language description, generating a second plan based on the first plan and the first circuit information, and generating first program code in a hardware description language based on the second plan.

The invention provides a code processing method and device of an integrated circuit, electronic equipment and a storage medium. The method comprises the steps that a source code is obtained, the source code comprises parameter information of a sub-module in the integrated circuit, and the source code is a register transfer level code; constructing a structured encapsulation unit tree based on the source code; packaging the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; and in response to the received connection instruction, code generation is performed based on the connection instruction and the hardware description language module to obtain a connection code, the connection instruction comprises a connection relationship between the sub-modules in the integrated circuit, the connection code indicates a signal transmission path between the sub-modules in the integrated circuit, and the connection code is a hardware description language code. According to the invention, the connection efficiency of signal transmission paths between modules in an integrated circuit design can be improved.

The present invention relates to a method and framework for designing of VLSI circuit using graphical user interface. The method comprises of selecting one or more components from a design tool bar module and / or a user library module configured within a graphical user interface (GUI) for creating a system / circuit design; providing connectivity information representing interconnections or interface between the selected components of the system design over a design plane or form by the user; specifying input and output ports information for the system design; specifying a hardware description language (HDL) from plurality of HDLs for HDL code generation into a hardware description language module; a timing waveform creation module configured to generate timing waveforms representing digital signals of the generated design; a low power intent module to low power circuit design, and generating the power intent into a UPF.

The invention relates to a redundant code identification method and device, computer equipment and a readable storage medium. The method comprises the following steps: acquiring a compiled initial hardware description language code, compiling the initial hardware description language code, performing code rule check on the compiled initial hardware description language code, performing simulation analysis and code coverage rate analysis on the compiled hardware description language code, and performing simulation analysis and code coverage rate analysis on the compiled hardware description language code. And identifying and marking the uncovered target hardware description language codes, identifying redundant codes in the target hardware description language codes according to the marking information of the target hardware description language codes, and processing the redundant codes. By adopting the method, the redundant codes can be effectively identified and processed, the code quality and the system performance are improved, and the reliability and maintainability of the system are enhanced.

The invention relates to a fully homomorphic logic circuit encryption method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a hardware description language and encrypted data of a client; converting the hardware description language into a gate-level circuit netlist, mapping the gate-level circuit netlist into a lookup table network, performing operator matching on each lookup table node in the lookup table network according to a truth table corresponding to each lookup table node, and determining an operator of each lookup table node; traversing all the lookup table nodes, merging the lookup table nodes meeting a preset merging condition to obtain an optimized network topology, performing ciphertext format conversion on the encrypted data to obtain encrypted data in a target format, and using the optimized network topology to obtain the encrypted data in the target format. And based on the operator of each lookup table node, carrying out operation on the encrypted data in the target format to obtain an operation result. Therefore, the problems that an encryption computing framework is low in computing efficiency and difficult to meet diversified application requirements are solved, and the computing efficiency of a logic circuit can be improved.

The invention aims to provide a Bayesian optimization-based EDA (Electronic Design Automation) tool parameter automatic tuning method and system. The method comprises the following steps of: setting a process library file, a hardware description language code of chip design and a constraint file, and configuring a parameter space formed by EDA tool parameters; inputting the process library file, the hardware description language code of the chip design, the constraint file and the parameter space into DGPSPMBO; and the DGPSPMBO outputs a chip layout design according to a diversity-guided multi-target Bayesian optimization framework. According to the method, important parameters are selected to ensure that optimization is concentrated on the most effective parameter dimension, and the search accuracy is improved. And meanwhile, a parallel optimization strategy considering parameter space and PPA index diversity is introduced, and exploration is guided by utilizing a batch selection mechanism and combining a hyper-volume improvement index, so that exploration is more sufficient, and a plurality of EDA tool parameter combinations capable of realizing high-quality chip design can be quickly and accurately found.

The embodiment of the invention is suitable for the technical field of digital circuits, and provides a circuit analysis method and device, electronic equipment and a computer program product, and the method comprises the steps: obtaining description information of a to-be-analyzed circuit in different description modes; the description information in different description modes at least comprises a function abstract corresponding to a text description mode, a circuit diagram corresponding to a graphic description mode and a hardware description language corresponding to a programming language description mode; performing feature fusion on the single-mode features obtained based on the description information to generate fusion features of the circuit to be analyzed; inputting the fusion features into an analysis model, and generating an analysis result corresponding to the circuit to be analyzed; the analysis result corresponding to the analysis circuit comprises a correlation circuit corresponding to the to-be-analyzed circuit and / or a prediction index corresponding to the to-be-analyzed circuit. According to the method provided by the embodiment of the invention, the circuit to be analyzed can be analyzed according to the characteristics under various description information, so that the analysis accuracy of the circuit is improved.

The invention relates to a hardware description language generation method and system based on a large language model, and the method comprises the following steps: S1, generating an initial digital circuit design code by adopting the large language model; s2, performing grammar verification on the initial digital circuit design code to obtain grammar verification information; s3, correcting the initial digital circuit design code according to the grammar verification information to obtain a corrected digital circuit design code; s4, performing simulation verification on the corrected digital circuit design code to obtain simulation verification information; s5, judging whether the large language model needs to be optimized or not according to the simulation verification information, if yes, optimizing the large language model, and returning to execute the step S1 after the large language model is optimized; if not, outputting a corrected digital circuit design code, and storing the corrected digital circuit design code to a sample database; according to the method, a'generation-verification-optimization 'closed-loop architecture is constructed, and the code error rate is reduced.

The invention relates to the technical field of integrated circuit design, and discloses a storage design analysis method and device, a medium and a program product. The method comprises the following steps: acquiring a hardware description language design file, and identifying each random access memory module in the hardware description language design file according to a preset grammar definition; abstracting each random access memory module into a structured model, wherein the structured model comprises a plurality of read-write port models; and obtaining target parameters matched with the read-write port models corresponding to the structured models, and obtaining memory classifications corresponding to the structured models according to the target parameters matched with the read-write port models. According to the scheme of the embodiment, efficient analysis of the storage design can be achieved in the RTL compiling stage, and the analysis efficiency of the storage design can be improved.

The invention provides a system-level design generation method and system based on AI-Agent. The method provided by the invention comprises the following steps: receiving design demand information input by a user; carrying out system-level architecture design and system segmentation on the design demand information based on the AI-Agent, generating a system architecture scheme, design prompt information and a constraint file, and carrying out feasibility verification on the system architecture scheme by generating a rule checking mechanism to obtain the system architecture scheme, the design prompt information and the constraint file which pass verification; matching a corresponding path generation method based on the design prompt information passing verification or a Python algorithm code input by a user, and generating a hardware description language code based on the path generation method; and performing function verification on the hardware description language code, connecting the hardware description language code passing the function verification and the constraint file passing the verification with a back-end tool, performing layout wiring, and outputting a GDS-II layout file.

The invention discloses an FPGA (Field Programmable Gate Array) self-excitation signal detection method and device based on a signal feedback loop, and the method comprises the steps: firstly, reading a received FPGA hardware description language code file, and integrating all modules in an FPGA code to form an overall code file from top to bottom; secondly, mapping the overall code file of the FPGA into a signal transmission network according to a transmission relationship among signals in the overall code file of the FPGA; and thirdly, searching all signal feedback loops in the signal transmission network, calculating signal feedback probabilities, selecting and recording the signal feedback loops of which the signal feedback probabilities are greater than a set threshold, and extracting signals in the signal feedback loops as self-excitation signals to be output. According to the method, the self-excitation signal in the FPGA design and the occurrence probability of the self-excitation signal can be effectively detected, the method is easy to use and low in investment cost, and the requirement for self-excitation signal detection when the triple modular redundancy design is carried out can be well met.

The invention provides a hardware description language code generation system based on TypeScript, comprising a configuration conversion unit, a type verification unit, a parameter calculation unit, an intermediate representation construction unit and a code generation unit, through a type system of TypeScript, type inconformity can be effectively captured in a coding stage, illegal configuration with parameter type inconformity is effectively intercepted, and the code generation efficiency is improved. Therefore, the design error risk and the later debugging cost are reduced; meanwhile, based on the object-oriented characteristic of the TypeScript, the target hardware description language code with the structured hierarchy can be generated, so that the readability of the target hardware description language code is high, and then the maintainability and development efficiency of hardware design are improved.

The specification relates to the technical field of computers, in particular to a transaction processor implementation method and device in a simulation acceleration platform. The method comprises: based on the functional requirements of a transaction processor to be developed, analyzing the functional logic of a verification component UVC in a simulation environment, which is related to the functional requirements; converting the time sequence related transaction processing logic in the functional logic into hardware description language code, loading the hardware description language code into the hardware resources of the simulation acceleration platform to obtain the hardware part of the transaction processor; converting the dynamic resources and control logic in the functional logic into software code and packaging it as a function that can be called through a direct programming interface DPI as the software part of the transaction processor. The method avoids the huge workload required for developing a transaction processor from scratch for a simulation acceleration platform, and realizes the migration and reuse of verification assets between different verification platforms.

The present application relates to a kind of kernel driving method under embedded real-time operating system, belong to embedded real-time operating system field.The method of the present application uses bus type driving framework to combine device tree mechanism, realizes the separation of driving code and hardware configuration information, to build kernel driving model;Wherein, bus type driving framework divides the driving of a certain device into two independent parts: bus driver and device driver;Device tree mechanism separates hardware configuration information from kernel code and driver program, and provides a standardized hardware description language to maintain hardware information, so that developers quickly understand hardware resource allocation;Through device tree mechanism, specific information of hardware device is dynamically transmitted to operating system, without using conditional compilation or static configuration hard coding.The present application realizes the standardization of hardware description, the generalization of driving code, to greatly improve the portability, maintainability and stability of embedded real-time operating system driving.

The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and / or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

The invention discloses a computing task processing method and device, a medium and a product, and relates to the technical field of integrated circuits. According to the scheme, an FMA unit is designed by adopting a hardware description language, and the direct scheduling capability of hardware is supported; when a plurality of calculation requests are received, storing each corresponding calculation task into a hardware queue, and respectively determining scheduling information of each calculation task; the scheduling information comprises hardware scheduling and software scheduling, that is, the scheme supports two scheduling modes of software and hardware; when the scheduling information of the calculation task is hardware scheduling, the target FMA unit is determined according to the hardware resource use condition of each FMA unit, and the calculation task is distributed to the target FMA unit, so that the target FMA unit executes the calculation task, task balancing based on FMA unit resources is realized, and the calculation efficiency and the FMA resource utilization rate are improved.

The application relates to the field of photonic device modeling, and discloses a parameterized optoelectronic joint simulation platform construction method for optoelectronic chip design, which is characterized in that, in an electronic design automation platform, a unified model framework of a photonic device is constructed based on a hardware description language, and conversion between frequency domain response and time domain response is realized in the model, including the following steps: a general VerilogA model framework is constructed based on the frequency domain response of the photonic device; a frequency-time domain numerical conversion mechanism is realized in the model; and for the photonic device with dispersion characteristics, a parameterized time domain model is constructed based on a finite impulse response. The application can directly embed the photonic device model into an electronic circuit simulation environment, co-simulate the electronic device, support time-frequency domain analysis of the cascade structure and the loop structure, thereby avoiding the complicated steps of separate simulation by relying on external simulation tools in the process of optoelectronic chip design, and further improving the design efficiency and iteration speed of the chip.

The application discloses a FIFO interface multi-channel DMA controller based on FPGA, which comprises an input data distribution module, an input data cache module, an output data distribution module, an output data cache module, a DMA scheduling module, a DDR output module and a DDR interface module; is used for caching multi-channel high-speed data of multiple data sources in a memory, does not occupy on-chip RAM resources of the FPGA, realizes parallel, independent and efficient storage and storage of multi-channel data, a data interaction interface is a standard FIFO interface, a user does not need to care about complex DDR3 / 4 (Double Data Rate) interface timing and multi-channel data scheduling, programming is realized by using a hardware description language, parameterization configuration is adopted, other FPGA platforms are compatible, the application can be called in FPGA design as an IP, a development cycle is shortened, and development efficiency is improved.

The invention relates to a method for performing static inspection on hardware description language codes, which is characterized in that an accurate chip object model is constructed and a submodule interface model is utilized to perform efficient cross-module analysis, so that the inspection speed is effectively improved, and time consumption caused by complete analysis of whole design details in a traditional method is avoided; meanwhile, deep semantic level analysis is carried out based on the object model, so that the false report rate and the missing report rate are effectively reduced, and the problem positioning accuracy is improved; besides, by carrying out intelligent classification and priority ranking on inspection results and supporting unified inspection on design and verification codes, user experience is greatly optimized, the error correction time of engineers is shortened, and therefore the efficiency and quality of chip design early-stage defect discovery are comprehensively improved.

A novel data generation system is provided, which includes a first data processing device having a function of generating a netlist by converting a hardware description language into graph-structured data and performing arithmetic processing based on Monte Carlo tree search, a second data processing device having a function of converting the graph-structured data into matrix data using a graph neural network, and a third data processing device including a transformer model and generating a first command in accordance with an input token sequence. The first data processing device has a function of generating a random number, and as a command executed in the Monte Carlo tree search, the first command or a second command selected using a calculation formula of action selection is selected in accordance with a magnitude relationship between the random number and a specified value.

A preferably computer-implemented method of prioritizing test cases, the method comprising: obtaining a test case coverage for each of a plurality of test cases for testing an integrated circuit, for example in a hardware description language, preferably on a register transfer level; the priority of each test case is determined based on the corresponding test case coverage rate, and the priorities indicate the execution sequence of the test cases.

This invention discloses a method and apparatus for FPGA code similarity detection based on weighted directed graphs. The method includes: reading two FPGA hardware description language code modules to be detected; constructing corresponding directed graphs based on the data flow relationships within the two modules; weighting the edges of the directed graphs to obtain a weighted directed graph; obtaining the corresponding weighted adjacency matrix; performing same-dimensional processing on the weighted adjacency matrices of the two modules to obtain same-dimensional weighted adjacency matrices of the two modules; calculating the total feature value of the weighted adjacency matrices; subtracting the same-dimensional weighted adjacency matrices of the two modules and performing weighted processing to obtain the feature difference; and calculating the similarity between the two modules based on the feature difference and the total feature value. This method is easy to implement, can be easily automated by computer, has high detection efficiency, and can well meet the needs of the FPGA software testing industry for test case reuse.

The invention relates to the technical field of nonvolatile memory chips, and discloses a verification method and device for a FLASH memory and a universal verification platform, and the simulation verification method comprises the steps: carrying out the modeling of a signal time sequence in the form of an executable task of a hardware description language based on the time sequence requirement of an operation manual of a target FLASH memory, defining a key time interval between the signals as a configurable parameter; performing parameter configuration on the executable task and the key time interval according to a parameter value input by a user for adapting to the target FLASH memory; according to the configured executable task and the key time interval, generating simulation data, and according to the simulation data, simulating the to-be-tested design of the target FLASH memory model; in the simulation process, a time sequence signal, a voltage signal and a decoding logic signal in a to-be-tested design are checked according to parameterized time sequence requirements. According to the invention, the accuracy and efficiency during simulation verification can be improved.

Providing a new data generation system. [Solution] The system includes a first data processing device that has the function of converting a hardware description language into graph structure data and generating a netlist by performing calculations based on Monte Carlo tree search; a second data processing device that has the function of converting the graph structure data into matrix data based on a graph neural network; and a third data processing device that has a transformer model and generates a first command according to the input token sequence. The first data processing device has the function of generating random numbers, and the command to be executed in Monte Carlo tree search is selected based on the relationship between the random number and a specified value, either as a first command or as a second command selected based on a calculation formula for action selection.

A computer-implemented method for generating program code involves receiving a natural language description of a hardware module, generating an initial schematic based on the natural language description, extracting initial circuit information from the natural language description, generating a second schematic based on the first schematic and the initial circuit information, and generating initial program code in a hardware description language based on the second schematic.