63 results about "Hardware description language" patented technology

A computer-implemented technique for generating program code includes receiving a natural language description of a hardware module, generating a first plan based on the natural language description, extracting first circuit information from the natural language description, generating a second plan based on the first plan and the first circuit information, and generating first program code in a hardware description language based on the second plan.

The invention provides a code processing method and device of an integrated circuit, electronic equipment and a storage medium. The method comprises the steps that a source code is obtained, the source code comprises parameter information of a sub-module in the integrated circuit, and the source code is a register transfer level code; constructing a structured encapsulation unit tree based on the source code; packaging the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; and in response to the received connection instruction, code generation is performed based on the connection instruction and the hardware description language module to obtain a connection code, the connection instruction comprises a connection relationship between the sub-modules in the integrated circuit, the connection code indicates a signal transmission path between the sub-modules in the integrated circuit, and the connection code is a hardware description language code. According to the invention, the connection efficiency of signal transmission paths between modules in an integrated circuit design can be improved.

The invention provides a system-level design generation method and system based on AI-Agent. The method provided by the invention comprises the following steps: receiving design demand information input by a user; carrying out system-level architecture design and system segmentation on the design demand information based on the AI-Agent, generating a system architecture scheme, design prompt information and a constraint file, and carrying out feasibility verification on the system architecture scheme by generating a rule checking mechanism to obtain the system architecture scheme, the design prompt information and the constraint file which pass verification; matching a corresponding path generation method based on the design prompt information passing verification or a Python algorithm code input by a user, and generating a hardware description language code based on the path generation method; and performing function verification on the hardware description language code, connecting the hardware description language code passing the function verification and the constraint file passing the verification with a back-end tool, performing layout wiring, and outputting a GDS-II layout file.

The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and / or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

The application relates to the field of photonic device modeling, and discloses a parameterized optoelectronic joint simulation platform construction method for optoelectronic chip design, which is characterized in that, in an electronic design automation platform, a unified model framework of a photonic device is constructed based on a hardware description language, and conversion between frequency domain response and time domain response is realized in the model, including the following steps: a general VerilogA model framework is constructed based on the frequency domain response of the photonic device; a frequency-time domain numerical conversion mechanism is realized in the model; and for the photonic device with dispersion characteristics, a parameterized time domain model is constructed based on a finite impulse response. The application can directly embed the photonic device model into an electronic circuit simulation environment, co-simulate the electronic device, support time-frequency domain analysis of the cascade structure and the loop structure, thereby avoiding the complicated steps of separate simulation by relying on external simulation tools in the process of optoelectronic chip design, and further improving the design efficiency and iteration speed of the chip.

A novel data generation system is provided, which includes a first data processing device having a function of generating a netlist by converting a hardware description language into graph-structured data and performing arithmetic processing based on Monte Carlo tree search, a second data processing device having a function of converting the graph-structured data into matrix data using a graph neural network, and a third data processing device including a transformer model and generating a first command in accordance with an input token sequence. The first data processing device has a function of generating a random number, and as a command executed in the Monte Carlo tree search, the first command or a second command selected using a calculation formula of action selection is selected in accordance with a magnitude relationship between the random number and a specified value.

A preferably computer-implemented method of prioritizing test cases, the method comprising: obtaining a test case coverage for each of a plurality of test cases for testing an integrated circuit, for example in a hardware description language, preferably on a register transfer level; the priority of each test case is determined based on the corresponding test case coverage rate, and the priorities indicate the execution sequence of the test cases.

The invention relates to the technical field of nonvolatile memory chips, and discloses a verification method and device for a FLASH memory and a universal verification platform, and the simulation verification method comprises the steps: carrying out the modeling of a signal time sequence in the form of an executable task of a hardware description language based on the time sequence requirement of an operation manual of a target FLASH memory, defining a key time interval between the signals as a configurable parameter; performing parameter configuration on the executable task and the key time interval according to a parameter value input by a user for adapting to the target FLASH memory; according to the configured executable task and the key time interval, generating simulation data, and according to the simulation data, simulating the to-be-tested design of the target FLASH memory model; in the simulation process, a time sequence signal, a voltage signal and a decoding logic signal in a to-be-tested design are checked according to parameterized time sequence requirements. According to the invention, the accuracy and efficiency during simulation verification can be improved.

Providing a new data generation system. [Solution] The system includes a first data processing device that has the function of converting a hardware description language into graph structure data and generating a netlist by performing calculations based on Monte Carlo tree search; a second data processing device that has the function of converting the graph structure data into matrix data based on a graph neural network; and a third data processing device that has a transformer model and generates a first command according to the input token sequence. The first data processing device has the function of generating random numbers, and the command to be executed in Monte Carlo tree search is selected based on the relationship between the random number and a specified value, either as a first command or as a second command selected based on a calculation formula for action selection.

A computer-implemented method for generating program code involves receiving a natural language description of a hardware module, generating an initial schematic based on the natural language description, extracting initial circuit information from the natural language description, generating a second schematic based on the first schematic and the initial circuit information, and generating initial program code in a hardware description language based on the second schematic.

Analysis may be performed on hardware description language (HDL) code to identify a violation, where the HDL code may describe an IC design, and where the violation may specify a line in the HDL code. The HDL code may be parsed to obtain a digital representation of the IC design. Connectivity information and semantic information of objects in the digital representation may be determined. A first object in the digital representation may be determined which corresponds to the line in the HDL code. The connectivity information and the semantic information may be used to identify a set of objects in the digital representation which are related to the first object. A set of lines in the HDL code may be selected which correspond to the set of objects in the digital representation.

A, preferably computer-implemented, method of verifying a design of an electronic circuit, comprising the steps of: prompting a large language model, LLM, with a design description in a machine-readable form, for example a hardware description language, HDL, for the LLM to provide one or more expressions specifying an intended functioning of the design in a natural language, prompting the same or another LLM with the one or more expressions for the LLM to provide one or more properties of the design in a machine-readable property description, for example a hardware verification language, HVL.

This application belongs to the field of FPGA technology and relates to an automated FPGA component code generation method and terminal. The invention replaces the manual writing of traditional hardware description languages ​​by defining FPGA application components with interfaces, creating component instances with configuration logic information, and establishing port connections, enabling non-professionals to participate in development. Then, based on the Eclipse PDE configuration trigger mechanism, the model information is collected through action execution classes and the generator is called to automatically create projects, generate configuration files, and complete placeholder replacement, realizing the automated conversion from modeling to code. This avoids the burden of detailed descriptions written manually and errors caused by human negligence, improves development efficiency, and reduces debugging costs. Furthermore, the unified modeling specifications and generation process replace various tools and specifications, ensuring development consistency to improve collaboration efficiency and facilitate subsequent maintenance and iteration. At the same time, it solves the defect of existing visualization tools that can only display but cannot automatically convert code.

The application provides a code processing method and device of an integrated circuit, electronic equipment and a storage medium. The method comprises: obtaining source code, wherein the source code contains parameter information of a sub-module in the integrated circuit, and the source code is register transfer level code; constructing a structured packaging unit tree based on the source code; performing packaging processing on the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; and in response to receiving a connection instruction, performing code generation based on the connection instruction and the hardware description language module to obtain connection code, wherein the connection instruction comprises a connection relationship between the sub-modules in the integrated circuit, the connection code indicates a signal transmission path between the sub-modules in the integrated circuit, and the connection code is hardware description language code. Through the application, the efficiency of connecting the signal transmission path between the modules in the integrated circuit design can be improved.

The present disclosure relates to a method and a system for creating and debugging a silicon production test program for a semiconductor device. The method includes running a pre-silicon test program for testing a semiconductor device under test based on a plurality of test plan parameters. The method includes converting the pre-silicon test program from a hardware description language to a high-level programming language in response to determining that the pre-silicon test program is created in the hardware description language. The method includes integrating the pre-silicon test program with a bench board test program or an automated test equipment (ATE) test program, and mapping Application Programming Interface (API) resources available in the pre-silicon test program to one or more resources available in the bench board test program or the ATE test program during integration. The method includes testing and debugging the semiconductor device under test using an emulation platform.

The application provides an SRAM module splicing method and device in a chip, the method comprising: performing a screening operation on an SRAM basic unit instance set to obtain a candidate basic unit set; sequentially taking each SRAM basic unit in the candidate basic unit set as a splicing main body, determining the maximum instantiation number and the current remaining capacity of the splicing main body, cyclically selecting an SRAM basic unit with a capacity closest to the current remaining capacity for supplementary splicing and updating the remaining capacity until the remaining capacity is less than or equal to zero to form an effective splicing solution; calculating a key feature index of each effective splicing solution and determining an optimal splicing solution; and generating a hardware description language code corresponding to the optimal splicing solution to encapsulate the spliced multiple SRAM basic units into a target SRAM module. The application can improve splicing efficiency and ensure splicing quality.

An example operation may include one or more of receiving a logical model of a circuit written in a hardware description language (HDL), the logical model of the circuit comprising normalized and ratioed clocks, and simulation-efficient edge-triggered latches or flip-flops, translating the logical model of the circuit into a physical model of the circuit in the HDL via a software application, wherein the translating comprises replacing the normalized and ratioed clocks in the logical model of the circuit with a base system clock, divider logic generating hold waveforms to achieve ratioed behavior, and pulse-enabled latches, and replacing the edge-triggered latches or flip-flops with pulse-generation logic and pulse-enabled latches, executing a formal verification which determines whether the logical model of the circuit is functionally equivalent to the physical model of the circuit, and displaying results of the formal verification via a graphical user interface (GUI) of the software application.

The invention provides an aerospace SOPC system based on a Loongson LA132 soft core processor, and the system comprises an on-chip system hardware unit which takes the Loongson LA132 soft core processor as a core, carries out the RTL design through a hardware description language, and achieves the configuration, connection and integration of the processor, a memory and peripheral equipment; the Makefile software compiling unit is used for generating a program code suitable for the Loongson LA132 soft core processor and supporting customized software development and deployment; the fault-tolerant unit is used for storing a bit configuration file of the FPGA and a program code of the processor in NOR Flash through a triple redundancy storage technology, performing consistency comparison on the program code through one-out-of-three operation when the system is started, loading a correct program code to the instruction RAM module, and performing error check and correction by adopting RS (12, 8, 4) codes when the processor is accessed; and errors caused by single event upset are prevented.

Embodiments of the present disclosure provide systems and methods for fine-tuning a pretrained large language model (LLM) for generating hardware description language (HDL) code. In at least one embodiment, a first training dataset that includes correct-by-construction non-textual representation data samples is obtained, and the pretrained LLM is fine-tuned using the first training dataset to provide the fine-tuned LLM for generating HDL code.

The invention provides a splicing method and device for SRAM (Static Random Access Memory) modules in a chip, and the method comprises the following steps: carrying out screening operation on an SRAM basic unit instance set to obtain a candidate basic unit set; sequentially taking each SRAM basic unit in the candidate basic unit set as a splicing main body, determining the maximum instantiation frequency and the current residual capacity of the splicing main body, circularly selecting the SRAM basic unit of which the capacity is closest to the current residual capacity to carry out supplementary splicing and updating the residual capacity until the residual capacity is less than or equal to zero so as to form an effective splicing solution scheme; calculating a key feature index of each effective splicing solution scheme and determining an optimal splicing solution scheme; and generating a hardware description language code corresponding to the optimal splicing solution scheme so as to package the plurality of spliced SRAM basic units into a target SRAM module. The splicing efficiency can be improved, and the splicing quality can be guaranteed.

Various embodiments of the present disclosure provide a multi-layered framework for security of integrated circuits. In one example, an embodiment provides for removing one or more routing tables in a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language, comprising replacing the one or more routing tables in the RTL source code with respective programmable memory, transforming a state space of one or more embedded state machines in the RTL source code, transforming one or more portions of combinational logic in the RTL source code, and / or removing one or more portions of security-critical logic in the RTL source code, comprising replacing the one or more portions of security-critical logic in the RTL source code with respective lookup tables.

The invention discloses a construction and implementation method of a hyperbolic tangent fractional order memristor chaotic system. The method comprises the following steps: firstly, designing a fractional order magnetic control memristor model containing a hyperbolic tangent function, and constructing a fractional order memristor chaotic system based on the model; through high-resolution order parameter scanning and in combination with Lyapunov exponent spectrum, bifurcation diagram, phase diagram and complexity analysis, rich dynamic behaviors and high sensitivity of the system under order change are revealed; a difference equation model of the system is obtained through a frequency domain approximation and discretization method, digital modeling is completed on a DSP Builder platform, and hardware description language codes executable by an FPGA are automatically generated; finally, the real-time iterative operation of the system is realized on the FPGA development board, and the physical realizability of the chaotic attractor is verified through the oscilloscope. The invention provides a high-precision and low-power-consumption hardware implementation scheme for the fractional order memristor chaotic system, and is suitable for the information security fields of secret communication, image encryption and the like.

The invention provides an automatic circuit design method of a TAGE branch predictor, which comprises the following steps: constructing a superscalar front-end simulator comprising a branch prediction unit, an instruction cache, an instruction queue and a prediction information cache, and simulating processor front-end behaviors through parameterized configuration; a time sequence and combinatorial logic decoupling normal form is introduced into the branch prediction unit, the branch prediction unit is decomposed into a time sequence component and a combinatorial logic component, the time sequence component comprises a global historical register, a folding historical register and a multi-stage prediction table, and the combinatorial logic component comprises a metadata generation unit, a direction prediction unit, a table item updating unit and a historical maintenance unit; obtaining input and output data of the branch prediction unit in the execution process; and based on the input and output data, generating a hardware description language code of the combinatorial logic component by using an automatic circuit design algorithm so as to realize automatic circuit design of the TAGE branch predictor. Therefore, the design efficiency and the performance of automatically designing the branch prediction component can be improved.

The invention relates to a jump sampling device of a clock domain crossing circuit, a detection method and a modeling method. The device is applied to verification of a clock domain crossing circuit. The device is represented by a hardware description language or a software coding modeling language; the device is used for generating a hopping signal under the condition that an input clock domain detects an input level of a signal to be sampled; and sampling the hopping signal in an output clock domain, and generating a target output signal in the output clock domain under the condition of determining that the hopping signal is hopped once. By adopting the method, the accuracy of cross-clock domain modeling can be improved.

Disclosed subject matter relates to verification and debugging tool and method for providing sensitive regions around and in Register Transfer Level (RTL) code objects. The verification and debugging tool includes input interface configured to receive RTL code in Hardware Description Language (HDL). Further, verification and debugging tool includes RTL parser configured to parse RTL code, and generate abstract syntax tree representing syntactic structure of RTL code. Thereafter, verification and debugging tool includes graph converter configured to convert abstract syntax tree into RTL directed graph. Furthermore, verification and debugging tool includes visual display configured to display code blocks, each exhibiting sensitive regions. Finally, verification and debugging tool includes objects extractor configured to detect user actions related to sensitive regions. The sensitive regions are provided around and in each of RTL code objects to facilitate extraction and display of relevant information regarding dependencies and operations of RTL code upon user interactions.

The invention relates to a user datagram protocol (UDP) communication method realized based on a Vitis HLS, and belongs to the technical field of Ethernet. According to the invention, a UDP communication protocol is realized through Vitis HLS, a UDP communication module is designed on an FPGA by using a C + + high-level language, and the UDP communication module comprises a receiving module and a sending module. The receiving module and the sending module only realize partial protocols and functions used in use, including an ARP protocol, a Ping function based on an ICMP protocol, a UDP protocol and the like. Other unused protocols or functions can be further realized based on the design. According to the method, the module design of the FPGA is realized by using the Vitis HLS, so that the design efficiency can be improved, a designer does not need to master hardware description languages such as Verilog HDL and the like, and the development difficulty is reduced to a certain extent.

A computer-implemented technique for generating program code includes receiving a natural language description of a hardware module, generating a first plan based on the natural language description, extracting first circuit information from the natural language description, generating a second plan based on the first plan and the first circuit information, and generating first program code in a hardware description language based on the second plan.

The present application relates to the field of integrated circuit technology, in particular to a FPGA logic resource test method and structure based on a new BIST, comprising the following steps: determining the measured module BUT and comparison module BUC of the internal resource of the FPGA to be measured; designing the BIST circuit structure based on the hardware description language, namely: designing the test vector generator TPG, measured module BUT, comparison module BUC and output response analyzer ORA four modules of the BIST circuit based on the hardware description language through the EDA design software of the FPGA; constraining the measured module BUT and comparison module BUC modules, namely: position constraint is conducted on the measured module BUT and comparison module BUC based on the EDA design software of the FPGA; generating and downloading the bit stream file and conducting the real installation board level test verification. The present application is used for solving the problems of low test efficiency, too many test configuration times, complex built-in self-test structure, test sequence generated by TPG not random or random but not covering the full address and weak generalization of the existing FPGA internal resource test.

This invention provides a method, apparatus, computer device, and medium for implementing a multi-protocol bus interface based on a programmable system-on-a-chip (SoC). The method includes the following steps: building a minimal hardware platform based on a SoC chip containing a processor system and programmable logic, and configuring external memory for the processor system; configuring the processor system's boot process; constructing bus interface IP cores for at least two different communication protocols using a hardware description language and deploying protocol stack drivers; establishing data and control paths through the SoC chip's on-chip high-speed interconnect bus to form a hardware-software co-processing architecture; and dynamically reconfiguring the programmable logic through the processor system, time-sharing or switching the execution of different bus interface IP cores. This invention provides a highly general and scalable hardware platform paradigm for the application of heterogeneous computing systems in the embedded field.

The application discloses a kind of computing task processing method, equipment, medium and product, it is related to integrated circuit technical field.The present scheme designs FMA unit using hardware description language, supports hardware direct scheduling capability;When receiving multiple computing requests, corresponding each computing task is stored to hardware queue, and the scheduling information of each computing task is determined respectively;Scheduling information includes hardware scheduling and software scheduling, i.e.the present scheme supports two kinds of scheduling mode of software and hardware;When the scheduling information of computing task is hardware scheduling, according to the hardware resource use condition of each FMA unit, determine target FMA unit, dispatch computing task to target FMA unit, so that target FMA unit executes computing task, realizes task equalization based on FMA unit resource, improves computing efficiency and FMA resource utilization.