107 results about "Hardware description language" patented technology

A computer-implemented technique for generating program code includes receiving a natural language description of a hardware module, generating a first plan based on the natural language description, extracting first circuit information from the natural language description, generating a second plan based on the first plan and the first circuit information, and generating first program code in a hardware description language based on the second plan.

The invention provides a code processing method and device of an integrated circuit, electronic equipment and a storage medium. The method comprises the steps that a source code is obtained, the source code comprises parameter information of a sub-module in the integrated circuit, and the source code is a register transfer level code; constructing a structured encapsulation unit tree based on the source code; packaging the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; and in response to the received connection instruction, code generation is performed based on the connection instruction and the hardware description language module to obtain a connection code, the connection instruction comprises a connection relationship between the sub-modules in the integrated circuit, the connection code indicates a signal transmission path between the sub-modules in the integrated circuit, and the connection code is a hardware description language code. According to the invention, the connection efficiency of signal transmission paths between modules in an integrated circuit design can be improved.

The invention relates to a fully homomorphic logic circuit encryption method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a hardware description language and encrypted data of a client; converting the hardware description language into a gate-level circuit netlist, mapping the gate-level circuit netlist into a lookup table network, performing operator matching on each lookup table node in the lookup table network according to a truth table corresponding to each lookup table node, and determining an operator of each lookup table node; traversing all the lookup table nodes, merging the lookup table nodes meeting a preset merging condition to obtain an optimized network topology, performing ciphertext format conversion on the encrypted data to obtain encrypted data in a target format, and using the optimized network topology to obtain the encrypted data in the target format. And based on the operator of each lookup table node, carrying out operation on the encrypted data in the target format to obtain an operation result. Therefore, the problems that an encryption computing framework is low in computing efficiency and difficult to meet diversified application requirements are solved, and the computing efficiency of a logic circuit can be improved.

The invention relates to a hardware description language generation method and system based on a large language model, and the method comprises the following steps: S1, generating an initial digital circuit design code by adopting the large language model; s2, performing grammar verification on the initial digital circuit design code to obtain grammar verification information; s3, correcting the initial digital circuit design code according to the grammar verification information to obtain a corrected digital circuit design code; s4, performing simulation verification on the corrected digital circuit design code to obtain simulation verification information; s5, judging whether the large language model needs to be optimized or not according to the simulation verification information, if yes, optimizing the large language model, and returning to execute the step S1 after the large language model is optimized; if not, outputting a corrected digital circuit design code, and storing the corrected digital circuit design code to a sample database; according to the method, a'generation-verification-optimization 'closed-loop architecture is constructed, and the code error rate is reduced.

The invention provides a system-level design generation method and system based on AI-Agent. The method provided by the invention comprises the following steps: receiving design demand information input by a user; carrying out system-level architecture design and system segmentation on the design demand information based on the AI-Agent, generating a system architecture scheme, design prompt information and a constraint file, and carrying out feasibility verification on the system architecture scheme by generating a rule checking mechanism to obtain the system architecture scheme, the design prompt information and the constraint file which pass verification; matching a corresponding path generation method based on the design prompt information passing verification or a Python algorithm code input by a user, and generating a hardware description language code based on the path generation method; and performing function verification on the hardware description language code, connecting the hardware description language code passing the function verification and the constraint file passing the verification with a back-end tool, performing layout wiring, and outputting a GDS-II layout file.

The invention discloses an FPGA (Field Programmable Gate Array) self-excitation signal detection method and device based on a signal feedback loop, and the method comprises the steps: firstly, reading a received FPGA hardware description language code file, and integrating all modules in an FPGA code to form an overall code file from top to bottom; secondly, mapping the overall code file of the FPGA into a signal transmission network according to a transmission relationship among signals in the overall code file of the FPGA; and thirdly, searching all signal feedback loops in the signal transmission network, calculating signal feedback probabilities, selecting and recording the signal feedback loops of which the signal feedback probabilities are greater than a set threshold, and extracting signals in the signal feedback loops as self-excitation signals to be output. According to the method, the self-excitation signal in the FPGA design and the occurrence probability of the self-excitation signal can be effectively detected, the method is easy to use and low in investment cost, and the requirement for self-excitation signal detection when the triple modular redundancy design is carried out can be well met.

The invention provides a hardware description language code generation system based on TypeScript, comprising a configuration conversion unit, a type verification unit, a parameter calculation unit, an intermediate representation construction unit and a code generation unit, through a type system of TypeScript, type inconformity can be effectively captured in a coding stage, illegal configuration with parameter type inconformity is effectively intercepted, and the code generation efficiency is improved. Therefore, the design error risk and the later debugging cost are reduced; meanwhile, based on the object-oriented characteristic of the TypeScript, the target hardware description language code with the structured hierarchy can be generated, so that the readability of the target hardware description language code is high, and then the maintainability and development efficiency of hardware design are improved.

The specification relates to the technical field of computers, in particular to a transaction processor implementation method and device in a simulation acceleration platform. The method comprises: based on the functional requirements of a transaction processor to be developed, analyzing the functional logic of a verification component UVC in a simulation environment, which is related to the functional requirements; converting the time sequence related transaction processing logic in the functional logic into hardware description language code, loading the hardware description language code into the hardware resources of the simulation acceleration platform to obtain the hardware part of the transaction processor; converting the dynamic resources and control logic in the functional logic into software code and packaging it as a function that can be called through a direct programming interface DPI as the software part of the transaction processor. The method avoids the huge workload required for developing a transaction processor from scratch for a simulation acceleration platform, and realizes the migration and reuse of verification assets between different verification platforms.

The present application relates to a kind of kernel driving method under embedded real-time operating system, belong to embedded real-time operating system field.The method of the present application uses bus type driving framework to combine device tree mechanism, realizes the separation of driving code and hardware configuration information, to build kernel driving model;Wherein, bus type driving framework divides the driving of a certain device into two independent parts: bus driver and device driver;Device tree mechanism separates hardware configuration information from kernel code and driver program, and provides a standardized hardware description language to maintain hardware information, so that developers quickly understand hardware resource allocation;Through device tree mechanism, specific information of hardware device is dynamically transmitted to operating system, without using conditional compilation or static configuration hard coding.The present application realizes the standardization of hardware description, the generalization of driving code, to greatly improve the portability, maintainability and stability of embedded real-time operating system driving.

The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and / or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

The invention discloses a computing task processing method and device, a medium and a product, and relates to the technical field of integrated circuits. According to the scheme, an FMA unit is designed by adopting a hardware description language, and the direct scheduling capability of hardware is supported; when a plurality of calculation requests are received, storing each corresponding calculation task into a hardware queue, and respectively determining scheduling information of each calculation task; the scheduling information comprises hardware scheduling and software scheduling, that is, the scheme supports two scheduling modes of software and hardware; when the scheduling information of the calculation task is hardware scheduling, the target FMA unit is determined according to the hardware resource use condition of each FMA unit, and the calculation task is distributed to the target FMA unit, so that the target FMA unit executes the calculation task, task balancing based on FMA unit resources is realized, and the calculation efficiency and the FMA resource utilization rate are improved.

The application relates to the field of photonic device modeling, and discloses a parameterized optoelectronic joint simulation platform construction method for optoelectronic chip design, which is characterized in that, in an electronic design automation platform, a unified model framework of a photonic device is constructed based on a hardware description language, and conversion between frequency domain response and time domain response is realized in the model, including the following steps: a general VerilogA model framework is constructed based on the frequency domain response of the photonic device; a frequency-time domain numerical conversion mechanism is realized in the model; and for the photonic device with dispersion characteristics, a parameterized time domain model is constructed based on a finite impulse response. The application can directly embed the photonic device model into an electronic circuit simulation environment, co-simulate the electronic device, support time-frequency domain analysis of the cascade structure and the loop structure, thereby avoiding the complicated steps of separate simulation by relying on external simulation tools in the process of optoelectronic chip design, and further improving the design efficiency and iteration speed of the chip.

The application discloses a FIFO interface multi-channel DMA controller based on FPGA, which comprises an input data distribution module, an input data cache module, an output data distribution module, an output data cache module, a DMA scheduling module, a DDR output module and a DDR interface module; is used for caching multi-channel high-speed data of multiple data sources in a memory, does not occupy on-chip RAM resources of the FPGA, realizes parallel, independent and efficient storage and storage of multi-channel data, a data interaction interface is a standard FIFO interface, a user does not need to care about complex DDR3 / 4 (Double Data Rate) interface timing and multi-channel data scheduling, programming is realized by using a hardware description language, parameterization configuration is adopted, other FPGA platforms are compatible, the application can be called in FPGA design as an IP, a development cycle is shortened, and development efficiency is improved.

A novel data generation system is provided, which includes a first data processing device having a function of generating a netlist by converting a hardware description language into graph-structured data and performing arithmetic processing based on Monte Carlo tree search, a second data processing device having a function of converting the graph-structured data into matrix data using a graph neural network, and a third data processing device including a transformer model and generating a first command in accordance with an input token sequence. The first data processing device has a function of generating a random number, and as a command executed in the Monte Carlo tree search, the first command or a second command selected using a calculation formula of action selection is selected in accordance with a magnitude relationship between the random number and a specified value.

A preferably computer-implemented method of prioritizing test cases, the method comprising: obtaining a test case coverage for each of a plurality of test cases for testing an integrated circuit, for example in a hardware description language, preferably on a register transfer level; the priority of each test case is determined based on the corresponding test case coverage rate, and the priorities indicate the execution sequence of the test cases.

This invention discloses a method and apparatus for FPGA code similarity detection based on weighted directed graphs. The method includes: reading two FPGA hardware description language code modules to be detected; constructing corresponding directed graphs based on the data flow relationships within the two modules; weighting the edges of the directed graphs to obtain a weighted directed graph; obtaining the corresponding weighted adjacency matrix; performing same-dimensional processing on the weighted adjacency matrices of the two modules to obtain same-dimensional weighted adjacency matrices of the two modules; calculating the total feature value of the weighted adjacency matrices; subtracting the same-dimensional weighted adjacency matrices of the two modules and performing weighted processing to obtain the feature difference; and calculating the similarity between the two modules based on the feature difference and the total feature value. This method is easy to implement, can be easily automated by computer, has high detection efficiency, and can well meet the needs of the FPGA software testing industry for test case reuse.

The invention relates to the technical field of nonvolatile memory chips, and discloses a verification method and device for a FLASH memory and a universal verification platform, and the simulation verification method comprises the steps: carrying out the modeling of a signal time sequence in the form of an executable task of a hardware description language based on the time sequence requirement of an operation manual of a target FLASH memory, defining a key time interval between the signals as a configurable parameter; performing parameter configuration on the executable task and the key time interval according to a parameter value input by a user for adapting to the target FLASH memory; according to the configured executable task and the key time interval, generating simulation data, and according to the simulation data, simulating the to-be-tested design of the target FLASH memory model; in the simulation process, a time sequence signal, a voltage signal and a decoding logic signal in a to-be-tested design are checked according to parameterized time sequence requirements. According to the invention, the accuracy and efficiency during simulation verification can be improved.

Providing a new data generation system. [Solution] The system includes a first data processing device that has the function of converting a hardware description language into graph structure data and generating a netlist by performing calculations based on Monte Carlo tree search; a second data processing device that has the function of converting the graph structure data into matrix data based on a graph neural network; and a third data processing device that has a transformer model and generates a first command according to the input token sequence. The first data processing device has the function of generating random numbers, and the command to be executed in Monte Carlo tree search is selected based on the relationship between the random number and a specified value, either as a first command or as a second command selected based on a calculation formula for action selection.

A computer-implemented method for generating program code involves receiving a natural language description of a hardware module, generating an initial schematic based on the natural language description, extracting initial circuit information from the natural language description, generating a second schematic based on the first schematic and the initial circuit information, and generating initial program code in a hardware description language based on the second schematic.

Analysis may be performed on hardware description language (HDL) code to identify a violation, where the HDL code may describe an IC design, and where the violation may specify a line in the HDL code. The HDL code may be parsed to obtain a digital representation of the IC design. Connectivity information and semantic information of objects in the digital representation may be determined. A first object in the digital representation may be determined which corresponds to the line in the HDL code. The connectivity information and the semantic information may be used to identify a set of objects in the digital representation which are related to the first object. A set of lines in the HDL code may be selected which correspond to the set of objects in the digital representation.

A, preferably computer-implemented, method of verifying a design of an electronic circuit, comprising the steps of: prompting a large language model, LLM, with a design description in a machine-readable form, for example a hardware description language, HDL, for the LLM to provide one or more expressions specifying an intended functioning of the design in a natural language, prompting the same or another LLM with the one or more expressions for the LLM to provide one or more properties of the design in a machine-readable property description, for example a hardware verification language, HVL.

This application belongs to the field of FPGA technology and relates to an automated FPGA component code generation method and terminal. The invention replaces the manual writing of traditional hardware description languages ​​by defining FPGA application components with interfaces, creating component instances with configuration logic information, and establishing port connections, enabling non-professionals to participate in development. Then, based on the Eclipse PDE configuration trigger mechanism, the model information is collected through action execution classes and the generator is called to automatically create projects, generate configuration files, and complete placeholder replacement, realizing the automated conversion from modeling to code. This avoids the burden of detailed descriptions written manually and errors caused by human negligence, improves development efficiency, and reduces debugging costs. Furthermore, the unified modeling specifications and generation process replace various tools and specifications, ensuring development consistency to improve collaboration efficiency and facilitate subsequent maintenance and iteration. At the same time, it solves the defect of existing visualization tools that can only display but cannot automatically convert code.

The application provides a code processing method and device of an integrated circuit, electronic equipment and a storage medium. The method comprises: obtaining source code, wherein the source code contains parameter information of a sub-module in the integrated circuit, and the source code is register transfer level code; constructing a structured packaging unit tree based on the source code; performing packaging processing on the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; and in response to receiving a connection instruction, performing code generation based on the connection instruction and the hardware description language module to obtain connection code, wherein the connection instruction comprises a connection relationship between the sub-modules in the integrated circuit, the connection code indicates a signal transmission path between the sub-modules in the integrated circuit, and the connection code is hardware description language code. Through the application, the efficiency of connecting the signal transmission path between the modules in the integrated circuit design can be improved.

The present disclosure relates to a method and a system for creating and debugging a silicon production test program for a semiconductor device. The method includes running a pre-silicon test program for testing a semiconductor device under test based on a plurality of test plan parameters. The method includes converting the pre-silicon test program from a hardware description language to a high-level programming language in response to determining that the pre-silicon test program is created in the hardware description language. The method includes integrating the pre-silicon test program with a bench board test program or an automated test equipment (ATE) test program, and mapping Application Programming Interface (API) resources available in the pre-silicon test program to one or more resources available in the bench board test program or the ATE test program during integration. The method includes testing and debugging the semiconductor device under test using an emulation platform.

The application provides an SRAM module splicing method and device in a chip, the method comprising: performing a screening operation on an SRAM basic unit instance set to obtain a candidate basic unit set; sequentially taking each SRAM basic unit in the candidate basic unit set as a splicing main body, determining the maximum instantiation number and the current remaining capacity of the splicing main body, cyclically selecting an SRAM basic unit with a capacity closest to the current remaining capacity for supplementary splicing and updating the remaining capacity until the remaining capacity is less than or equal to zero to form an effective splicing solution; calculating a key feature index of each effective splicing solution and determining an optimal splicing solution; and generating a hardware description language code corresponding to the optimal splicing solution to encapsulate the spliced multiple SRAM basic units into a target SRAM module. The application can improve splicing efficiency and ensure splicing quality.

The present invention provides a novel information processing system that has enhanced convenience, usefulness, and reliability. The information processing system includes three components. The first component has the function of accepting a question and transmitting the question to the third component and the function of accepting and providing an answer. The second component accepts a first directive and generates an answer using a large-scale language model. The third component has the function of creating the first directive and transmitting the first directive to the second component and includes a database and a search engine. The first directive includes the question, background information, and an instruction to generate the answer to the question with reference to the background information. The database includes original data described in a programming language or a hardware description language and a summary described in a natural language. The search engine collects records associated with the question from the database to create the background information.

An example operation may include one or more of receiving a logical model of a circuit written in a hardware description language (HDL), the logical model of the circuit comprising normalized and ratioed clocks, and simulation-efficient edge-triggered latches or flip-flops, translating the logical model of the circuit into a physical model of the circuit in the HDL via a software application, wherein the translating comprises replacing the normalized and ratioed clocks in the logical model of the circuit with a base system clock, divider logic generating hold waveforms to achieve ratioed behavior, and pulse-enabled latches, and replacing the edge-triggered latches or flip-flops with pulse-generation logic and pulse-enabled latches, executing a formal verification which determines whether the logical model of the circuit is functionally equivalent to the physical model of the circuit, and displaying results of the formal verification via a graphical user interface (GUI) of the software application.

The invention discloses a construction method of a Verilog HDL (Hardware Description Language) code model and a related device. Firstly, a basic Butterworth filter and a VCode template are created in GCKontrol, and an IP core equivalent to an addition and subtraction operation unit in the filter is designed in Vivado based on service requirements. Then configuring a VCode template port to be consistent with the addition and subtraction operation unit to generate a VCode module, after the addition and subtraction operation unit is replaced, enabling a GCKontrol code generation directory to point to a Vivado path, and finally instantiating an IP core to the VCode module to complete model generation. According to the method, GCKontrol and IP core multiplexing are combined, automatic standardized code generation is achieved, manual work and skill dependence are reduced, efficiency and interface consistency are improved, and errors and development cost risks are reduced.

The invention provides an aerospace SOPC system based on a Loongson LA132 soft core processor, and the system comprises an on-chip system hardware unit which takes the Loongson LA132 soft core processor as a core, carries out the RTL design through a hardware description language, and achieves the configuration, connection and integration of the processor, a memory and peripheral equipment; the Makefile software compiling unit is used for generating a program code suitable for the Loongson LA132 soft core processor and supporting customized software development and deployment; the fault-tolerant unit is used for storing a bit configuration file of the FPGA and a program code of the processor in NOR Flash through a triple redundancy storage technology, performing consistency comparison on the program code through one-out-of-three operation when the system is started, loading a correct program code to the instruction RAM module, and performing error check and correction by adopting RS (12, 8, 4) codes when the processor is accessed; and errors caused by single event upset are prevented.

The application provides a chip pin function comparison analysis method, device and equipment and a storage medium. The method comprises the following steps: obtaining chip CPU pin SPC description data and analyzing the same, identifying a pin distribution diagram and a packaging diagram as pin diagram comparison data, extracting electrical characteristics and pin definitions, constructing an abstract syntax tree for a hardware description language code segment to extract logical functions, and obtaining pin function comparison data; performing entity alignment and knowledge fusion on a pin information set, constructing a chip knowledge graph and storing the same; extracting a target subgraph according to a chip to be compared, calling a multi-modal large model to perform visual feature alignment on pin diagram data, performing semantic logic analysis on pin function data, identifying differences, and generating a file in a preset format. Through automatic analysis and multi-modal intelligent comparison technology, the application realizes efficient and accurate comparison and analysis of chip pin functions, and solves the problems of low efficiency and errors in the traditional manual comparison method.