Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

PCIE verification method based on UVM

A verification methodology and verification method technology, applied in the direction of instruments, electrical digital data processing, computing, etc., can solve the problems of inability to reuse, low efficiency of verifying PCIE modules, and error-prone writing

Active Publication Date: 2014-01-22
丁贤根
View PDF3 Cites 43 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the process of verifying the PCIE module in the past, it is not only troublesome to regenerate various PCIE data packets, but also prone to errors in temporary writing, because the efficiency of verifying the PCIE module through the verification platform is very low and cannot be reused

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • PCIE verification method based on UVM
  • PCIE verification method based on UVM

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0027] combine figure 2 As shown, the PCIE module verification environment platform created by the present invention is completed by using the system-level hardware description language SystemVerilog: it mainly includes the following 9 components: test case, sequence generator (sequence), AXI driver module (AXI in_agent), PIPE driver Module (PIPE in_agent), AXI monitoring module (AXI out_agent), PIPE monitoring module (PIPE out_agent), PCIE reference model (reference model), scoreboard (scoreboard), functional coverage module. The UVM components are connected or communicated through ports.

[0028] The test case completes the definition of the randomization sequence, and different test cases use different sequences to verify different functions of PCIE;

[0029] The sequence generator completes the definition of the randomized data packet, including the transaction type of the transaction layer data packet, the receiver address, the order attribute, the cache consistency att...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a PCIE verification method based on the UVM. The PCIE verification method is characterized in that the UVM and a system-level hardware descriptive language are adopted, a verification environment platform is set up through a high-level extensible interface bus behavior model, functional verification is implemented on a PCIE module, and the verification environment platform comprises a test case, a sequence generator, an AXI drive module, a PIPE drive module, an AXI monitoring module, a PIPE monitoring module, a PCIE reference model, a scoreboard and a functional coverage rate module. Due to the fact that the UVM is implemented, a stratified verification structure can be obtained, the PCIE with different types of configuration can be easily transplanted and verified, random data packet excitation can be generated through constraints, all instructions and addresses can be traversed, and the functional coverage rate module can also collect and monitor the coverage rate.

Description

technical field [0001] The invention relates to a PCIE verification method based on UVM verification methodology. Background technique [0002] The rapid development of chip design and verification technology makes the functional verification of the module more and more demanding. Complete the functional verification of the module in a short time to ensure the correct logic function, which has a high impact on the completeness, automation and reusability of the verification environment. Require. [0003] PCIE is the latest and most popular bus and interface standard. Its main advantages are extremely high transmission rate and high bandwidth brought by multiple high-speed serial transmissions. The functional correctness of PCIE is crucial, especially every redesigned or modified PCIE needs to go through a lot of regression tests, and even multiple tape-outs can be actually used in the project. Therefore, the verification of PCIE usually requires a lot of time and manpower ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F11/267
Inventor 林谷赵赛李冰丁贤根
Owner 丁贤根
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com