9 results about "Special function register" patented technology

A simple configuration aims to reduce MCU vulnerabilities. [Solution] The control device 10 includes an MCU 20. The MCU 20 has a CPU 22, a system bus 26, a storage device 28, and an address translation device 24 that translates addresses between the CPU address space of the CPU 22 and the system bus address space of the system bus 26 in accordance with translation rules set in a special function register 24A. The MCU 20 starts up in an unrestricted mode in which all addresses in the CPU address space are available, and after startup, when a predetermined condition is met, it switches to a restricted mode in which only a portion of the addresses in the CPU address space are available. The special function register 24A allows the translation rules to be set and read when in the unrestricted mode, and does not allow the translation rules to be set or read when in the restricted mode.

A self-configurable traffic generator system in a System-on-Chip architecture includes a transmit special function register circuit configured to receive initial input parameters including frequency, expected bandwidth, periodicity, and latency from a silicon-dump or external target specification. A time-microscale circuit generates micro-level bandwidth targets based on one or more initial input parameters. A target-deviation circuit estimates, for each logical client, deviation between achieved bandwidth and corresponding micro-level bandwidth targets and computes adaptive weights using adaptive learning. A transactional-intelligence circuit controls one or more transaction parameters based on the adaptive weights. A transmit generation core circuit generates traffic for a plurality of clients based on the controlled one or more transaction parameters. A performance monitor circuit captures traffic information.

A control device 10 includes an MCU 20 including a CPU 22, a system bus 26, storage 28, and an address translator 24 translating an address in the CPU address space of the CPU 22 to and from an address in the system bus address space of the system bus 26 according to the translation rule set in the special function register 24A. The MCU 20 starts up in the limitation-release mode in which all addresses in the CPU address space are available, and switches to the limitation mode in which only some of the addresses in the CPU address space are available when a predetermined condition is satisfied after the start-up. For the special function register 24A, the translation rule is settable and readable in the limitation release mode, and the translation rule is neither settable nor readable in the limitation mode.

Apparatuses and methods are disclosed. The apparatus includes a bus master including processing circuitry and a bus interface. The processing circuitry is configured to control operation of the bus master such that the bus master transmits a first address to a bus slave through a bus in a first mode and to transmit a second address having a same first length as the first address to the bus slave through the bus in a second mode. The bus interface is configured to generate the second address such that the second address includes a plurality of short addresses corresponding to a plurality of special function registers of the bus slave, respectively, in the second mode.

A method of testing a storage controller included in a storage device may include supplying power to the storage device, transmitting a write command including an algorithm pattern corresponding to a designated special function register of the storage controller, transmitting a read command corresponding to the designated special function register, receiving a chip ID response corresponding to the read command, and determining whether the storage controller is defective based on the chip ID response.

Method (400, 500) for processing data in a processor (102), wherein the method comprises: in response to the occurrence of a function call instruction (410) and before executing (460) the function: Copying (420) a return address value of the function into a second general register (32); Storing (430) the return address value from the second general register (32) into a second memory location; Computation (440) of an entry hash value using a hash of three hash input parameters, wherein a first hash input parameter is a value from a first general-purpose register (32), a second hash input parameter is the return address value in the second general-purpose register, and a third hash input parameter is a secret key stored in a special-function register (35); and Store (450) the entry hash value in a first memory location, and After completion of the function and before exiting (510) the function: Loading (520) the entry hash value from the first memory location into a third general-purpose register (32); Loading (530) the return address value from the second memory position into the second general register (32); Computation (550) of an exit hash value using the same hash as in the computation of the entry hash value and using three hash input exit parameters, wherein a first hash input exit parameter is the value from the first general-purpose register (32), a second hash input exit parameter is the return address value from the second general-purpose register (32), and a third hash input exit parameter is the secret key stored in the special-function register (35); Determine (560) whether the entry hash value equals the exit hash value; in response to the finding that the entry hash value equals the exit hash value, perform (570) a function jump back to exit the function; and In response to the fact that the entry hash value does not match the exit hash value, execute (580) a trap interrupt.

A memory device, a memory system, and a control logic are provided. The memory device includes an array of memory cells including a plurality of non-volatile memory cells, and a control logic circuit including a system bus, a microcontroller configured to write data to a plurality of special function registers through the system bus, and a parallel controller configured to write parallel data to at least two registers among the plurality of special function registers independently of the system bus.

A Peripheral Trigger Generator (PTG) for generating signals adaptively responsive to time-driven events based on execution run time. A variable PTG step delay, such as a “wait for software trigger” command, may provide an adaptive step delay between the output trigger commands. An adaptive step delay may use a combination of PTG Command+Control Bit in PTG Special Function Register. The adaptive step delay may be part of the Functional Safety Diagnostics package developed for the PTG module.

A Peripheral Trigger Generator (PTG) for generating signals adaptively responsive to time-driven events based on execution run time. A variable PTG step delay, such as a "wait for software trigger" command, may provide an adaptive step delay between the output trigger commands. An adaptive step delay may use a combination of PTG Command + Control Bit in PTG Special Function Register. The adaptive step delay may be part of the Functional Safety Diagnostics package developed for the PTG module.