35 results about "Access register" patented technology

The invention provides a data processor and method, electronic equipment and a storage medium, the data processor comprises an instruction scheduler and a copy engine, the instruction scheduler comprises a first tensor access register, and the first tensor access register is used for storing sub-tensor description information transmitted externally; the replication engine comprises a first queue structure, a second tensor access register and an instruction decoder, the second tensor access register is used for storing sub-tensor description information received from the first queue structure, and the instruction decoder is used for analyzing an instruction received from the first queue structure and generating a control signal to drive data handling; wherein the instruction scheduler is configured to dynamically detect a change parameter item of the sub-tensor description information, and write the change parameter item into the first queue structure, so that the copy engine incrementally updates the sub-tensor description information in the second tensor access register based on the change parameter item, therefore, the data transmission redundancy can be reduced, and the data transmission efficiency is improved. And the instruction processing efficiency is improved.

The application discloses a multicast or broadcast access register verification method and system, and belongs to the chip verification technical field, and comprises the following steps: obtaining a register model corresponding to a device under test; reloading a driver configuration global parameter of a bus agent in a multicast or broadcast test case; obtaining all register nodes in the register model according to the test case, screening all the register nodes according to a register node list to obtain a corresponding register node sequence; obtaining all registers corresponding to each register node in the register node sequence, and screening all the registers of each register node in the register node sequence according to a preset register attribute and a register name of the register list; performing write access on each register to obtain a first register, and performing read access on the first register, thereby improving the verification efficiency.

This application relates to a register monitoring method, apparatus, system, chip, and chip module. Applied to a register monitor located on a transmission port of an on-chip bus, the method includes: obtaining multiple access events of at least one target master device accessing a register from a cache queue of the on-chip bus; packaging the multiple access events according to a preset trace data structure to obtain a trace data stream; the trace data stream is used to monitor the register access behavior. This method enables register monitoring.

The invention belongs to the technical field of hardware design, and provides a sharing operation method, system and equipment of a network acceleration unit and a medium, and the method comprises the step of configuring a shared general register, an exclusive general register and an exclusive special register group for multiple hosts in a single network acceleration unit. Each host accesses the register through the low-speed bus based on the unique identifier. And the acceleration unit performs data interaction with each host through a high-speed bus according to the configuration of the register. When the host operation is processed, the management message and the data transmission message are distinguished by judging whether the basic communication resource register group is accessed or not, and high-order modification and resource mapping are carried out on a load data address in the data transmission message. When an external data packet is received, a target host is determined through analysis and address matching, and resource identifier mapping and data access are carried out. According to the invention, each host is ensured to have independent communication resources and data channels, the complexity and the cost of hardware implementation are reduced, and the resource utilization rate and the system expansibility are improved.

The invention relates to a data encryption transmission method and system based on RDMA (Remote Direct Memory Access), and the method comprises the steps: in a user mode driver or a kernel mode driver, when an application calls a create qp function, defaulting to distribute a memory buffer with a fixed size, and registering the memory buffer into an mr to obtain a memory mr specially used for encryption mode transmission; when a user application program calls a modify qp function to switch the QP state to RTS, the distributed memory cache is initialized, an encrypted character is generated and filled in the memory mr, and the encrypted character is packaged into a network frame through RDMA hardware and then sent to a receiving end; the sending end analyzes the encrypted character and modifies the operation mode of the RDMA hardware DMA access memory corresponding to the configuration; and the receiving end analyzes the encrypted characters, modifies and configures the opposite operation mode into a register of a DMA access memory of RDMA hardware, and performs corresponding data increase and decrease operation through the configured DMA operation mode to complete decryption and recovery of the data. According to the invention, the security problem of data transmission can be solved.

The present invention is a PXIe data acquisition module with multi-channel isolation that supports multiple acquisition functions. The present invention relates to the field of PXIe data acquisition technology. A plurality of analog signal channels with inter-channel isolation are used to connect ports to be measured. Signal conditioning and analog-to-digital conversion are performed on the port signals to generate analog signals. The output analog signals are processed and stored using an FPGA, and the processed signals are output to a data transmission interface via a PCIe interface. The FPGA performs corresponding on-chip digital signal processing and stores the signals in a DDR. The main controller can read the data stored in the DDR via the PXIe bus. The main controller configures the different measurement functions of each channel by accessing register configurations in the FPGA. The PXIe interface used in the present invention can achieve a data transmission rate of up to 16 Gbps via the PCIe 2.0x4 bus.

The invention discloses a TH-1 chip debugging method based on an OpenOCD and a customized OpenOCD, and belongs to the technical field of processor on-chip debugging. The method comprises the steps that a communication environment between a debugging host and a TH-1 chip is set up; configuring related parameters adapted to TH-1 chip debugging for the OpenOCD, and operating an OpenOCD program after parameter configuration in a debugging host; and debugging the TH-1 chip based on the debugging host carrying the customized OpenOCD, and obtaining a debugging result. According to the invention, the internal state of the TH-1 chip, such as interruption, operation and reset of a core, can be controlled; a register and a storage space in the TH-1 chip can be accessed; the Flash on the chip can be read and written; the access to the memory space of the chip by using a specific instruction set of the TH-1 chip is supported, and the problem that the OpenOCD open source version does not support the TH-1 chip is solved.

The embodiment of the invention discloses an access conversion method and device of a peripheral register, electronic equipment and a computer readable storage medium, and relates to the technical field of computers.The method comprises the steps that an equipment hardware access interface is created, and a memory mapping function is registered; responding to an application program access equipment hardware access interface, and calling a memory mapping function to apply for a shared memory corresponding to the application program; responding to the application program to access the shared memory, and calling a preset monitoring operation function; determining a physical address mapped by the shared memory based on a preset monitoring operation function, and establishing a memory monitoring service for the physical address; responding to the situation that the application program accesses the physical address through the memory monitoring service, and obtaining peripheral register data from the shared memory. Therefore, when the off-chip peripheral register is accessed, access can also be performed in a memory mapping base address and offset mode, and the operation of accessing the register by an application layer is simplified.

The invention discloses a dual-bus register access device and method, and relates to the field of registers. The device comprises a register module which comprises a shared physical register and two read mapping buffer areas; the two bus interfaces are configured to be used for accessing the shared physical register and accessing the corresponding read mapping buffer areas, and the two bus interfaces are configured to be used for accessing the shared physical register and the corresponding read mapping buffer areas; an arbiter; and the synchronization unit is used for refreshing the address data of the written register unit stored in the read mapping buffer area corresponding to the two bus interfaces in response to the operation of writing data into the shared physical register by the two bus interfaces. In the write operation stage, the data is actively refreshed through the synchronization unit, hardware-level active guarantee of write-read consistency is achieved, and the requirement of an ARM M0 low-power-consumption scene for data real-time performance is met. Meanwhile, the read-write isolation design of the double-read mapping buffer area and the synchronization unit is matched with the access arbitration strategy of the arbiter to form a full read-write process conflict-free closed loop.

Security and support for trust domain operation is described. An example of a method includes processing, at an accelerator, one or more compute workloads received from a host system; upon receiving a notification that a trust domain has transitioned to a secure state, transition an original set of privileges for the accelerator to a downgraded set of privileges; upon receiving a command from the host system for the trust domain, processing the command in accordance with the trust domain; and upon receiving a request from the host system to access a register, for a register included in an allowed list of registers for access, allow access to the register, and, for a register that is not within the allowed list of registers for access, disallowing access to the register.

The invention relates to a device register access method, an electronic device and a storage medium, and belongs to the field of memories. The method comprises the steps that a write access request from a processor is received, the write access request comprises a register address and a data field, and the data field comprises a memory address and a data length; if the write access request is a special write access request, identifying a real intention of the special write access request; and if the real intention of the special write access request is read access, reading data of which the length is consistent with the data length from a register corresponding to the register address, and storing the read data into a memory corresponding to the memory address. According to the method and the device, the super-long data larger than 8 bytes can be accessed at a time, when multiple registers (for example, larger than 2) with continuous addresses need to be accessed, the registers do not need to be accessed in multiple steps, the multiple registers can be accessed at a time, and therefore the access efficiency can be greatly improved.

The disclosure provides a PLC instruction system, and relates to the technical field of programmable logic controller, which comprises an instruction executor, a register and a memory mechanism; the instruction executor is used for executing instructions stored in a program block, accessing the register and the memory mechanism according to the instructions, and interacting inside the PLC instruction system through the instructions stored in the program block; the register is used for storing bit logic results of current operation; and the memory mechanism is used for storing data and accessed by a program. The instruction executor in the disclosure accesses the register and the memory mechanism through the instructions stored in the program block, unifies the format inside the PLC instruction system, has the role of unified format, and solves the problem that the PLC instruction system is not unified in the related art.

An AESA may include a point-to-point serial interface between RFIC that implements positional addressing and is extensible to an unlimited amount of RFIC. A controller of the AESA may access registers of one or more RFIC and sends control and synchronization signals using a low-latency serial interface. The AESA may include primary and secondary interfaces which form a mesh network allowing communications around defective devices or interconnects and reduced area overhead resulting in array size reduction. The AESA may include health monitoring to determine location of data network faults providing improved array mean-time between failure (MTBF) and fault recovery. The AESA may allow faster antenna array configuration and beam steering rates for improved uptime and optimized scan modes. The AESA may experience improvements in manufacturability and reliability due to redundancy and fault isolation. The AESA may include more RFIC per serial interface allows scaling into larger arrays.

The present disclosure provides a data processor, a method, an electronic device and a storage medium, the data processor comprising an instruction scheduler and a replication engine, the instruction scheduler comprising a first tensor access register configured to store sub-tensor description information transmitted externally; the replication engine comprising a first queue structure, a second tensor access register configured to store sub-tensor description information received from the first queue structure, and an instruction decoder configured to parse instructions received from the first queue structure and generate control signals to drive data transfer; wherein the instruction scheduler is configured to dynamically detect a change parameter item of the sub-tensor description information, write the change parameter item into the first queue structure, so that the replication engine incrementally updates the sub-tensor description information in the second tensor access register based on the change parameter item. Thus, the embodiments of the present disclosure can reduce data transmission redundancy and improve instruction processing efficiency.

The invention provides a PLC instruction system, which relates to the technical field of programmable logic controllers and comprises an instruction actuator, a register and a memory mechanism. The instruction executor is used for executing instructions stored in a program block, accessing a register and a memory mechanism according to the instructions, and interacting in the PLC instruction system through the instructions stored in the program block; the register is used for storing a bit logic result which runs at present; and the memory mechanism is used for storing data and is accessed by a program. According to the instruction executor, the internal formats of the PLC instruction system are unified through the instructions stored in the program block, the access register and the memory mechanism, the effect of unifying the formats is achieved, and the problem that the PLC instruction system is not unified in the related technology is solved.

The invention discloses an FPGA (Field Programmable Gate Array) firmware upgrading method and related equipment. According to the method, under the condition that FPGA firmware upgrading needs to be carried out, the electronic equipment can switch the state of the state machine to the upgrading state, lock protection is carried out on the switching process, the currently-used FPGA firmware can be erased, and the new FPGA firmware can be burnt and applied. In the erasing, burning and application process, when the level of the GPIO pin used for simulating the JTAG needs to be set, the electronic equipment can write the register preset value corresponding to the target level of the GPIO pin into the corresponding register, and maintenance and measurement information related to register access does not need to be recorded. According to the method, time consumed in the FPGA firmware upgrading process can be saved, so that the JTAG working frequency simulated through GPIO is improved, the requirement of the JTAG working frequency achieved by hardware is met, and hot updating of the FPGA firmware is achieved.

The invention provides an access and instruction generation method, device and system, an upper computer, a lower computer, a medium and a program product, and the method comprises the steps: responding to a received register access instruction, and analyzing the register access instruction, obtaining an instruction type included in the register access instruction, at least one to-be-accessed register address and a register value corresponding to each to-be-accessed register address; under the condition that the instruction type is a read instruction, reading a value in a register to be accessed corresponding to each address of the register to be accessed, and sending the value in the register to be accessed to an upper computer; and when the instruction type is a write instruction, respectively writing the register value corresponding to each to-be-accessed register address into a to-be-accessed register corresponding to each to-be-accessed register address. In this way, the effect of accessing a plurality of to-be-accessed registers with discontinuous addresses can be achieved through one register access instruction.

This application provides a method for accessing a bus device via JTAG. It includes: a first JTAG interface forming a first JTAG chain, a first CPU core group, and a first JTAG-bus conversion unit; the first CPU core group is coupled to a register file of at least one hardware resource within the chip via a first bus; the first JTAG interface accesses the first CPU core group and the first JTAG-bus conversion unit in a chained manner; the first JTAG-bus conversion unit is coupled to the register file via a second bus, and the register file is not coupled to the first JTAG chain; the first JTAG-bus conversion unit, in response to recognizing an access request received via the first JTAG link instructing it to access the register file, accesses the register file, and sends the access result to the first JTAG interface via the first JTAG chain.

The invention provides a mirror image starting method and device, a medium and electronic equipment. The mirror image starting method comprises the steps that an IU request message sent by a host to a switch is received, and fields of the IU message comprise a destination MAC address, a source MAC address, the Ethernet type of an IU, the length of an IU part of the IU request message, whether the request IU message needs to be responded or not, a switch identifier, the type of sent switch, an error number, the type of the IU message, IU message data and an IU response identifier; the IU response identifier is an IU request type or an IU response type; sending an IU response message to the host based on the IU request message, wherein the IU response message comprises switch information; and based on the IU request message and the IU response message, starting an executable mirror image loaded to a memory. According to the method, the switch can only maintain one mirror image code, and independent development and maintenance for different hosts are not needed. In addition, the cpu applied in the switch can access the register more quickly.

A method for handling non-access stratum (NAS) mobility management (MM) cause is provided. The method is applicable to a user equipment (UE). The method includes the following steps. Receiving a message from a network node. The message includes a specific cause indicating that a public land mobile network (PLMN) is not allowed to operate at a location where the UE is currently located. Deleting a last accessed registered tracking area identity (TAI) and a TAI list according to the message.

An integrated circuit includes a hardware inexact floating-point logarithmic number system (FPLNS) multiplier. The integrated circuit access registers containing a first floating-point binary value and its first logarithmic binary value and a second floating-point binary value and its second logarithmic binary value, each being in an FPLNS data format. The FPLNS multiplier configured to multiply the first and second floating-point binary values by adding, using an approximate adder, the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, shifting a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, subtracting a correction factor from the first shifted bias value to form a first corrected bias value, and subtracting the first corrected bias value from the first logarithmic sum to form a first result

A control circuit including a storage circuit, a voltage detection circuit, a processing circuit, and a wake-up circuit is provided. The storage circuit includes a register and stores a program code. The voltage detection circuit detects an external voltage. The processing circuit accesses the register in response to the external voltage reaching a first predetermined voltage. The processing circuit enters a power-down mode in response to the external voltage reaching a second predetermined voltage. In the power-down mode, the processing circuit stops accessing the register. The wake-up circuit determines whether a wake-up event occurs. In response to the wake-up event, the wake-up circuit directs the processing circuit to exit the power-down mode and enter an operation mode. In response to there being no wake-up event, the processing circuit stays in the power-down mode. In the operation mode, the processing circuit executes the program code.

The application provides a programmable logic controller implicit access address identification method, system and electronic equipment, and the method comprises the following steps: in the compiling process of a user program, scanning relevant program codes to find out target instructions; according to preset address interval analysis rules, the target instructions are analyzed to identify all register addresses corresponding to the target instructions, and all identified register addresses are determined as implicit access addresses; and the implicit access addresses are identified in a cross-reference table in a preset format. Through identification of the implicit access register addresses and intuitive identification in the cross-reference table, the application can help electrical engineers to more quickly and conveniently check the use of the register addresses, effectively improve program checking efficiency and reduce the difficulty of program debugging and maintenance.

The invention discloses a storage device and a method for providing address pages of registers accessible per client. A memory device may include a memory cell array, a register block, and a logic controller. The register group may include: a plurality of registers configured to store setting values for performing a plurality of operations on the memory cell array; and a specific register including first address information of at least one accessible register selected from the plurality of registers. The logic controller may compare the second address information with the first address information and allow or prevent access to the accessible register based on a result of the comparison. The second address is received along with a register access command from an external device.

An integrated circuit includes a hardware inexact floating-point logarithmic number system (FPLNS) multiplier. The integrated circuit access registers containing a first floating-point binary value and its first logarithmic binary value and a second floating-point binary value and its second logarithmic binary value, each being in an FPLNS data format. The FPLNS multiplier configured to multiply the first and second floating-point binary values by adding, using an approximate adder, the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, shifting a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, subtracting a correction factor from the first shifted bias value to form a first corrected bias value, and subtracting the first corrected bias value from the first logarithmic sum to form a first result.

A unified hierarchical 3D integrated register file for SIMT compute cores A hierarchically organized register file (RF) for use in SIMT processor core is disclosed. A global I / O block of the RF comprises comprising a plurality of input-output circuits for servicing wave-related RF requests. Each input-output circuit is responsive to a respective thread lane of the SIMT core. Each memory bank of the RF is divided into parallelly accessible sub-banks. Per-bank local I / O circuitry is configured to buffer the requests forwarded by the corresponding input-output circuit, schedule and dispatch the buffered requests to a selected sub-bank. The RF is unified with respect to different threads and with respect to different data types. Each request to access the register file includes a register address, and the local I / O circuitry is configured to select one of the associated sub-banks based on wave index information included in the register address. The RF is implemented on a separate memory die for vertical integration with a core die comprising the thread lanes.

Embodiments of the present application provide a cache control method and device, electronic equipment and readable storage medium, the method comprising: in the case of receiving a memory access request of a memory access module, recording request information of the memory access request into a memory access register of a control module, waiting for arbitration of an arbitration unit and then sending to a cache pipeline unit; using the cache pipeline unit to query whether the memory access request hits the cache; in the case of the memory access request hitting the cache, executing the memory access request; in the case of the memory access request not hitting the cache, adjusting the state of the memory access register to a dormant state and sending a first request to a master node; the first request is used to obtain cache data required by the memory access request. Embodiments of the present application can guarantee cache consistency in a multi-core processor system without excessive hardware overhead and bus overhead.

A system and method for instruction execution are disclosed. The system may include a processor including a register and a code memory. The reordering component may reorder a first instruction and a second instruction of a set of instructions of a first type stored in a code list in a code memory, at least one of the first instruction and the second instruction accessing a register.

The present application relates to sram device and method based on register redundancy repair, by designing address comparison unit and register unit for sram memory without redundant row and column, when redundancy repair is needed, address comparison unit can be used to determine whether to access data in sram memory bank or data in register unit, to achieve the purpose of using register to realize sram redundancy repair mechanism. Compared with the traditional sram repair method, the above repair design realizes the automatic repair process of sram without redundant row and column, thereby reducing the sram design cost and design cycle, compared with sram with redundant row and column, the above repair design can flexibly allocate repair resources according to the failure of sram, and is compatible with the existing EDA tool automatic process.