234 results about "Instruction distribution" patented technology

According to the instruction processing system, method and device provided by the invention, the instructions can be efficiently and smoothly distributed and run through the at least one processing module of the processor, and different instruction distribution logics are adopted based on different types of business processing instructions through two-stage instruction distribution, so that the service processing efficiency is improved. The business processing instructions are stored in the target storage area and then scheduled to the instruction execution module, so that quick distribution and hardware support of different types of business processing instructions are realized, the instruction distribution efficiency is greatly improved, complex calculation tasks can be flexibly and efficiently processed, instruction scheduling can be performed according to the priorities of the business processing instructions, and the service processing efficiency is improved. The key business operation is ensured to be responded and processed in time, and the overall performance and the operation efficiency of the database processor are effectively improved. The technical effect of flexibly and efficiently processing the database acceleration task is achieved.

The invention provides a switching station control method and system of a subway station. The system comprises a subsystem control unit, a main control unit, a communication module and a data caching module, the subsystem control unit transmits an equipment on-off state, a fault signal and an environment parameter to the main control unit in a hybrid networking mode, and a first cooperative control instruction set is generated in combination with a linkage rule base; a target priority is distributed for the operation instruction to obtain a second cooperative control instruction set, and the communication module adopts a multi-channel parallel distribution mechanism for pushing; in the process of executing the switching station operation, the data caching module stores running state data, identifies a time sequence mode by using a machine learning model, pre-judges a switching station linkage scene and loads a control strategy; and the main control unit detects the response delay of the subsystem control unit and generates a third cooperative control instruction set according to the control strategy so as to optimize the switching station control time sequence. According to the invention, intelligent cooperative control of multiple electromechanical devices can be realized.

The invention provides a processor memory access optimization implementation method and system with multi-channel concurrent instructions, and relates to the technical field of processor integrated circuits, and the method comprises the steps: obtaining a Load instruction and a Store instruction to be executed; distributing a plurality of memory access instructions to each memory access channel which is independently processed in parallel, wherein each memory access channel comprises a Load memory access channel and a Store memory access channel; an independent Load queue and an independent RAW check queue are arranged in the Load memory access channel, and an independent Store queue, an independent STD queue and an independent Store Buffer queue are arranged in the Store memory access channel; the Load instruction is sequentially subjected to an address generation stage, a TLB parallel query stage, an L1Cache access stage, a RAW check and data forward push stage and a data write-back stage in the Load memory access channel; according to the method, address and data separation processing is carried out on a Store instruction, an address part enters a Store queue, a data part enters an STD queue, then merging is carried out, multiple Store operations on the same Cache Line are merged into one-time writing, the merged data are written into a Store Buffer queue, and then the Store Buffer queue submits and caches in a unified mode.

The invention provides a circuit board processing control method and system applied to an industrial internet of things, and the method comprises the steps: collecting the real-time equipment state data of a plurality of processing equipment in the processing process of a target circuit board, and calling a path generation model to generate an initial processing path based on the historical processing path data in a processing parameter set; inputting the path node data and a physical sensing data set into a parameter adjustment model for matching, and generating a path node adjustment instruction; performing parameter optimization on the processing nodes in the initial processing path based on the path node adjustment instruction through a parameter adjustment model, generating a target processing path, extracting a process constraint condition of each processing node in the target processing path, performing real-time control instruction distribution on the plurality of processing devices, and generating a target processing path; and performing joint iterative updating on the path generation model and the parameter adjustment model based on the feedback signal until the processing error rate of the target processing path is lower than a preset threshold value. The circuit board machining precision and the overall production efficiency can be improved.

The invention relates to the technical field of hydraulic engineering monitoring, and discloses a hydraulic engineering operation risk monitoring management system based on multi-sensor fusion. The system comprises a data acquisition module, a data fusion module, an early warning and instruction generation module, and an instruction distribution and verification and correction module. The data acquisition module acquires structural deformation, water flow pressure and environment temperature and humidity data in real time through multiple types of intelligent sensors; the data fusion module inputs the collected data into a dynamic weighted fusion model, and generates a comprehensive monitoring index in combination with a sensor confidence coefficient weight and a historical data deviation rate; the early warning and instruction generation module triggers multi-stage early warning and generates an equipment regulation and control instruction set according to the comprehensive monitoring index and a preset safety threshold value; the instruction distribution module distributes the instruction to an execution terminal through a distributed message queue; and the verification and correction module checks terminal feedback signals by using a back propagation verification mechanism, and corrects the confidence coefficient weight of the model.

The invention discloses a real-time simulation performance evaluation method based on an ARMv8 architecture multi-core processor, and particularly relates to the technical field of multi-core performance evaluation. Comprising the following steps that a concurrent monitoring module is arranged, and an access instruction sequence and memory barrier instruction information of a processing core are collected; analyzing an address cross relation and time sequence dependence between the access instructions, and generating an instruction rearrangement risk access group; concurrency consistency analysis is carried out on the risk access group, race conditions are identified, and a synchronization mode and memory barrier instruction distribution are recorded; high-intensity concurrent operation is injected into the simulation environment, read-write operation of the shared variables is continuously tracked, and an instruction execution sequence is analyzed; the matching degree under different simulation load conditions is counted, a real-time simulation performance evaluation index for the weak memory model is generated, and the potential consistency problem caused by instruction rearrangement can be accurately recognized.

The invention relates to the technical field of multi-agent cooperative control, and discloses a multi-agent cooperative operation control method and system based on a wireless deterministic network, and the system comprises a time synchronization calibration module which is used for collecting the initial timestamps and network transmission delay data of all agent nodes, setting synchronization protocol attributes for calibration, and transmitting the initial timestamps and the network transmission delay data to a wireless deterministic network; establishing a collaborative operation network model; the task instruction distribution module associates the job task demand with the agent capability data, and generates a collaborative job instruction set through task decomposition; the path conflict detection module initializes parameters based on a network model and optimizes a path to obtain a collaborative optimization path; the collaborative state sensing module obtains real-time state data and analyzes and determines control strategy parameters; and the control parameter optimization module performs simulation verification and feeds back optimization parameters. According to the system, the precision, efficiency and reliability of multi-agent collaborative operation are improved, and the system is suitable for various complex operation scenes.

The invention provides a parallel optimization method and system for a GPGPU (General Purpose Graphics Processing Unit) instruction execution stage, and the method comprises the steps: splitting an input instruction into a plurality of sub-instructions which can be independently scheduled based on an instruction type, operand dependency analysis and a hardware resource real-time state, and generating a dependency table to record the input and output association of the sub-instructions; acquiring real-time load data of the calculation unit, the storage unit and the communication unit, and distributing the sub-instructions to the calculation unit, the storage unit or the communication unit by adopting a priority dynamic adjustment algorithm and combining instruction key path analysis; according to the dependency relationship of the sub-instructions and the availability of hardware resources, the execution sequence of the sub-instructions is adjusted to maximize the degree of parallelism; and analyzing the dependency relationship among the sub-instructions in real time to maximize the degree of parallelism to dynamically adjust a parallel execution strategy so as to realize serial execution of dependent instructions and parallel execution of non-dependent instructions. According to the method, the complexity of instruction compiling is reduced, the efficiency of instruction compiling is improved, and meanwhile extra consumed time is reduced.

The invention provides a vector instruction processing method and device, electronic equipment and a storage medium, and relates to the technical field of data processing.The method comprises the steps that a null item is distributed for a vector instruction in an instruction sequencing queue, the vector instruction is split into vector instruction internal operation corresponding to each data element in the vector instruction, and the vector instruction internal operation corresponds to each data element in the vector instruction; performing register renaming on the internal operation of each vector instruction, respectively distributing an empty item for the internal operation of each vector instruction in the vector instruction sequencing queue, executing the internal operation of each vector instruction out of order, writing the internal operation of each vector instruction back to an item corresponding to the internal operation of each vector instruction in the vector instruction sequencing queue, and writing the internal operation of each vector instruction back to the item corresponding to the internal operation of each vector instruction in the vector instruction sequencing queue. And writing the vector instruction back to an item corresponding to the vector instruction in the instruction sequencing queue. The invention provides a vector instruction processing method and device, electronic equipment and a storage medium, which can more reasonably utilize computing resources of a processor so as to reduce the computing resources of the processor required to be occupied by vector instruction processing.

The invention discloses an adjustable resource unified data external characteristic modeling, regulation and control method and system oriented to various transaction scenes. The method comprises the following steps: collecting real-time data of an internal adjustable resource of a virtual power plant; the climbing time, the duration, the response capacity and the responsible frequency are quantized and defined as a group of external characteristic parameters, an adjustable resource data external characteristic model is constructed, adjustable resources are classified according to the external characteristic parameters of the model, and an adjustable resource characteristic library is established; in combination with the response characteristic and the load state of each adjustable resource, generating an optimal regulation and control strategy meeting the regulation and control requirements, and allocating a corresponding regulation and control instruction to each adjustable resource; each adjustable resource adjusts power output according to the regulation and control instruction, and meanwhile, the calling cost of each adjustable resource is calculated; in combination with the real-time state and the adjustment cost minimization target, the regulation sequence and proportion are optimized; according to the method, the economy and flexibility of the virtual power plant in multi-scene regulation can be effectively improved, and meanwhile, the accuracy of power grid frequency modulation response and the system stability are enhanced.

The embodiment of the invention provides a synchronization method, a synchronization device, electronic equipment and a storage medium. The synchronization method comprises the following steps: aiming at a thread bundle comprising a plurality of threads, distributing a synchronization channel for a first instruction; the first instruction and the second instruction are synchronized based on the synchronization channels, a dependency relationship exists between the first instruction and the second instruction, the thread bundle corresponds to a plurality of synchronization channel groups, each synchronization channel group comprises at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions. The synchronization method uses a synchronization channel mechanism based on an instruction type to realize synchronization of instructions in the thread bundle, effectively realizes decoupling of synchronization channels used by different types of instructions, and expands the number of synchronization channels, thereby improving the processing capability of the thread bundle for a workload, and improving the processing efficiency of the thread bundle. And challenges brought by continuously increasing workloads in the thread bundle can be effectively handled.

The invention relates to the technical field of information, and discloses a digital right near-field real-time cancel-after-verification system based on edge computing, which comprises a space-time coding module used for generating a unique cancel-after-verification identifier according to the geographic position and time of a user, and transmitting the identifier to a dynamic weight module; a dynamic weight module which is connected with the space-time coding module, generates a right and interest distribution strategy based on a federated learning model and an optimization algorithm, and outputs the optimized strategy to a block chain fragmentation module; the block chain fragment module is connected with the dynamic weight module, dynamically divides a consensus network according to the real-time cancel-after-verification density, executes distributed verification in fragments and generates a cancel-after-verification authorization instruction; and the cancel-after-verification execution module is used for distributing cancel-after-verification tasks according to the authorization instruction and synchronously updating the multi-node inventory state. By adopting the technical scheme of gridding coordinate mapping, time window division and nonlinear hash of the space-time coding module, the technical effect that the verification identifier is unpredictable and uniquely bound is achieved.

The invention relates to the technical field of power system dispatching, in particular to a distributed storage system for source-network-load-storage collaborative dispatching, which comprises a distributed data acquisition module, a regional collaborative sensing module, a distributed energy storage evaluation module, a dispatching instruction generation module and a dispatching instruction distribution module, wherein the distributed data acquisition module is used for acquiring real-time operation data of source, network, load and storage nodes in parallel; the regional collaborative sensing module is used for calculating a real-time power deviation value; the distributed energy storage evaluation module is used for generating an energy storage adjustment instruction set; and the scheduling instruction generation module is used for generating a final refined scheduling instruction. According to the invention, through constructing a cooperative scheduling mechanism of the source network load storage full chain, accurate identification of power deviation and optimal distribution of energy storage resources are realized, and scheduling response efficiency and operation stability of the system are significantly improved.

The invention relates to the technical field of industrial control, and discloses an industrial communication protocol adaptation method and system based on OpenHarmony. The method comprises the following steps: performing distributed soft bus deployment on a plurality of industrial devices in an industrial control network to obtain a distributed device connection architecture; carrying out multi-protocol adapter loading on the industrial automation runtime service of the distributed equipment connection architecture to obtain a multi-protocol runtime service instance; performing communication protocol identification and configuration on the plurality of industrial devices according to the multi-protocol runtime service instance to obtain standardized device data; and establishing a data transmission channel according to the standardized device data, and performing global state synchronization and cooperative control instruction distribution on the plurality of industrial devices to generate a distributed cooperative control network. The deployment and maintenance work of the industrial control system is simplified, the accuracy and consistency of system configuration are improved, the risk of manual configuration errors is reduced, and the development cost and maintenance complexity of industrial application are reduced.

Aspects of the disclosed technology include computer-implemented systems and methods for adapting machine-learned models using high-quality synthetic data that is tailored to elicit improved instruction-following abilities for particular target instruction distributions and models. A model adaptation system can obtain instruction metadata indicative of at least one use case and at least one skill associated with a particular computing task to be performed by a target machine-learned model. The system can generate a metadata-conditioned synthetic instruction by prompting a generative model system including one or more machine-learned generative models with the instruction metadata as one or more constraints. The system can generate a model response by prompting the generative model system with the metadata-conditioned synthetic instruction. The system can modify a target sequence processing model based at least in part on a data pair including the metadata-conditioned synthetic instruction and the model response.

The invention relates to the technical field of call center control, and discloses an unmanned vehicle formation control and obstacle avoidance reconstruction system based on complex road conditions. The system call data acquisition module is used for acquiring multi-source interaction data in real time; the dynamic feature extraction module is used for performing semantic intention hierarchical analysis on the voice stream text conversion data, performing event fragment segmentation on the user behavior time sequence data, and generating an operation track feature vector; the scene clustering engine module is used for performing space-time alignment on the semantic intention hierarchical analysis result and the event fragment segmentation result to generate a multi-dimensional scene clustering tag; the strategy matching core module is used for retrieving an interaction strategy set matched with the current scene from a distributed strategy library according to the multi-dimensional scene clustering label and generating a dynamic control instruction sequence; and the instruction distribution execution module is used for distributing the dynamic control instruction sequences to corresponding seat terminals and voice routing equipment after sorting the dynamic control instruction sequences according to priorities.

The invention discloses a batch step execution adjustment method, a computer readable medium and electronic equipment. The method comprises the following steps: acquiring a current resource index and a current index weight of a system, and a priority and a historical instruction distribution number of each step; according to the current resource index and the current index weight, whether the task parallelism degree is adjusted or not is determined; if the task parallelism degree is determined to be adjusted, determining the instruction distribution number of each step according to the current resource index, the current index weight, the priority of each step, the historical instruction distribution number and an instruction distribution algorithm; and finally, according to the instruction allocation number, allocating a corresponding number of instructions to each step so as to adjust the execution speed of each step, and pausing execution of some steps which are not allocated with instructions, or newly allocating instructions to some to-be-executed steps, that is, the number of the steps which are executed in parallel by the system is changed, so that the task parallelism degree is adjusted.

The invention relates to a neural network accelerator, in particular to an instruction flow control system applied to the neural network accelerator, which comprises a first-stage instruction flow control unit, a second-stage instruction flow control unit, a third-stage instruction flow control unit, a fourth-stage instruction flow control unit and a fourth-stage instruction flow control unit, and is characterized in that the first-stage instruction flow control unit is responsible for prefetching, decoding, executing and distributing instructions of the neural network accelerator and responding to pause influence of debugging events and synchronization events on instruction distribution; the second-level instruction flow control unit is located in each execution unit, extracts execution parameters from the second-level execution instructions distributed by the first-level instruction flow control unit, is responsible for translating and maintaining the instruction execution dependency relationship among the execution units, and ensures that the execution units execute the instructions in sequence according to the instruction execution dependency relationship among the execution units; according to the technical scheme, the defect that in the prior art, it is difficult to efficiently execute instructions with the execution dependency relationship between the execution units can be effectively overcome.

The invention relates to the technical field of industrial internet, in particular to a control system and method for stirrer production. Comprising an edge data preprocessing unit, a flexible production instruction distribution unit and a working condition diagnosis and protection control unit. By constructing an integrated control parameter mapping model, an industrial operation signal is converted into a collaborative sensing digital primitive; the production task is compiled into an intelligent production execution process cluster based on a resource scheduling algorithm, and equipment is driven to execute differentiated production; and performing situation assessment on the digital primitives by using the anomaly detection model, and generating a regulation and control instruction to execute process logic recombination and safety protection. According to the invention, the problems of low production information integration level and tight data in each link of a production control system are solved, and flexible scheduling and active security defense in the production process are realized.

The invention relates to the technical field of quantum computer control, and belongs to a quantum equipment instruction distribution system and method based on multi-thread parallel routing, the system comprises an upper computer, an instruction board, an instruction routing board and an equipment end, and the instruction distribution method comprises the following steps: S1, inputting a program instruction and a control instruction through the upper computer, the data is issued to the instruction board through the local bus interface; s2, multi-thread parallel execution of the program instruction is achieved in an instruction board FPGA chip, a control instruction is generated and output to a routing board through a high-speed radio frequency interface, and the control instruction comprises a target address code; s3, dynamically selecting an output port by the instruction routing board according to the target address code generated in S2, and distributing the instruction to specified equipment; and S4, each device in the device end receives the instruction through the SSMA sequence interface and executes the instruction. According to the invention, efficient synchronous control of quantum equipment is realized through multi-thread parallel execution and a dynamic routing mechanism.

A decoding method of a simultaneously multi-threading processor, a processor, and a chip are provided. The method includes: fetching an instruction stream according to an instruction fetching request; segmenting the instruction stream which is fetched in response to the simultaneously multi-threading processor being in a single-threaded mode; allocating the instructions at split positions as boundaries of switching instructions queues, wherein the plurality of target instruction queues comprise instruction queues corresponding to active threads and instruction queues corresponding to inactive threads; and decoding the instructions in the plurality of target instruction queues by using a plurality of decoder groups to obtain micro-ops obtained after decoding by the decoder groups. The embodiments of the present disclosure can improve the decoding efficiency of a multi-thread processor while being compatible with multiple thread modes.

The invention relates to the technical field of data monitoring, in particular to a workshop operation state real-time monitoring, management and control method and system, and the method comprises the steps: carrying out the real-time collection of multi-source heterogeneous data of each process execution unit through a plurality of data collection terminals, and carrying out the standardization processing of the collected multi-source heterogeneous data; based on the standardized multi-source heterogeneous data, extracting multi-dimensional features corresponding to each process execution unit, associating the multi-dimensional features with plan standard features, inputting the associated features into a state judgment model, and outputting a comprehensive state identifier; if it is judged that the comprehensive state identifier triggers a state abnormal event, comparing the state abnormal event with a preset decision rule base, and outputting corresponding decision action information; and packaging the decision action information into a corresponding management and control instruction, and transmitting the management and control instruction to the corresponding process execution unit for execution through an instruction distribution interface, thereby realizing comprehensive, accurate, real-time and intelligent management and control of the workshop operation state.

The invention discloses an eVTOL aircraft ground control device based on a multi-link adaptation and response mechanism, and belongs to the technical field of eVTOL aircraft communication and control. The device comprises an instruction distribution module, a multi-link management module, a frame construction module and an error control module. The instruction distribution module is responsible for cooperating with eVTOL aircraft information to send a corresponding flight control instruction according to an actual condition; the multi-link management module evaluates a plurality of communication links (including a main link, a standby link and an emergency link) in real time and is used for sending different instructions; the frame construction module constructs an extended interactive data frame based on the MAVLink protocol, and the data frame comprises a plurality of control fields for control; the device also has an error control mechanism, and a closed-loop control system is completed through the mechanism. Through the method, the instruction reliability of the ground control station in a complex communication environment and the stability of an eVTOL aircraft system can be effectively improved.

The embodiment of the invention provides a data processing device, a processor and a data processing method. The data processing apparatus includes an instruction distribution unit, an instruction information recording unit, an instruction processing unit, and a write-back control unit, the instruction distribution unit being configured to split a vector instruction into a plurality of microinstructions, and to distribute the plurality of microinstructions to the instruction processing unit; the instruction information recording unit is configured to record instruction state information corresponding to a plurality of microinstructions respectively; the instruction processing unit is configured to receive a plurality of micro-instructions, process each of the plurality of micro-instructions to obtain a corresponding execution result, and feed back a processing progress to the instruction information recording unit; and the write-back control unit is configured to select at least one to-be-written-back microinstruction from the instruction information recording unit to perform write-back operation based on the instruction state information, and the write-back operation is used for writing an execution result of the to-be-written-back microinstruction back to the register. The device can realize out-of-order write-back of the instruction and improve the execution efficiency of the instruction.

The invention discloses a memory access device, a processor and a memory access method, and belongs to the technical field of computers. The memory access device comprises a scheduling module which is configured to distribute memory access instructions in an instruction queue to a plurality of assembly lines of the memory access device; the first cache module is configured to cache the first mapping relation; the control module is configured to query the page table and update the second mapping relation in the second cache module according to the memory access instruction of the virtual machine monitor if the memory access instruction currently processed by the plurality of assembly lines does not hit the first mapping relation and the memory access instruction is the memory access instruction of the virtual machine monitor; and the second cache module is configured to cache the second mapping relation. On the basis of not increasing the complexity of hardware design, the resource utilization rate in the execution process of the memory access instruction of the virtual machine monitor can be improved.

Apparatuses, methods, systems, chip containing products, and computer readable media are disclosed. An apparatus comprises dispatch circuitry to receive instructions, and to identify linear chains of instructions each comprising a first instruction and one or more further instructions, which are temporarily ineligible for execution due to a dependence on an immediately preceding instruction. The apparatus further comprises offline storage circuitry. The dispatch circuitry is configured, for each of the linear chains: to dispatch the sequentially first instruction to the issue circuitry and to retain the one or more further instructions in the offline storage circuitry until a chain trigger signal is received, the chain trigger signal indicating that a previously dispatched instruction, on which a sequentially next instruction depends, has satisfied a predefined issuing condition. In response to receipt of the chain trigger signal, the dispatch circuitry is configured to dispatch the sequentially next instruction to the issue circuitry.

The embodiment of the invention provides an instruction distribution device and method, a processor and electronic equipment. The instruction distribution device comprises a write selection module, a plurality of micro instruction queues and a read distribution module. The write selection module is configured to write microinstructions into a plurality of microinstruction queues; the plurality of microinstruction queues are configured to cache written microinstructions; and the read distribution module is configured to read the microinstructions from the plurality of microinstruction queues, obtain a target microinstruction group to be distributed at this time based on the read microinstructions, and execute a distribution operation. The instruction distribution device improves the bandwidth of instruction distribution by setting a plurality of microinstruction queues and a scheduling method of the plurality of microinstruction queues, thereby promoting the improvement of the performance of a processor.

The invention discloses a programmable instruction distribution system, belongs to the technical field of general graphic processing units, and aims to solve the technical problems that when branch instruction segments and loop instruction segments are processed, a large number of invalid operations exist in a GPGPU instruction pipeline, a plurality of clock cycles are occupied, the execution efficiency and parallel performance of a GPGPU are reduced, and the execution efficiency of the GPGPU is reduced. According to the technical scheme, the system comprises an instruction splitting unit and an instruction replaying unit; the instruction splitting unit is used for splitting the complete instruction segment into a plurality of sub instruction segments and completing rapid distribution of a specific instruction segment; the instruction splitting unit comprises an instruction selection switch and a programmable instruction queue; wherein the instruction selection switch is used for generating a corresponding branch instruction section from a programmable instruction queue according to an instruction mask, and distributing a branch instruction; the instruction replay unit is used for recording the distributed instruction segments and controllably replaying the corresponding instruction segments; the instruction replay unit includes register redirection logic, an instruction counter, and an instruction record queue.

The invention relates to the technical field of chips, and provides a tensor memory accelerator and a tensor memory acceleration method.The tensor memory accelerator comprises an instruction distribution unit and a plurality of tensor memory acceleration engines capable of conducting parallel processing; wherein the instruction distribution unit is used for distributing a tensor memory acceleration instruction to idle engines in a plurality of tensor memory acceleration engines for execution, each tensor memory acceleration engine is provided with a descriptor storage unit for storing descriptors, and each tensor memory acceleration engine is used for storing the descriptors according to multiplexing identification information in the tensor memory acceleration instruction. And multiplexing the descriptors from the corresponding descriptor storage units or obtaining new descriptors from the external memory. According to the invention, each tensor memory acceleration engine can selectively multiplex descriptors from the local or obtain new descriptors from the outside, so that instruction-level parallel processing and effective multiplexing of descriptor information are realized.

The invention discloses a self-coupling PID (proportion integration differentiation) flight control method of a rudder-controlled transverse-row type rotor unmanned aerial vehicle based on dynamic multi-dimensional heterogeneous fuzzy logic, and belongs to the technical field of flight control of rudder-controlled transverse-row type rotor unmanned aerial vehicles. A flight control system architecture of the self-coupling PID flight control method is composed of three core modules: (1) a dynamic multi-dimensional fuzzy logic coupling PID controller (DMHFL-SCPID); (2) control instruction distribution; and (3) a six-degree-of-freedom dynamical model of the rudder-controlled transverse rotorcraft. According to the control algorithm, input and output dynamic parameters of a system are analyzed in real time, and four-dimensional flight control quantities (roll, pitch, yaw and height instructions) are generated. A control distribution strategy based on the aerodynamic characteristics of the rotor converts the instructions into actuating quantity of an actuating mechanism, and flight attitude adjustment is realized by changing aerodynamic load distribution of a rotor system, so that the unmanned aerial vehicle is guided to realize accurate tracking along a predetermined flight path.