Image recognition accelerator and MPU chip possessing image recognition accelerator

Abstract

The invention provides an image recognition accelerator which mainly comprises a system bus arbitrator, an inside bus, an access control unit, a command distribution device, a direct memory access controller, a system task array, a resource statistical meter, a running task reserving station, a configuration memory, a plurality of command encoder units, a data memory, a plurality of processing unit arrays, a data reserving station and a Gray encoder. Compared with the prior special image recognition accelerating chip, the image recognition accelerator has the advantages of high performance, low cost, flexible application, etc.

Description

Technical field [0001] The present invention relates to image processing large-scale integrated circuit technology, and more specifically, to the technology of image processing acceleration devices. Background technique [0002] With the development of information and network technology, the connotation of digital content is becoming more and more abundant, from the original single text and pictures to the audio, video and 3D environment and other media, involving education, science, finance, culture, entertainment, Business, communications and other fields. In terms of technology, digital content development, digital content delivery, and digital content security are the three major supports of the digital content industry. On the one hand, digital content development is closely integrated with cultural creativity and artistic creation, but also inseparable from technologies such as images, audio, video, and Web2.0; with the development of broadband technology, digital content d...

AI Technical Summary

Problems solved by technology

Since the image recognition algorithm is aimed at different applications, the parameters and steps are often very different. Therefore, the effective field of the acceleration circuit for a specific algorith

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