1523 results about "Data memory" patented technology

A system is disclosed for continuous and intermittent monitoring of physiological parameters. The system comprises at least one sensor coupled to a wearable device configured to measure physiological parameters of a user; a non-transitory data store storing data collected from the at least one sensor and computer-executable instructions; and a processor in communication with the at least one sensor and the non-transitory data store, wherein the computer-executable instructions, when executed by the processor, configure the processor to: continuously measure the physiological parameters by sampling the at least one sensor at a sampling rate to obtain repeated measurements at series of intervals configured to capture important physiological events; compare measurements of the physiological parameters to a threshold to determine a likelihood of a physiological event; and alert the user when an occurrence of the physiological event is likely.

A system for implementing blended learning, including: • a central processing unit (CPU) configured to receive, process and store data from a range of user interfaces, learning management software modules, classroom interaction devices and cloud-based data storage; • an AI engine integrated into the CPU, configured to analyze students' interactions with educational content, classroom activities, and performance data in real time, with the AI ​​engine applying machine learning techniques to create personalized learning paths for each student based on their individual learning style, past performance, and engagement patterns; • A range of devices for classroom interaction, including at least one smartboard, tablet, or interactive projector, each configured to capture real-time data on classroom activities such as student participation, oral responses, and collaborative tasks. The captured data is then transferred to the CPU for analysis by the AI ​​engine to refine and dynamically adapt learning paths for each student; • a student user interface, wherein the student interface displays dynamically generated content tailored to the student's progress and performance, and wherein the content includes multimedia materials such as videos, tests and reading material adapted based on the student's interaction history and learning needs; • a CPU-connected teacher interface, wherein the teacher interface displays real-time analytics and insights from student data, including performance trends, engagement levels, and potential learning gaps, and wherein the AI ​​engine provides the teacher with actionable recommendations for adapting teaching strategies, resources, and interventions based on the individual needs of the students and their performance in class; • a cloud-based storage system, whereby the system securely stores student profiles, historical performance data and learning content, and whereby the CPU retrieves, updates and stores data from the cloud-based system in real time to ensure continuous adaptation of the learning experience.

The invention discloses a method and a device for realizing task splitting based on a multi-core processor and a related product. A device may be included as a processing device in a combined processing device, which may further include an interface device and a computing device. The computing device interacts with the processing device to jointly complete computing operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is connected with the computing device and the processing device and used for storing data of the computing device and the processing device. The scheme disclosed by the invention provides a method for scheduling group matrix multiplication class operation task splitting on the multi-core processor, which can effectively reduce data memory access and improve processing efficiency.

A machine learning platform operating at a server is described. The machine learning platform accesses a dataset from a datastore. A task that identifies a target of a machine learning algorithm from the machine learning platform is defined. The machine learning algorithm forms a machine learning model based on the dataset and the task. The machine learning platform deploys the machine learning model and monitors a performance of the machine learning model after deployment. The machine learning platform updates the machine learning model based on the monitoring.

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

The invention discloses a neural network extension execution computer system based on RISC-V. The neural network extension execution computer system comprises an RISC-V processor based on an out-of-order execution system structure, a neural network hardware accelerator, an instruction memory, a data memory and a dynamic scheduler. The dynamic scheduler is used for switching different working modes for the computer system according to the current calculation load, and distributing a calculation task to be executed to the RISC-V processor or the neural network hardware accelerator for execution; the working modes comprise a standard calculation mode, a neural network acceleration mode and a low power consumption mode; the computing tasks comprise a general computing task and a neural network computing task. According to the technical scheme, the intelligence of the computer system is improved, and the calculation efficiency, the resource consumption and the power consumption are well balanced.

The invention provides a memory access instruction processing method and a processor, and relates to the technical field of data processing, and the method comprises the following steps: splitting a target vector memory access instruction into a plurality of target vector memory access micro-operations based on a memory access width, combining the target scalar memory access instruction with at least one unexecuted scalar memory access instruction into a target scalar memory access micro-operation; executing each target vector memory access micro-operation, and / or executing a target scalar memory access micro-operation; the memory access width is determined based on a number of data cache banks in a data cache in the processor and a bit width of the data cache banks. According to the memory access instruction processing method and the processor provided by the invention, resources can be more reasonably allocated for vector memory access and scalar memory access during data memory access through splitting of the vector memory access instruction and merging of the scalar memory access instruction, and maximum resource sharing of the vector memory access and the scalar memory access is realized.

An apparatus for data fault detection and repair is disclosed. The apparatus comprises at least a processor and a memory communicatively connected to the at least a processor. The memory instructs the processor to receive a user profile relating to a user, wherein the user profile comprises at least provider data of a user. The memory instructs the processor to generate practitioner data as a function of the user profile. The memory additionally instructs the processor to retrieve remittance data as a function of the practitioner data. The memory then instructs the processor to identify a data fault in at least one of the practitioner data and the remittance data. The memory instructs the processor to initiate a data correction action based on the identified data fault.

The invention discloses a method and device for executing an operation task on a multi-core system and a related product. The device may be included as a processing device in a combined processing device, which may further include an interface device and a computing device. The computing device interacts with the processing device to jointly complete computing operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is connected with the computing device and the processing device and used for storing data of the computing device and the processing device. According to the scheme, the method for executing the operation task on the multi-core system is provided, data memory access can be effectively reduced, and the processing efficiency is improved.

The invention discloses a control strategy optimization method for a laser cutting machine, and relates to the technical field of laser cutting, and the method comprises the following steps: obtaining cutting design information of a target laser cutting machine and a workpiece by constructing an operation data space of the laser cutting machine; and performing matching retrieval on the operation data, and establishing an operation data memory bank. Performing equivalent region segmentation on the workpiece based on the cutting design information to obtain an equivalent cutting region set; and performing control strategy analysis, and determining a control strategy parameter set. And the control strategy parameter set is used for conducting cutting feedback detection on the laser cutting machine, and a sensing feedback data stream is obtained. And optimization analysis is conducted on the control strategy parameter set, an optimized control strategy parameter set is determined, and strategy optimization control is conducted on the laser cutting machine. The technical problem that an existing laser cutting machine is unstable in cutting quality under different workpieces and cutting conditions is solved, and the technical effects that the control strategy optimization accuracy is improved, and the cutting quality is kept stable are achieved.

The invention relates to the technical field of computers, in particular to an operation method of a DeePMD-kit model in a Shenwei super computer, six core groups CG of the Shenwei super computer are respectively responsible for reasoning of six sub-regions of an MPI process, each core group CG comprises an MPE and 64 CPEs, and the MPE contains a 256-bit SIMD unit; each CPE contains a 512-bit SIMD (Single Instruction Multiple Data) unit; each CPE comprises a local data memory, and each local data memory LDM realizes continuous data transmission through a DMA strategy and a main memory; the CPEs in the same core group CG realize data transmission through remote memory access (RMA); the reasoning method of each core group CG comprises the following steps: accelerating a time-consuming operator through an SACA, and distributing a calculation-intensive part of the time-consuming operator to 64 CPEs by MPE; after calculation is completed, the MPE synchronizes calculation results of the 64 CPEs and stores the results in a main memory; when the SACA runs, the SIMD is parallel, and a 512-bit vectorization instruction is sent out through the CPE. By means of the technical scheme, the method has the advantage that the DeePMD-kit model can be applied to the Shenwei computer.

The invention belongs to the related technical field of high-performance computing, and provides a memory architecture-oriented dual-precision general matrix multiplication optimization method and system in order to solve the problems of limited computing power and access efficiency and the like in the prior art. Decomposing the matrix into a plurality of sub-matrix blocks according to the slave core array topology; the slave core receives the sub-matrix blocks issued by the master core, divides the sub-matrix blocks into small sub-matrix blocks based on a uniform blocking rule, loads the small sub-matrix blocks to an independent buffer area of a local data memory based on a DMA double-buffer protocol, divides the small sub-matrix blocks in the buffer area into SIMD vectors according to the SIMD unit characteristics of the slave core, and sends the SIMD vectors to the slave core; vectorization calculation and caching operation are alternately switched according to an iteration period through different independent buffer areas; and after all the slave cores finish calculation, the master core collects results written back to the master memory by the slave cores to obtain a final operation result, and double breakthrough of calculation power and memory access efficiency is realized.

The invention provides an intelligent control gas generator set and a control system, and relates to the technical field of gas power generation. The gas generator set comprises a compression ignition type internal combustion engine, a synchronous generator, an intelligent control box and a plurality of sensors. The intelligent control box comprises a display screen, a data memory, a central processing unit and a unit regulator; the central processing unit is used for receiving collected data of the sensors and processing the collected data to obtain adjustment parameters of the compression ignition type internal combustion engine; the unit regulator regulates the input air flow of the engine, the piston motion state and the rotating speeds of the engine and the synchronous generator according to the regulation parameters; the synchronous generator converts mechanical energy obtained by the engine into electric energy to be output, the operation efficiency and economical efficiency of the gas generator set are improved, emission is reduced, and environment-friendly power generation is achieved.

The present invention relates to a transcranial focused ultrasound acoustic pressure field prediction device, a transcranial focused ultrasound acoustic pressure field prediction program, and a method for implementing acoustic pressure field generation artificial intelligence. The transcranial focused ultrasound acoustic pressure field prediction device includes: an input / output unit for allowing a user to input data, and outputting the data in a form that is recognizable by the user, a memory for storing a transcranial focused ultrasound acoustic pressure field prediction program; and a control unit for executing the transcranial focused ultrasound acoustic pressure field prediction program to derive result data according to the data input through the input / output unit, wherein the control unit outputs ultrasound acoustic pressure field data formed in a transcranial region by ultrasound applied by an ultrasonic transducer when shape data of a skull and position data of the ultrasonic transducer are input.

This application is directed to managing custom memory functions in a memory device coupled to a host device in an electronic system. The memory device obtains an information item (e.g., program, data, metadata) used to implement a custom memory function. The memory device receives a host signature and a public key from the host device and authenticates the host signature using the public key. In accordance with an authentication of at least the host signature, the memory device executes the custom memory function based on the information item. In some embodiments, the host device selects a set of memory devices based on a first-come-first-serve order, and the custom memory function is executed at each of the set of memory devices in accordance with an authentication of at least a respective host signature issued by the host device.

The invention discloses a data error correction method and device based on low-density parity check, equipment and a medium, and relates to the technical field of data error correction, and the method comprises the steps: reading data to be corrected from a data memory, and carrying out the pre-verification of the data to be corrected and a verification matrix of a preset low-density parity check code, and obtaining a pre-verification result; based on the pre-verification result, determining a first error position set in a code word position set; performing bit flipping operation on code words indicated by the first error position set to complete pre-error correction; and inputting the code word after pre-error correction processing into a low density parity check decoder for decoding, outputting data after error correction, pre-detecting the error position of the code word, and performing bit flipping on the code word at the error position, thereby reducing the number of error bits entering LDPC decoding, and improving the decoding efficiency. Therefore, the number of error bits does not exceed the decoding capability limit of hard decoding, the probability that the system enters soft decoding is reduced, and the decoding throughput rate of the system is ensured.

The embodiment of the invention provides a vector data processor, an instruction processing method, a system on chip and computing equipment, the vector data processor comprises a data access unit and a vector floating point unit, the data access unit comprises a temporary register, and the vector floating point unit comprises a vector register; the data memory access unit is used for responding to a vector memory access instruction, performing memory access of target vector data on a memory and updating a temporary register based on the target vector data, and the vector memory access instruction is obtained by splitting a mask vector memory access instruction; and the vector floating point unit is used for reading the target vector data from the temporary register and writing back the corresponding target element in the target vector data to the vector register based on the mask vector. The hardware design is optimized, the complexity is effectively reduced, the power consumption is controlled, the performance frequency is effectively improved, the area of a vector data processor is reduced, and the innovative scheme provided by the embodiment of the specification can be used for an RISC-V instruction set chip.

A Harvard-architecture computer simultaneously reads instructions using an instruction bus and accesses data over a separate data bus. A debug module has an external interface to an external debugger that initiates a debugging session by setting a debug bit in a debug mode register. When the debug bit is set, a first mux to disconnect an instruction pointer and an instruction buffer from the instruction bus and instead connects the data bus to the instruction bus. A second mux disconnects a load / store unit in an execution core from the instruction bus and instead connects the debug module to the instruction bus. The external debugger sees a unified memory space and writes addresses to the debug module that are sent through the second mux to access the data memory, and instruction addresses are sent through the second mux and the first mux to the instruction memory to read or write instructions.

The application relates to a computer-implemented method for configuring and / or controlling a bioprocessing system that is configured to physically perform and / or simulate a bioprocess, a respective computer program product, a method for performing a bioprocess, a control device for controlling and / or configuring a bioprocessing system and a bioprocess. The method uses a probabilistic algorithm to determine a predictive posterior distribution for a target set of model parameter values and configure and / or control at least one state parameter of the bioprocessing system cand / or bioprocess based on the determined predictive posterior distribution. The probabilistic algorithm employs a combination of evaluation methods based on a common physical model, including a numerical simulation method, a search method for searching in a data storage storing a plurality precomputed solution-parameter sets of the physical model and an artificial intelligence based method using a physics informed artificial intelligence model (such as physics informed neural network model), which is trained based on the solutions of the physical model generated by the simulation method and the physical model.

An apparatus for the generation of a medical report is disclosed. The apparatus includes at least processor and a memory communicatively connected to the processor. The memory instructs the processor to receive a user query. The memory instructs the processor to receive a user profile comprising a plurality of medical tests. The memory instructs the processor to generate testing data as a function of the plurality of medical tests using an encoder. The memory instructs the processor to generate textual data that is representative of the testing data using a querying transformer model (Q-former). The memory instructs the processor to generate a medical report as a function of the user query and the textual data using a report large language model (LLM).

The embodiment of the invention discloses a data operation method, electronic equipment and a chip system.The method comprises the steps that a data operation instruction from a memory controller DDRC is received, and the data operation instruction comprises a target data address; determining a target memory space from a common data memory space and a near memory calculation PIM data memory space of the memory based on the target data address, wherein the common data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset division unit; and in response to the data operation instruction, executing data operation on the target memory space based on the target data address. Visibly, the memory is divided into the common data memory space and the PIM data memory space which are mutually independent, so that the operation instruction of the common data and the operation instruction of the PIM data can be accurately distinguished, the corresponding operation instruction is accurately executed in the memory space, and the validity of data operation is improved.

The invention discloses an energy storage EMS system communication configuration method comprising the following steps: S1, designing a communication system configuration interface, completing the construction of a communication object through the communication system configuration interface in combination with a communication protocol of each device in a communication system, and carrying out communication parameter configuration and communication instruction configuration on the constructed communication object; s2, establishing a communication configuration file, and storing the configuration information in the communication configuration file; s3, compiling EMS communication software, reading the information of the communication configuration file by the EMS communication software, and constructing a data structure according to the content of the communication configuration file; s4, performing data access configuration according to the data structure constructed in the step S3; and S5, starting a communication thread for each communication object, circularly polling all communication commands of the object in the communication thread, and storing data read back from the equipment into a data memory table or issuing information read from the data memory table to corresponding equipment according to uplink or downlink characteristics of the communication commands. The universality and adaptability of the system can be improved.

The invention provides a memory address generation method, a memory control method and a memory address generation device. The generation method comprises the following steps: obtaining a data memory address based on an address signal from a bus of the SOC system by utilizing a memory controller in the SOC system, and correspondingly storing data from the bus into a data memory unit according to an access sequence from the lowest bit to the highest bit of the data memory address; and based on the mode of the storage controller, obtaining the ECC memory address, and correspondingly storing the obtained ECC check codes into the ECC storage unit according to the access sequence from the highest bit to the lowest bit of the ECC memory address. Therefore, the problem of common cause failure of the address line can be avoided, and the function safety protection effect is improved.

The invention discloses an intelligent networked automobile decision planning module simulation test system and a method thereof. The system comprises a driving simulator, RSU simulation equipment, an unmanned simulation automobile, an intelligent driving database and a data processing unit. The driving simulator comprises a parameter setting unit, a scene calculation unit, a real-time scene display unit, a GPS simulator and a vehicle state transmission unit. The RSU simulation equipment comprises a host and a radio frequency unit; the unmanned simulation automobile comprises an on-board unit (OBU), a vehicle data memory, a positioning sensor, a to-be-tested decision planning module, a path parameter setting unit and an Ethernet interface; the intelligent driving database comprises a high-precision map database, a traffic rule database and a scene database; and the data processing unit comprises a data memory and a data analysis system. The method saves site facilities, does not need to build complex instruments and equipment, and is low in cost, flexible in application and high in efficiency.

The invention relates to a full-unloading regular matching system and method based on an FPGA (Field Programmable Gate Array). The system comprises a regular rule compiling unit and an FPGA full matching unit, the regular rule compiling unit is used for receiving a regular rule set, extracting each rule fixed feature substring, compiling the uniform format isomorphic NFA, and constructing a mapping relation table of the substrings and the corresponding NFA; the FPGA full matching unit comprises a parallel high-speed character string matching engine array, a character string-NFA mapping table module, a full-quantity regular data memory, a reconfigurable general NFA engine module and a matching result output module; and the reconfiguration engine module is used for executing full unloading regular matching on the input network traffic: scanning the traffic through the engine array, screening to-be-verified traffic containing a fixed feature substring and outputting a substring identifier, querying the NFA identifier through the mapping table module, and loading NFA matching by the reconfiguration engine module. By adopting the method, low delay and high throughput performance of regular matching in a high-speed network environment can be ensured.

The invention discloses an Internet of Things access control system and method based on an intelligent contract and trust evaluation. The system comprises IoT equipment, a resource data memory RDS, an attribute authority AA and a block chain network, the method comprises the steps of initiating a resource access request, searching and responding attributes, evaluating and calculating trust values, deciding access authorization, sending access authorization and tokens, verifying access tokens, judging strategy violation, and sending and accessing resource data. According to the method, trust evaluation is introduced as the basis of authorization decision, and the comprehensive trust value is dynamically evaluated to realize fine-grained and self-adaptive access authorization; and meanwhile, safe and credible access control of the Internet of Things is realized by utilizing the characteristics of traceability and non-tampering of the block chain and adopting an intelligent contract mode. In addition, the sensitive attribute information is separated from other access control data in a main chain and side chain mode, and privacy protection of the sensitive attribute information in the access control process of the Internet of Things is achieved.

The invention discloses a robot motion strategy model optimization method and a related device, and relates to the field of artificial intelligence, and the method comprises the steps: carrying out the preliminary training of a robot motion strategy model based on an autonomous interaction playback data memory library, and obtaining a preliminarily trained robot motion strategy model; according to the situation when the second robot executes the task, whether a scene which does not meet the requirement exists or not is judged; if yes, retraining the preliminarily trained robot motion strategy model on the basis of a hybrid interaction playback data memory bank for a scene which does not meet the requirement to obtain a trained robot motion strategy model; according to the method and the device, the demonstration data of the person is collected for a scene in which task execution of the preliminarily trained robot motion strategy model does not meet requirements, so that post-mixed training is performed in a targeted manner, the robot motion strategy model can quickly meet training requirements, the training efficiency of the robot motion strategy model is improved, the training period is shortened, and the training efficiency of the robot motion strategy model is improved. The training cost is reduced.

The invention provides a network management system and method based on cloud computing, and relates to the field of network communication. The network management system based on cloud computing comprises four functional modules, namely a hardware resource layer module, a virtual resource layer module, a management layer module and a system service layer, the equipment controlled by the hardware resource layer module comprises a network server, a data memory, a router and a switch; and the virtual resource layer module has a server virtualization function, a memory virtualization function and a network virtualization function. The use cost is automatically generated through an algorithm when the user uses cloud computing, and transparent cost use billing is established through the cost generated through the algorithm, so that the whole system can more healthily and conveniently calculate the cost which the user should pay in the aspect of management, the benign development of the whole system is guided, and the user experience is improved. And more clients are attracted to use the network management system.

A statically reconfigurable dataflow architecture processor (SRDAP) performs an N-dimensional affine transform specified by a matrix on an input image to produce an output image includes L address pattern memory units (PMUs) comprising a memory arranged as a vector of L banks, and L corresponding data PMUs. Each data PMU receives a copy of the input image. In parallel: each address PMU writes an L-vector of addresses of input pixels to the vector of L banks and reads a single address of the written L-vector of addresses from a predetermined bank corresponding to a PMU number of the address PMU among the L address PMUs, and each data PMU receives the single address from the corresponding address PMU and uses it to read a single input pixel from the data PMU memory. A tree of pattern compute units coalesces the L single input pixels into an L-vector of input pixels.

An imaging device includes: an imaging sensor configured to capture a subject image to generate image data; a storage configured to store a plurality of color conversion data each defining a corresponding relationship between color information of an image before and after color conversion; an output unit configured to output a live view screen based on the image data; an operation unit configured to receive a user operation; and a controller configured to designate first color conversion data and second color conversion data from the plurality of color conversion data, in accordance with the user operation. The live view screen presents a live view image resultant of image processing of applying the first color conversion data and the second color conversion data to the image data.