5650 results about "Lithographic artist" patented technology

The invention is a seamless projection lithography system that eliminates the need for masks through the use of a programmable Spatial Light Modulator (SLM) with high parallel processing power. Illuminating the SLM with a radiation source (1), which while preferably a pulsed laser may be a shuttered lamp or multiple lasers with alternating synchronization, provides a patterning image of many pixels via a projection system (4) onto a substrate (5). The preferred SLM is a Deformable Micromirror Device (3) for reflective pixel selection using a synchronized pulse laser. An alternative SLM is a Liquid Crystal Light Valve (LCLV) (45) for pass-through pixel selection. Electronic programming enables pixel selection control for error correction of faulty pixel elements. Pixel selection control also provides for negative and positive imaging and for complementary overlapping polygon development for seamless uniform dosage. The invention provides seamless scanning by complementary overlapping scans to equalize radiation dosage, to expose a pattern on a large area substrate (5). The invention is suitable for rapid prototyping, flexible manufacturing, and even mask making.

The present invention is directed to methods for patterning a substrate by imprint lithography. An imprint lithography method includes placing a curable liquid on a substrate. A template may be contacted with the curable liquid. Surface forces at the interface of the curable liquid and the template cause the curable liquid to gather in an area defined by a lower surface of the template. Alternately, the curable liquid may fill one or more relatively shallow recesses in the template and the area under the template lower surface. Activating light is applied to the curable liquid to form a patterned layer on the substrate.

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, “wrapped” gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials (e.g. silicon-germanium, germanium, gallium arsenide, etc.), high-permittivity ridge isolation material, and narrowed base regions can be used in conjunction with the segmented channel regions to further enhance device performance.

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, “wrapped” gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials (e.g. silicon-germanium, germanium, gallium arsenide, etc.), high-permittivity ridge isolation material, and narrowed base regions can be used in conjunction with the segmented channel regions to further enhance device performance.

Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction. Conventional photo-lithography steps can be used in combination with pitch-reduction techniques to form elongate, pitch-reduced features such as bit-line contacts, for example.

The invention concerns an illumination system for wavelengths <=193 nm, particularly for EUV lithography, with at least one light source, which has an illumination A in a predetermined surface; at least one device for producing secondary light sources; at least one mirror or lens device comprising at least one mirror or one lens, which is or are organized into raster elements; one or more optical elements, which are arranged between the mirror or lens device comprising at least one mirror or one lens, which is or are organized into raster elements and the reticle plane, whereby the optical elements image the secondary light sources in the exit pupil of the illumination system.The illumination system is characterized by the fact that the raster elements of the one or more mirror or lenses are shaped and arranged in such a way that the images of the raster elements cover by means of the optical elements the major portion of the reticle plane and that the exit pupil defined by aperture and filling degree is illuminated.

An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate. In addition to the dual-bit nature of the cell, density can be even further improved by multi-level storage. In one embodiment, the dual multi-level structure is applied to the ballistic step split gate side wall transistor. In a second embodiment, the dual multi-level structure is applied to the ballistic planar split gate side wall transistor. Both types of ballistic transistors provide fast, low voltage programming. The control gates are used to override or suppress the various threshold voltages on associated floating gates, in order to program to and read from individual floating gates. The targets for this non-volatile memory array are to provide the capabilities of high speed, low voltage programming (band width) and high density storage.

Previously disclosed methods and devices are extended in this application by two-dimensional analysis of optical proximity interactions and by fashioning a computationally efficient kernel for rapid calculation of adjustments to be made. The computations can be made in realtime, whereby the use of OPC assist features can be reduced, with substantial savings in file size and computational requirements. Further aspects of the invention are disclosed in the descriptions, figures, claims and documents incorporated by reference.