391 results about "Epitaxy" patented technology

The invention discloses a method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip. The method comprises the following steps: S1, preparing an epitaxial structure: processing a substrate and a buffer layer, growing an etching barrier layer and an ohmic contact layer, and carrying out stacking epitaxy on a functional layer; s2, patterning the silicon-based substrate: preparing a dielectric layer and a metal structure; s3, diamond ohmic contact layer integration: processing a p-type conductive diamond film layer, and carrying out metal reflection and bonding; s4, removing the substrate and forming an n-type structure: stripping the substrate to be in n-type contact; s5, back-end process integration: preparing an electrode and an optical structure; according to the invention, the heat dissipation performance of the chip is significantly improved; the series resistance is reduced by 30%-50%; the resistivity of the p / n type diamond ohmic contact layer is reduced by 1-2 orders of magnitude compared with ITO; gaAs material light absorption and metal shading are avoided, and the red light transmittance is improved from 75% to more than 90% by combining with the micro lens array; the method is compatible with existing MOCVD, CVD and photoetching processes, large-scale production of wafers of 2-12 inches can be achieved, and the manufacturing cost is reduced.

The invention relates to a method for improving epitaxial growth quality of a tunnel junction cascade semiconductor laser. The invention innovatively provides a strain superlattice gradient repair technology. By designing a low-temperature low-speed nucleation-high-temperature high-speed epitaxy composite growth mode, a periodic superlattice buffer layer is introduced to a tunnel junction interface. Wherein lattice strain relaxation is achieved at the rate of 0.5-2 / s in the low-temperature stage, defect coverage is completed at the rate of 4-8 / s in the high-temperature stage, and dislocation line bending is terminated on a superlattice interface through thermodynamic regulation and control. Compared with the traditional process, the scheme can obviously improve the crystal quality, and does not increase the specific contact resistance of the tunnel junction interface.

The invention discloses a grinding and polishing processing method of an ultra-precise YIG (yttrium iron garnet) single crystal, which is suitable for a planar YIG (yttrium iron garnet) single crystal (circle) prepared by a liquid phase epitaxy method, a molten salt method and a floating zone melting method, and comprises the following steps: grinding the YIG single crystal, and controlling the thickness and the total thickness deviation (TTV) of the crystal; rough polishing is carried out on the YIG single crystal, and subsurface damage of the wafer is eliminated; and finally, carrying out ultra-precision polishing on the YIG crystal to realize surface planarization with sub-nano-scale surface roughness. According to the method, the surface roughness of the yttrium iron garnet single crystal can be controlled below 1nm.

The utility model relates to the technical field of single crystal preparation by a liquid phase epitaxy method, in particular to a leading forced convection introducing device for single crystal growth by a resistance heating LPE method, which comprises a graphite crucible and a graphite heating component arranged on the outer side of the graphite crucible, one end of the graphite seed crystal rod extends into the graphite crucible and is connected with the graphite seed crystal support; the seed crystal is adhered to the bottom surface of the graphite seed crystal support; the graphite annular turbofan is arranged in the graphite crucible; the graphite annular turbofan is connected with the graphite seed rod through a jackscrew clamp; the other end of the graphite seed crystal rod is externally connected with a seed crystal lifting and rotating mechanism; and the graphite seed crystal rod drives the seed crystal and the graphite annular turbofan to do lifting and rotating motion. According to the device, the influence of adverse convection on the whole flow field is weakened, and the controllability of the whole flow field can be improved; and meanwhile, an ideal temperature field for growing high-quality silicon carbide crystals in the growth cavity is ensured.

The invention provides a silicon carbide trench MOSFET device with a three-side trench structure and a preparation method thereof, and the method comprises the steps: growing a silicon carbide epitaxy on a silicon carbide substrate, and carrying out the injection to form a P-well region; forming a first barrier layer on the P-well region, and performing injection to form a P + region; removing the first barrier layer to form a second barrier layer, and performing injection to form an N + region; removing the second barrier layer, and simultaneously performing rapid thermal annealing on the P-well region, the P + region and the N + region; forming a third barrier layer, and etching to form a gate trench region; removing the third barrier layer, and performing dry-oxygen thermal oxidation to form a gate oxide layer; forming polycrystalline silicon by using chemical vapor deposition; after the polycrystalline silicon is doped, etching is carried out to form a grid electrode; and depositing metal to form a drain electrode and a source electrode, and performing rapid thermal annealing on the drain electrode and the source electrode to form ohmic contact. By arranging the three-side groove structure, the area of the channel is increased, and conduction resistance is reduced.

The invention discloses an LTO film thickness uniformity optimization method through an APCVD method, and particularly relates to the technical field of semiconductor manufacturing, and the method comprises the following steps: S1, prefabricating a silicon wafer; s2, selecting a tungsten filament ring; s3, installing a tungsten filament ring; s4, depositing an LTO thin film; s5, measuring the thickness of the LTO thin film of the silicon wafer; and S6, confirming the service life of the tungsten filament ring. According to the LTO film thickness uniformity optimization method through the APCVD method, the silicon wafer is chamfered, stress concentration and dislocation are reduced, wafer edge breakage and inward movement of thermal stress defects are effectively prevented, a more stable substrate is provided for follow-up film deposition, a tungsten filament ring of a specific specification is selected and correctly installed, and the uniformity of the thickness of the LTO film is improved. The diffusion and transmission conditions of gas in the APCVD process can be improved, the problems of stacking faults, crystal points, self-doping and the like after epitaxy caused by non-uniform films are reduced, and the consistency and reliability of device performance are improved.

The invention discloses a semiconductor laser and a preparation method thereof, which can be used in the field of semiconductor device preparation, and the method comprises the steps: firstly, providing a first conductive type substrate; then, epitaxially growing a buffer layer of a first conduction type, a lower optical waveguide limiting layer, a quantum well active light-emitting layer, an upper optical waveguide limiting layer, a corrosion barrier layer, a current injection layer and an intrinsic ohmic contact layer on the substrate in sequence to obtain a multi-layer epitaxial layer; then, etching the multi-layer epitaxial layer to the corrosion barrier layer based on a preset pattern to form a ridge-shaped table which starts from the intrinsic ohmic contact layer and is deeply cut off to the corrosion barrier layer; and finally, performing particle doping in a region corresponding to the ridge-shaped table, and converting one sides, close to the corrosion barrier layer, of the intrinsic ohmic contact layer, the current injection layer, the corrosion barrier layer and the upper optical waveguide limiting layer into a second conduction type. Therefore, current limitation can be realized without performing multiple epitaxy like a traditional buried heterojunction, and the production cost and the process difficulty are greatly reduced.

The invention provides a buried heterojunction structure, a preparation method thereof and a laser. The preparation method comprises the following steps: primary epitaxy: growing an N-type InP buffer layer, a multi-layer quantum well structure and a P-type InP protective layer on an N-type InP substrate by using an MOCVD (Metal Organic Chemical Vapor Deposition) technology; growing an etching stop layer on the P-type InP protection layer, wherein the etching stop layer is made of an III-V group material; depositing an insulating medium as a mask on the etching stop layer, and etching the etching stop layer and the basic structure layer in a dry or wet etching mode to form a mesa structure; removing the mask on the mesa structure by wet etching; secondary epitaxy: growing a current limiting layer on the mesa structure by adopting an MOCVD (Metal Organic Chemical Vapor Deposition) technology, wherein the current limiting layer covers the whole mesa structure; and forming a funnel-shaped opening on the current limiting layer by wet etching to expose the etching stop layer. According to the invention, the difficulty of growing the current limiting layer by using the MOCVD technology is greatly reduced; the problem of current leakage is effectively suppressed; the current injection efficiency is improved; and the method has good process repeatability and controllability.

The present application relates to a kind of methods and applications of growing bismuth-doped rare-earth iron garnet BRIG crystal by guided mode pulling-top seed crystal method.For solving the problems of large internal stress, many defects, difficult to prepare thick film of single crystal in the current liquid phase epitaxy method of growing BRIG crystal;And the problems of long growth cycle, difficult to obtain seed crystal in top seed crystal method, the present application combines the fast growth of guided mode pulling crystal and the high-quality single crystal growth of top seed crystal method, and invents guided mode pulling-top seed crystal method to realize the fast growth of high-quality BRIG single crystal.First, the large-size doped rare-earth iron garnet crystal with high lattice matching and similar composition is quickly grown by guided mode pulling method, which is cut into centimeter-level seed crystal, and high-quality BRIG bulk single crystal is quickly grown by TSSG method.The crystal grown by this method has the advantages of small internal stress, less cracking, good uniformity, fast crystal growth, etc., and has obvious advantages in high-performance magneto-optical isolator.

A wafer suitable for epitaxial growth of gallium nitride (GaN) in a Metal Oxide Chemical Vapor Deposition (MOCVD) process. The wafer includes a silicon substrate having a front side and a back side and an edge extending between the front side and the back side, the edge including a front bevel surface connected to the front side and a back bevel surface connected to the back side, wherein the silicon substrate comprises an oxygen denuded silicon layer surrounding a core. The wafer further includes a protection layer being a thermally grown silicon oxide (SiO2) layer substantially covering the front bevel surface and the back bevel surface of the edge, while leaving at least a central region of the front side of the silicon substrate exposed, for preventing meltback during the MOCVD process.

The invention discloses a method for improving the light emitting performance of an AlGaInP red light Micro LED. The method comprises the following steps: S1, preparing an epitaxial structure: processing a substrate and a buffer layer, growing an etching barrier layer and an ohmic contact layer, and stacking and extending a functional layer; s2, patterning the silicon-based substrate; s3, carrying out epitaxial wafer pretreatment and Mesa etching; s4, side wall repairing and wet oxidation treatment; s5, performing secondary epitaxy and side wall passivation; s6, preparing a metal reflecting layer and a protective layer; s7, bonding and removing the substrate; s8, optimizing an n-side electrode and performance; according to the invention, the defects of low luminous efficiency and poor stability caused by side wall non-radiative recombination aggravation, carrier transverse leakage and easy side wall corrosion of the existing AlGaInP red light Micro LED in a small-size and high-PPI scene are overcome, and the synchronous improvement of the luminous performance and the working stability is realized through the preparation method of'epitaxial layer wet oxide layer design + multi-process collaborative optimization '.

The invention provides a single-mode 660nm semiconductor laser device with a superlattice structure and a preparation method of the single-mode 660nm semiconductor laser device, and belongs to the technical field of photoelectrons. The multi-quantum-well multi-quantum-well light-emitting diode sequentially comprises a GaAs substrate, a buffer layer, a sectional lower limiting layer, a lower waveguide layer, a multi-quantum-well active region, an AlInP / GaP superlattice, an upper waveguide layer, a sectional upper limiting layer, a band gap transition layer and a GaAs cap layer from bottom to top. The preparation method comprises the processes of substrate processing, buffer layer growth, V-group source switching, limiting layer and waveguide layer epitaxy, multi-quantum well and superlattice structure growth, cap layer deposition and the like. Through the segmented design of the superlattice structure and the limiting layer, the hole injection efficiency and the carrier limiting capability are improved, and the high-temperature working characteristic of the device is effectively improved. Stable output of single-mode laser in the 660nm wave band is achieved, reliable power output of 120mW can be kept in a high-temperature environment of 60 DEG C, and meanwhile, low loss, high conversion efficiency and excellent photoelectric performance are achieved.

Example methods, compositions and structures are presented whereby sub-10-nm-thick strain-relieving Si1-xGex layers can be realized by Ge ion implantation, into, and selective oxidation of, Si(111) wafers. The resulting Ge-rich layers are fully strain relaxed via a network of misfit dislocations at the Si / Si1-xGe, interface, which do not propagate through the Si1-xGex film. The dislocation network has been found to coincide with a periodic variation in the composition at the Si / Si1-xGex interface and is believed to result from the defect-medicated diffusion of Si atoms from the Si substrate through the Si1-xGex layer to the above SiO2 layer. The epitaxial growth of GaAs on such ultra-thin substrates is demonstrated, presenting a promising approach for solving the long-standing challenge of local, monolithic integration of III-V optoelectronics on the Si platform.

The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor epitaxial structure forming method and a semiconductor device.The semiconductor epitaxial structure forming method comprises the following steps that photoetching and etching are conducted on the back face of a substrate, and photoetching marks are formed; extending a first-layer first-type doped epitaxial layer on the front surface of the substrate, and spin-coating photoresist on the surface of the first-layer first-type doped epitaxial layer; or growing an oxide layer on the front surface of the substrate as a hard mask, and then spin-coating photoresist on the surface of the oxide layer; the exposure mark on the front face of the substrate is aligned with the photoetching mark on the back face of the substrate, exposure of the layer is completed, for a multi-layer epitaxial process scheme, alignment of each epitaxial layer is carried out through the method, the influence of the epitaxial process on the photoetching mark can be avoided, etching of the photoetching mark does not need to be carried out after epitaxy, and a large number of photoetching and etching processes are reduced; meanwhile, if each layer is aligned with the same alignment mark, exposure error accumulation between layers can be avoided.

The application discloses a vertical cavity surface emitting semiconductor laser based on a lateral epitaxial technology and a preparation method. The core of the structure is to solve the problem of presetting a lower DBR through the lateral epitaxial technology, to preset the DBR first, to open a window on the DBR, to grow the functional area of the laser on the upper side of the DBR through the lateral epitaxial technology, to complete the preparation of the lower DBR, and then to prepare the upper DBR and the metal electrodes on the two sides through common processes, so that the vertical cavity surface emitting laser is formed. The direction of the electric injection is perpendicular to the direction of the laser emission, and the influence of the current spreading layer of the ultraviolet band VCSEL on the light field absorption can be avoided. The application is favorable for reducing the damage to the device, improving the yield and the device performance, well utilizing the high-quality material area grown through the lateral epitaxial technology, improving the crystal quality, improving the light emitting efficiency and the service life, and the electric field direction is the non-polarized direction of the material, so that the quantum confinement Stark effect can be effectively reduced, and the reduction of the quantum efficiency and the wavelength drift of the device under a large voltage can be inhibited.

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof. The preparation method comprises the following steps: (1) providing a semiconductor structural member, wherein the semiconductor structural member comprises a substrate; the stacked structure is arranged on the surface of the substrate, and the stacked structure comprises a sacrificial layer and a channel layer which are sequentially arranged in a stacked mode in the direction away from the substrate; the false gate is arranged across the laminated structure; the side walls are arranged on the side surfaces of at least part of the false gates; the laminated structure which is not covered on the outer sides of the dummy gate and the side wall is a source-drain region; (2) etching the source and drain regions of the semiconductor structural member, and stopping on the surface of the substrate; (3) forming an inner side wall on the side surface of the sacrificial layer; (4) forming a protective layer on the side surface of the channel layer; (5) carrying out epitaxy on the laminated structure in the source and drain regions to form an epitaxial layer, and removing the protective layer; and (6) fusing the epitaxial layer, and then carrying out solid-phase epitaxy regrowth and crystallization to obtain the semiconductor device.

The application relates to the technical field of liquid phase epitaxy growth, and discloses a liquid phase epitaxy tool and a method for growing a thin film by using the same. The tool comprises a base, a sliding strip, a detachable supporting component, a mother liquid plate and a cover plate. The detachable supporting component comprises a sleeved inner core and an outer ring. The mother liquid plate is provided with a mother liquid groove for containing mother liquid. The base is provided with a first groove matched with the sliding strip, and the upper surface of the base is provided with a second groove. The sliding strip is located in the first groove, and is provided with a through hole penetrating through the thickness. The detachable supporting component is located in the through hole, and the upper surface of the detachable supporting component is used for placing a substrate. The depth of the second groove is not less than the thickness of the substrate, the width of the second groove is matched with the thickness of the outer ring, and the outer ring falls into the second groove when the sliding strip moves to above the second groove, so that the edge of the substrate protrudes from the inner core. The mother liquid plate is located on the upper surface of the base and the sliding strip. The tool can disconnect the thin film from the surrounding when the mother liquid is in a molten state, and the yield of the thin film is improved.

The invention relates to the technical field of micro electro mechanical system devices, in particular to a SON and silicon epitaxy process-based PMUT preparation method and a PMUT, and the method comprises the following steps: S1, forming a cavity on a silicon substrate by using an SON process; s2, annealing treatment is carried out, and the roughness of the silicon surface above the cavity is optimized; s3, forming a monocrystalline silicon epitaxial layer above the cavity by using a silicon epitaxial process; s4, carrying out planarization processing by using CMP, and optimizing the surface roughness of the monocrystalline silicon epitaxial layer; and S5, preparing the PMUT above the monocrystalline silicon epitaxial layer. According to the invention, the consistency and stability of device performance are improved; the process route is relatively simplified, the process steps and equipment investment are reduced, the production cost is reduced, and large-scale industrial production is facilitated; the monocrystalline silicon epitaxial layer has good crystal quality and mechanical property, and the influence of structural defects on the performance of the device is reduced; proper materials can be selected for the piezoelectric layer according to different application requirements, and the sensitivity and reliability of the PMUT are further improved.

Embodiments of the present disclosure relate to a method of manufacturing a bipolar transistor and a bipolar transistor obtained by such a method. A method of manufacturing a bipolar transistor includes forming a stack of a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer on a substrate. An opening is formed in the stack to reach the substrate. An epitaxy process forms a collector of the transistor on the substrate and selectively etches a ring-shaped opening in the third layer. An intrinsic portion of a base is then formed by epitaxy on the collector, the intrinsic portion being separated from the third layer by the ring-shaped opening. A junction between the collector and the intrinsic portion of the base is surrounded by the second layer. An emitter is formed on the intrinsic portion and the third layer is removed. A semiconductor layer is selectively deposited on the second layer and in direct contact with the intrinsic portion to form a non-intrinsic portion of the base.

The invention discloses a 950V super-junction MOS terminal structure of a deep groove filling structure and a manufacturing method of the 950V super-junction MOS terminal structure, a device is additionally provided with Ptop floating P column connecting layer injection, a terminal region polycrystalline silicon field plate and a terminal region metal field plate, the whole device is subjected to secondary epitaxy through an N-type substrate, and a plurality of functional layers are expanded according to optimal conditions. According to the invention, a deep groove filling process is utilized, and the structure design and the manufacturing process are optimized, so that the on-resistance is effectively reduced, the breakdown voltage grade and the stability are improved, the switching loss of a terminal part is optimized, and the overall performance is improved; n-type epitaxy is grown on a substrate twice to optimize the charge imbalance phenomenon caused by the etching angle problem in deep groove etching, due to the fact that the resistivity of the two times of epitaxy is different, charge balance of the whole N column and the whole P column is completed to the maximum extent, P-type light injection is conducted on the surface of a terminal area, the floating P columns in the terminal area are connected, and the terminal area is formed. And the surface electric field distribution is optimized, so that the more stable breakdown characteristic is realized.

The application discloses a diamond mosaic splicing homogeneous epitaxial growth method and system based on AI intelligent control, and belongs to the technical field of single crystal diamond material preparation. A plurality of single crystal diamond substrates are spliced into a large-size deposition base in a mosaic manner; an initial geometric shape and a micro-gap distribution of a splicing seam are identified through a pre-trained AI visual detection model; a global process parameter combination and a staged deposition strategy for promoting lateral epitaxy are generated by combining a homogeneous epitaxial growth thermodynamic database and an AI process optimization model; during the growth process, a morphology evolution image and plasma state data of the splicing seam area are collected in real time, and a gap healing trend is predicted by an AI closed-loop control model, and the global process parameters are dynamically adjusted. Through AI accurate control of the global process parameters, the lateral epitaxy and the grain boundary migration at the splicing seam can be controlled to occur, and finally a seamless integrated large-size single crystal diamond is obtained.

The invention provides a method for growing a germanium epitaxial layer in a deep silicon groove, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: photoetching and etching a Si / SiO2 substrate to form a deep silicon groove with a preset depth, and soaking the Si / SiO2 substrate with the deep silicon groove in a TMAH solution to perform first cleaning; and then soaking the Si / SiO2 substrate with the deep silicon groove in a wet-process chemical cleaning solution so as to carry out secondary cleaning. And finally, performing a selective germanium epitaxial process in the deep silicon groove so as to form a germanium epitaxial layer. According to the technical scheme, the TMAH cleaning process is added before the traditional cleaning process, so that the optimization of the roughness of the side wall of the deep silicon groove is realized, a good epitaxial foundation is provided for subsequent germanium epitaxy, the quality of the germanium epitaxial layer can be improved, the situation that small holes appear after the germanium epitaxial layer is ground to be flat through CMP (Chemical Mechanical Polishing) surface is avoided, and the quality of the germanium epitaxial layer is improved. The performance of the germanium device is stabilized; and the loss of the optical chip waveguide is reduced.

The application provides a two-dimensional nanometer patterning substrate and a preparation method. A graphene film is prepared on a supporting substrate; a metal film is deposited on the graphene film; the metal film is converted into discontinuous metal nanoparticles; the graphene pattern is etched by using the metal nanoparticles as a mask; the metal nanoparticle mask on the graphene pattern is removed; and a nitride material is grown on the graphene pattern. Compared with existing electron beam exposure, nano-imprinting and nano-sphere mask schemes, the two-dimensional nanometer patterning substrate and the preparation method are simple and feasible, and the cost can be effectively controlled. In addition, the two-dimensional nanometer patterning substrate and the preparation method are suitable for large-size and batch construction, and the above technical details are suitable for the advantages. Finally, the nanometer pattern size and other geometric parameters have high flexibility, which is important for promoting subsequent lateral epitaxy of high-quality nitride materials.

The application provides a preparation method of a diamond CMOS inverter and the inverter, and relates to the technical field of super-wide band gap semiconductor field effect transistor devices. The method comprises the following steps: introducing boron elements and nitrogen elements into a microwave plasma chemical vapor deposition chamber through a gaseous source or a solid source, so as to grow an n-type diamond epitaxy on a diamond substrate layer; treating the diamond substrate after depositing a metal mask by using hydrogen plasma, so as to prepare a p-type active region on a second n-type diamond epitaxy, and the first n-type diamond epitaxy becomes an n-type active region; and preparing a source electrode, a drain electrode, an NMOS field effect tube gate dielectric layer, a PMOS field effect tube gate dielectric layer and a gate electrode on the p-type active region and the n-type active region. In this way, the hydrogen-terminated diamond preparation process and the diamond boron-nitrogen co-doping process are used to simultaneously form the p-type active region and the n-type active region on a single monocrystalline diamond surface, so that the preparation of the CMOS inverter on the single diamond is realized.

The invention discloses a space-time modulation hydride vapor phase epitaxy reaction chamber, equipment and a method. Wherein the reaction chamber comprises a reaction chamber which is provided with a water cooling side wall and is limited by a flange to form a cavity, and the interior of the cavity is divided into an upper part, a middle part and a lower part; the metal source reaction boat assembly is positioned at the upper half part of the reaction chamber cavity; the space-time modulation reaction growth device is positioned in the middle of the reaction chamber cavity; the heating device and the tail gas collecting device are positioned at the lower half part of the reaction chamber cavity; and the central gas circuit device is positioned at the axis position of the cavity of the reaction chamber and is connected with the metal source reaction boat assembly at the upper half part of the cavity and the space-time modulation reaction growth device in the middle of the cavity. According to the invention, the growth time is controlled through the combination of time modulation and space modulation, so that the thickness of the material thin layer is accurately controlled, the flexibility of growth program setting is improved, the rapid epitaxial growth of the ultra-thin layer and ultra-thick layer material stacking structure is realized, and the low-cost epitaxial growth requirement of a semiconductor device with a complex structure is met.

The present invention relates to a single-crystalline Al2O3 dielectric compatible with two-dimensional materials and an integrated device thereof. A single-crystalline Al thin film is produced on a single-crystalline graphene / germanium (110) substrate via the van der Waals (vdW) epitaxy approach, the single-crystalline Al thin film is peeled off from the graphene / germanium substrate, and intercalative oxidation is performed to produce the single-crystalline Al2O3 dielectric compatible with two-dimensional materials on the lower surface of the single-crystalline Al thin film. The gate leakage current (J<1×10−5 A cm−2), interface state density (Dit=8.4×109 cm−2 eV−1), and dielectric strength (Ebd=17.4 MV / cm) of the single-crystalline Al2O3 dielectric obtained in the present invention can meet the requirements of the international roadmap for devices and systems (IRDS) for low power consumption devices.

This invention discloses an antimony compound multi-wavelength laser material, its preparation method, and its applications. It relates to the field of semiconductor laser technology and solves the problems of existing antimony compound-based semiconductor laser materials, such as difficulty in achieving multi-wavelength laser emission through single epitaxial growth, and the complex epitaxial processes, limited interlayer interface quality, and insufficient precision in composition control of existing multi-wavelength laser materials. The antimony compound multi-wavelength laser material provided by this invention comprises, from bottom to top, a substrate, a monolayer of graphene, a buffer layer, a lower confinement layer, a lower waveguide layer, a dielectric layer, a quantum well structure, an upper waveguide layer, an upper confinement layer, and a capping layer; wherein the quantum well structure includes In… x3 Ga 1‑x3 As y3 Sb 1‑y3 And Al x4 Ga 1‑ x4 As y4 Sb 1‑y4 Laser materials can be used to fabricate mid-infrared semiconductor lasers, achieving selective epitaxial growth, multi-channel spectral acquisition, and broadband coverage through single-epitaxy and controlled photolithography patterns.

The present disclosure relates generally to materials including cyclic compounds that are adhesive below the temperature at which pyrolysis occurs, and which are also adhesive at higher temperatures including the temperatures used in the regime for growing SiC crystals, which may be above 2000° C, or for SiC or GaN epitaxy, which may be above 1500° C.

This disclosure provides a method, system, and epitaxial wafer for improving particulate contamination of silicon wafers during epitaxy. The method includes: selecting at least one test silicon wafer from a batch of silicon wafers to be processed, and determining a target power range to be applied to the epitaxial furnace based on the test results of the test silicon wafer; adjusting the effective power applied to the epitaxial furnace to the target power range before the silicon wafer to be processed is fed into the epitaxial chamber of the epitaxial furnace, so that the temperature inside the epitaxial chamber is within a target temperature range; maintaining the effective power of the epitaxial furnace within the target power range until the silicon wafer to be processed enters the epitaxial chamber, thereby using the target temperature range to suppress thermal deformation of the silicon wafer to be processed; and growing an epitaxial layer on the surface of the silicon wafer to be processed after it enters the epitaxial chamber. This disclosure can effectively reduce particulate contamination of the silicon wafer to be processed during epitaxy.

The present invention discloses a SiCMOSFET device resistant to single-particle irradiation and a method for manufacturing the same. The device sequentially adopts the method of second-conductivity-type epitaxy, JFET region trench etching, and first-conductivity-type SiC epitaxy on the first-conductivity-type drift region, and utilizes a deep second-conductivity-type well region to form a semi-superjunction structure near the surface of the device. While ensuring the reverse withstand voltage of the device, the first-conductivity-type doping concentration in the JFET region is increased, thereby reducing the resistance of the JFET region. An additional thickened oxide layer is provided above the JFET region to reduce the electric field strength of the gate dielectric region during single-particle irradiation. At the same time, the doping concentration of the second-conductivity-type epitaxial region slowly decreases in a gradient in the direction pointing to the drift region. This structure can simultaneously improve the device's resistance to single-particle burnout and single-particle gate penetration, and improve the device's static electrical characteristics. This structure can be used in combination with irradiation reinforcement measures such as an epitaxial buffer layer and local SOI to further enhance the radiation resistance.