212 results about "Epitaxy" patented technology

The invention discloses a semiconductor laser and a preparation method thereof, which can be used in the field of semiconductor device preparation, and the method comprises the steps: firstly, providing a first conductive type substrate; then, epitaxially growing a buffer layer of a first conduction type, a lower optical waveguide limiting layer, a quantum well active light-emitting layer, an upper optical waveguide limiting layer, a corrosion barrier layer, a current injection layer and an intrinsic ohmic contact layer on the substrate in sequence to obtain a multi-layer epitaxial layer; then, etching the multi-layer epitaxial layer to the corrosion barrier layer based on a preset pattern to form a ridge-shaped table which starts from the intrinsic ohmic contact layer and is deeply cut off to the corrosion barrier layer; and finally, performing particle doping in a region corresponding to the ridge-shaped table, and converting one sides, close to the corrosion barrier layer, of the intrinsic ohmic contact layer, the current injection layer, the corrosion barrier layer and the upper optical waveguide limiting layer into a second conduction type. Therefore, current limitation can be realized without performing multiple epitaxy like a traditional buried heterojunction, and the production cost and the process difficulty are greatly reduced.

The present application relates to a kind of methods and applications of growing bismuth-doped rare-earth iron garnet BRIG crystal by guided mode pulling-top seed crystal method.For solving the problems of large internal stress, many defects, difficult to prepare thick film of single crystal in the current liquid phase epitaxy method of growing BRIG crystal;And the problems of long growth cycle, difficult to obtain seed crystal in top seed crystal method, the present application combines the fast growth of guided mode pulling crystal and the high-quality single crystal growth of top seed crystal method, and invents guided mode pulling-top seed crystal method to realize the fast growth of high-quality BRIG single crystal.First, the large-size doped rare-earth iron garnet crystal with high lattice matching and similar composition is quickly grown by guided mode pulling method, which is cut into centimeter-level seed crystal, and high-quality BRIG bulk single crystal is quickly grown by TSSG method.The crystal grown by this method has the advantages of small internal stress, less cracking, good uniformity, fast crystal growth, etc., and has obvious advantages in high-performance magneto-optical isolator.

The invention provides a single-mode 660nm semiconductor laser device with a superlattice structure and a preparation method of the single-mode 660nm semiconductor laser device, and belongs to the technical field of photoelectrons. The multi-quantum-well multi-quantum-well light-emitting diode sequentially comprises a GaAs substrate, a buffer layer, a sectional lower limiting layer, a lower waveguide layer, a multi-quantum-well active region, an AlInP / GaP superlattice, an upper waveguide layer, a sectional upper limiting layer, a band gap transition layer and a GaAs cap layer from bottom to top. The preparation method comprises the processes of substrate processing, buffer layer growth, V-group source switching, limiting layer and waveguide layer epitaxy, multi-quantum well and superlattice structure growth, cap layer deposition and the like. Through the segmented design of the superlattice structure and the limiting layer, the hole injection efficiency and the carrier limiting capability are improved, and the high-temperature working characteristic of the device is effectively improved. Stable output of single-mode laser in the 660nm wave band is achieved, reliable power output of 120mW can be kept in a high-temperature environment of 60 DEG C, and meanwhile, low loss, high conversion efficiency and excellent photoelectric performance are achieved.

Embodiments of the present disclosure relate to a method of manufacturing a bipolar transistor and a bipolar transistor obtained by such a method. A method of manufacturing a bipolar transistor includes forming a stack of a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer on a substrate. An opening is formed in the stack to reach the substrate. An epitaxy process forms a collector of the transistor on the substrate and selectively etches a ring-shaped opening in the third layer. An intrinsic portion of a base is then formed by epitaxy on the collector, the intrinsic portion being separated from the third layer by the ring-shaped opening. A junction between the collector and the intrinsic portion of the base is surrounded by the second layer. An emitter is formed on the intrinsic portion and the third layer is removed. A semiconductor layer is selectively deposited on the second layer and in direct contact with the intrinsic portion to form a non-intrinsic portion of the base.

The application discloses a diamond mosaic splicing homogeneous epitaxial growth method and system based on AI intelligent control, and belongs to the technical field of single crystal diamond material preparation. A plurality of single crystal diamond substrates are spliced into a large-size deposition base in a mosaic manner; an initial geometric shape and a micro-gap distribution of a splicing seam are identified through a pre-trained AI visual detection model; a global process parameter combination and a staged deposition strategy for promoting lateral epitaxy are generated by combining a homogeneous epitaxial growth thermodynamic database and an AI process optimization model; during the growth process, a morphology evolution image and plasma state data of the splicing seam area are collected in real time, and a gap healing trend is predicted by an AI closed-loop control model, and the global process parameters are dynamically adjusted. Through AI accurate control of the global process parameters, the lateral epitaxy and the grain boundary migration at the splicing seam can be controlled to occur, and finally a seamless integrated large-size single crystal diamond is obtained.

The application provides a preparation method of a diamond CMOS inverter and the inverter, and relates to the technical field of super-wide band gap semiconductor field effect transistor devices. The method comprises the following steps: introducing boron elements and nitrogen elements into a microwave plasma chemical vapor deposition chamber through a gaseous source or a solid source, so as to grow an n-type diamond epitaxy on a diamond substrate layer; treating the diamond substrate after depositing a metal mask by using hydrogen plasma, so as to prepare a p-type active region on a second n-type diamond epitaxy, and the first n-type diamond epitaxy becomes an n-type active region; and preparing a source electrode, a drain electrode, an NMOS field effect tube gate dielectric layer, a PMOS field effect tube gate dielectric layer and a gate electrode on the p-type active region and the n-type active region. In this way, the hydrogen-terminated diamond preparation process and the diamond boron-nitrogen co-doping process are used to simultaneously form the p-type active region and the n-type active region on a single monocrystalline diamond surface, so that the preparation of the CMOS inverter on the single diamond is realized.

The present invention relates to a single-crystalline Al2O3 dielectric compatible with two-dimensional materials and an integrated device thereof. A single-crystalline Al thin film is produced on a single-crystalline graphene / germanium (110) substrate via the van der Waals (vdW) epitaxy approach, the single-crystalline Al thin film is peeled off from the graphene / germanium substrate, and intercalative oxidation is performed to produce the single-crystalline Al2O3 dielectric compatible with two-dimensional materials on the lower surface of the single-crystalline Al thin film. The gate leakage current (J<1×10−5 A cm−2), interface state density (Dit=8.4×109 cm−2 eV−1), and dielectric strength (Ebd=17.4 MV / cm) of the single-crystalline Al2O3 dielectric obtained in the present invention can meet the requirements of the international roadmap for devices and systems (IRDS) for low power consumption devices.

This invention discloses an antimony compound multi-wavelength laser material, its preparation method, and its applications. It relates to the field of semiconductor laser technology and solves the problems of existing antimony compound-based semiconductor laser materials, such as difficulty in achieving multi-wavelength laser emission through single epitaxial growth, and the complex epitaxial processes, limited interlayer interface quality, and insufficient precision in composition control of existing multi-wavelength laser materials. The antimony compound multi-wavelength laser material provided by this invention comprises, from bottom to top, a substrate, a monolayer of graphene, a buffer layer, a lower confinement layer, a lower waveguide layer, a dielectric layer, a quantum well structure, an upper waveguide layer, an upper confinement layer, and a capping layer; wherein the quantum well structure includes In… x3 Ga 1‑x3 As y3 Sb 1‑y3 And Al x4 Ga 1‑ x4 As y4 Sb 1‑y4 Laser materials can be used to fabricate mid-infrared semiconductor lasers, achieving selective epitaxial growth, multi-channel spectral acquisition, and broadband coverage through single-epitaxy and controlled photolithography patterns.

The present disclosure relates generally to materials including cyclic compounds that are adhesive below the temperature at which pyrolysis occurs, and which are also adhesive at higher temperatures including the temperatures used in the regime for growing SiC crystals, which may be above 2000° C, or for SiC or GaN epitaxy, which may be above 1500° C.

This disclosure provides a method, system, and epitaxial wafer for improving particulate contamination of silicon wafers during epitaxy. The method includes: selecting at least one test silicon wafer from a batch of silicon wafers to be processed, and determining a target power range to be applied to the epitaxial furnace based on the test results of the test silicon wafer; adjusting the effective power applied to the epitaxial furnace to the target power range before the silicon wafer to be processed is fed into the epitaxial chamber of the epitaxial furnace, so that the temperature inside the epitaxial chamber is within a target temperature range; maintaining the effective power of the epitaxial furnace within the target power range until the silicon wafer to be processed enters the epitaxial chamber, thereby using the target temperature range to suppress thermal deformation of the silicon wafer to be processed; and growing an epitaxial layer on the surface of the silicon wafer to be processed after it enters the epitaxial chamber. This disclosure can effectively reduce particulate contamination of the silicon wafer to be processed during epitaxy.

This invention provides a trench-type superjunction field-effect transistor and its fabrication method. Conductive pillars are formed in a first trench using an epitaxial filling method, reducing the aspect ratio of the formed conductive pillars and resulting in a smaller pitch size. Then, a third epitaxial layer with multiple sub-epitaxy layers is formed on a second epitaxial layer using a multilayer epitaxial process, with simultaneous epitaxy and etching to form well regions within the multiple sub-epitaxy layers. This significantly reduces the thermal budget and photolithography costs during the superjunction field-effect transistor fabrication process, and also results in a smaller pitch size for the well regions formed in the sub-epitaxy layers of the third epitaxial layer. The combination of these processes results in narrower P-type conductive pillars and a wider N-type epitaxial layer containing the P-type conductive pillars. This slows down the switching speed of the body diode region formed by the P-type well region, P-type conductive pillars, and N-type epitaxial layer during device depletion and expansion, thereby reducing transient capacitance and improving the device's EMI performance.

The invention relates to a solid phase epitaxy method of an amorphous semiconductor over a crystalline substrate. A semiconductor device (200) includes: a semiconductor substrate (202); a first crystalline silicon layer (204) over the semiconductor substrate (202); an electronic component (206, 208) extending into the first crystalline silicon layer (204); a second crystalline silicon layer (224) over the electronic component (206, 208) and the first crystalline silicon layer (204); and a distributed silicon oxide inclusion layer (219) between the first crystalline silicon layer (204) and the second crystalline silicon layer (224).

A method includes forming a fin in a substrate. The fin is etched to create a source / drain recess. A source / drain feature is formed in the source / drain recess, in which a lattice constant of the source / drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source / drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.

A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

The application discloses a transistor with low parasitic capacitance, which comprises a substrate, a ground metal layer arranged on a second surface of the substrate, an epitaxial layer arranged on a first surface of the substrate, and an electrode layer arranged on the epitaxial layer, wherein the epitaxial layer comprises a gate region, a source region and a drain region, the electrode layer of the source region and the electrode layer of the drain region comprise an ohmic contact layer and an upper metal layer arranged on the ohmic contact layer, and a part of the drain region is doped to form an insulating region by epitaxy. A high-resistance insulating region is formed in the part of the drain region, which obviously reduces the parasitic capacitance of the source and the drain and improves the radio frequency performance of the radio frequency device.

A system for controlling flatness of an epitaxial semiconductor wafer includes a polishing assembly, a measuring device, and a computer system in communication with the polishing assembly and the measuring device. The computer system stores and executes instructions that cause the computer system to measure one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer profile produced by an epitaxy apparatus, polish a semiconductor wafer using a polishing assembly and measure the polished semiconductor wafer to determine a surface profile of the polished wafer, generate a predicted post-epitaxy surface profile of the polished wafer by comparing the surface profile of the polished wafer and the determined epitaxial deposition layer profile produced by the epitaxy apparatus, determine a predicted post-epitaxy parameter based on the predicted post-epitaxy surface profile and adjust, based on the predicted post-epitaxy parameter, a process condition of the polishing assembly.

A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

The invention belongs to the technical field of diamond cultivation, and discloses a splicing epitaxy method and system of single crystal diamond, a terminal and a storage medium, the method comprises the following steps: obtaining a single crystal diamond substrate, and carrying out first epitaxial growth on the single crystal diamond substrate to obtain a single crystal diamond epitaxial layer; performing vertical cutting treatment on the monocrystal diamond epitaxial layer to obtain a first epitaxial layer and a second epitaxial layer; carrying out polishing treatment, first etching treatment and arrangement treatment on the first epitaxial layer and the second epitaxial layer to obtain an arranged epitaxial layer; and carrying out second etching treatment, joint repair growth and second epitaxial growth on the arranged epitaxial layer to obtain the target monocrystal diamond. According to the method, epitaxial growth and vertical cutting treatment are carried out on the single crystal diamond substrate, the in-plane deflection angle consistency of spliced crystals can be guaranteed, arrangement and seam repair are carried out according to growth lines, and the splicing success rate and growth quality of the large-size single crystal diamond are effectively improved.

The invention provides a nickel-based single-crystal high-temperature alloy component laser epitaxy repairing method based on energy field regulation and dynamic crystal selection. The nickel-based single-crystal high-temperature alloy component laser epitaxy repairing method comprises the steps that a damaged area is subjected to cleaning treatment and three-dimensional scanning, matrix crystallographic orientation is obtained, a three-dimensional thermal-structure finite element simulation model is established, and a repairing basic process is determined; homogeneous alloy powder is adopted, a laser machining head with a coaxial powder feeding nozzle is used for repairing the damaged area, in the repairing process, auxiliary induction heating is conducted, and the temperature field and the morphology of a molten pool are monitored; if the G / R is lower than the preset critical threshold value, the auxiliary induction heating power is dynamically enhanced; if the tail of the molten pool is disturbed, an ultrasonic vibration field is applied to the molten pool; and treating after repairing. A repair system is also provided. According to the method, the epitaxial growth of the single crystal consistent with the crystallographic orientation of the matrix can be dynamically guided, so that the nickel-based single crystal high-temperature alloy component can be repaired, the repair success rate and the structure consistency are remarkably improved, and the epitaxial proportion of the single crystal is increased to 95% or above.

A lift-off method includes joining a transfer substrate to a face side of an optical device layer of an optical device wafer with a joining member interposed therebetween, thereby making up a composite substrate, applying a pulsed laser beam having a wavelength transmittable through the epitaxy substrate and absorbable by a buffer layer, from a reverse side of the epitaxy substrate of the optical device wafer, thereby breaking the buffer layer, and an optical device layer transferring step of peeling off the epitaxy substrate from the optical device layer and transferring the optical device layer to the transfer substrate. The optical device layer transferring step includes the step of applying a bending moment to an area of the composite substrate that includes an outer peripheral portion thereof while holding an area of the composite substrate that includes a central portion thereof.

This invention discloses a method for improving silicon dross on the back of a substrate after epitaxy, comprising a back-sealing step and an epitaxial step. In the back-sealing step, the polycrystalline temperature is controlled at 600°C to 650°C, and silane is used as a raw material. At the polycrystalline temperature, the silane decomposes and precipitates to form a polycrystalline film. After back-sealing in the polycrystalline step, the substrate silicon wafer is polished and then proceeds to the epitaxial step. This invention adjusts the polycrystalline temperature in the polycrystalline back-sealing step to control the physical properties of the substrate wafer after the formation of the polycrystalline film, thereby improving the back-side silicon dross problem after epitaxy.

The invention belongs to the technical field of optoelectronic devices, and particularly relates to a planar metal grating laser based on two different gratings and with a phase interval of lambda / 2, which comprises a gain chip, a gain chip optical waveguide, an optical waveguide substrate, a back optical waveguide, an annular resonance optical waveguide and a planar metal grating. A unique outer cavity structure is adopted, a traditional interlayer semiconductor grating is replaced by two metal plane gratings with similar grating constants and a phase difference of lambda / 2, the advantages that the plane metal gratings do not need to be etched and are smoother and more regular are utilized, and a'mouth-to-mouth 'coupling butt joint mode of a gain chip and an optical waveguide substrate is combined; the covering layer grows on the plane metal grating, and the high-reflection HR film is plated on the covering layer, so that the grating reflection efficiency is effectively improved, the optical energy loss of the optical waveguide is reduced, meanwhile, secondary epitaxy is omitted, the process is simplified, and the cost is reduced.

This invention relates to the field of semiconductor manufacturing technology, specifically disclosing a method for processing heavily doped substrate silicon wafers and the epitaxial wafers formed therefrom. This invention adjusts the process steps of traditional processing methods for heavily doped substrate silicon wafers with a composite back-sealing structure of "polysilicon + silicon dioxide". After the polysilicon layer is deposited on the substrate, edge polishing is performed first to remove polysilicon from the chamfered surface, followed by the deposition of the silicon dioxide layer. This process optimization ensures that the junction between the flat back surface and the chamfered surface of the substrate is always completely covered by the silicon dioxide layer, avoiding polysilicon deposition and protrusion formation during epitaxy caused by exposure of monocrystalline silicon. This invention effectively solves problems such as lithography machine vacuum alarms and defocus defects caused by back edge protrusions in existing processes, significantly improving the flatness of the epitaxial wafer and the manufacturing yield for end customers.

The present application relates to the technical field of semiconductor, in particular to a kind of stacked polycrystalline or single-crystal-like nanosheet device and its preparation method, comprising the following steps: forming multilayer stacked nanosheet structure on substrate;By lithography and etching process, define active region, and form gate structure;Metal-induced window is etched out on one side of gate structure, and polycrystalline or single-crystal-like nanosheet channel is formed by metal-induced multilayer stacked amorphous nanosheet crystallization;Contact hole is etched out on the other side of gate structure, and second-stage silicide is formed;By interconnection via process, the integration of stacked polycrystalline or single-crystal-like nanosheet device is completed.The present application not only simplifies the complexity of traditional epitaxy process, reduces production cost, but also effectively solves the problem of parasitic channel effect, provides a practical solution for the manufacture of high-performance transistor under advanced process node.

The application provides a metal substrate based nitride template, relates to the technical field of semiconductors and communication, and comprises a metal substrate, a two-dimensional material film, an inert material pattern mask layer and a nitride epitaxial layer; the surface of the two-dimensional material film is subjected to activation treatment for providing nucleation sites for growth of the nitride material and inhibiting interface reaction in a high-temperature epitaxial process; the inert material pattern mask layer realizes selective epitaxy of the nitride material, thereby realizing lateral over-epitaxial growth, reducing dislocation density in the nitride epitaxial layer and improving crystal quality of the epitaxial layer. The application also provides a preparation method and application of the template; the composite metal substrate structure of the metal substrate / two-dimensional material film / inert material pattern mask layer can realize direct high-temperature epitaxial growth of high-quality and stress-free nitride material, the template has high scalability, and is suitable for epitaxy and devices of deep ultraviolet LEDs and second-generation semiconductor materials such as GaAs and InP.

The invention provides a silicon carbide epitaxial growth system, and relates to the technical field of silicon carbide epitaxy. The system comprises a wafer bearing disc, a doping detection module, a partition air inlet module and a doping control module, the wafer bearing disc is used for bearing a silicon carbide wafer; the doping detection module collects the doping concentration of the wafer edge and the wafer center epitaxial layer in real time; the partition gas inlet module comprises an edge gas inlet channel and a central gas inlet channel which are used for conveying doped gas to the edge and the central area of the wafer respectively; and the doping control module dynamically adjusts the doping gas concentration at the edge and the center of the wafer according to the difference of the doping concentration of the epitaxial layer at the edge and the center of the wafer, which is acquired in real time, so that the difference of the doping concentration at the edge and the center of the epitaxial layer is minimized. On the premise of not influencing the uniformity of the growth thickness of the epitaxial layer, the doping concentration difference between the edge and the center of the silicon carbide epitaxial layer can be reduced.

Methods of forming red light emitters via two-dimensional (2D) material assisted epitaxy and related articles, devices, and systems are generally described.

This invention discloses a method for fabricating gallium nitride (GaN) thin films and Micro-LED devices based on patterned graphene masks. A graphene layer is obtained by PECVD deposition on a GaN substrate. An etching process is then used to obtain a graphene mask structure pattern with elongated strips or a matrix arrangement of cubes. MOCVD epitaxy is employed, and by changing conditions such as temperature, pressure, and V / III ratio during MOCVD growth, the nucleation of GaN along the steps of the window and mask boundary is effectively controlled. Through lateral epitaxial growth at different times, GaN thin films with low dislocation density and high-performance Micro-LED devices are obtained.

Photonic integrated circuit (103, 203, 403, 754) comprising: a laser (104, 204, 404) over an optical waveguide (205, 312, 405); and an on-chip insulator (108, 208, 308, 408, 508) optically coupled to the laser (104, 204, 404), the on-chip insulator (108, 208, 308, 408, 508) comprising the optical waveguide (205, 312, 405), a magneto-optical garnet film (228, 328, 428, 528) grown in liquid phase epitaxy, coupled to a first subsection of the optical waveguide (205, 312, 405), and a grating-matched substrate (229, 429) on the garnet film (228, 328, 428, 528), wherein at least a second subsection of the optical waveguide (205, 312, 405) and / or an oxide coating (406) is formed on the laser (104, 204, 404), and wherein the garnet film (228, 328, 428, 528) lies below an upper surface of the oxide coating (406).

This invention relates to organic functional thin films, specifically to a method for growing controllable number of layers using solvent vapor-assisted growth. p A method for preparing MSB molecular crystal thin films, and the application of these films in generating superoxide ions under light irradiation for antibacterial protection. This method addresses the limitations of existing solution drop casting epitaxy methods for preparing... p To address the problems of uncontrollable layer number, limited area, and insufficient reactive oxygen generation efficiency in MSB molecular crystal thin films, this invention utilizes toluene vapor atmospheres of varying concentrations to control the solvent evaporation rate, thereby achieving... p The few-layer, large-area, and uniform growth of MSB molecular crystal thin films allows for the regulation of molecular arrangement and electronic structure, promoting electron localization and efficient electron transfer to oxygen molecules under illumination, thus significantly improving the generation efficiency and stability of superoxide ions.