472 results about "Epitaxy" patented technology

The invention discloses a method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip. The method comprises the following steps: S1, preparing an epitaxial structure: processing a substrate and a buffer layer, growing an etching barrier layer and an ohmic contact layer, and carrying out stacking epitaxy on a functional layer; s2, patterning the silicon-based substrate: preparing a dielectric layer and a metal structure; s3, diamond ohmic contact layer integration: processing a p-type conductive diamond film layer, and carrying out metal reflection and bonding; s4, removing the substrate and forming an n-type structure: stripping the substrate to be in n-type contact; s5, back-end process integration: preparing an electrode and an optical structure; according to the invention, the heat dissipation performance of the chip is significantly improved; the series resistance is reduced by 30%-50%; the resistivity of the p / n type diamond ohmic contact layer is reduced by 1-2 orders of magnitude compared with ITO; gaAs material light absorption and metal shading are avoided, and the red light transmittance is improved from 75% to more than 90% by combining with the micro lens array; the method is compatible with existing MOCVD, CVD and photoetching processes, large-scale production of wafers of 2-12 inches can be achieved, and the manufacturing cost is reduced.

The invention provides an AlGaN film growth method and an AlGaN film, relates to the technical field of semiconductor material epitaxy, and aims to solve the technical problem of high defect density of an AlGaN film grown based on a silicon carbide substrate in the prior art. The method comprises the following steps: preparing a substrate, and cleaning the substrate; putting the cleaned substrate into high-temperature MOCVD (Metal Organic Chemical Vapor Deposition) equipment, and introducing a metal organic source for appointed time, so that metal atoms are adsorbed on the growth surface of the substrate; carrying out metal atom desorption treatment on the substrate adsorbed with the metal atoms for a specified time to obtain a target substrate; and growing an AlGaN film on the growth surface of the target substrate. According to the method, the step density of the surface of the substrate is reduced through metal atom adsorption and desorption processes, and an oxide layer on the surface is effectively removed, so that the crystal quality and the surface smoothness of the AlGaN film are improved.

The invention relates to a method for improving epitaxial growth quality of a tunnel junction cascade semiconductor laser. The invention innovatively provides a strain superlattice gradient repair technology. By designing a low-temperature low-speed nucleation-high-temperature high-speed epitaxy composite growth mode, a periodic superlattice buffer layer is introduced to a tunnel junction interface. Wherein lattice strain relaxation is achieved at the rate of 0.5-2 / s in the low-temperature stage, defect coverage is completed at the rate of 4-8 / s in the high-temperature stage, and dislocation line bending is terminated on a superlattice interface through thermodynamic regulation and control. Compared with the traditional process, the scheme can obviously improve the crystal quality, and does not increase the specific contact resistance of the tunnel junction interface.

The invention discloses a grinding and polishing processing method of an ultra-precise YIG (yttrium iron garnet) single crystal, which is suitable for a planar YIG (yttrium iron garnet) single crystal (circle) prepared by a liquid phase epitaxy method, a molten salt method and a floating zone melting method, and comprises the following steps: grinding the YIG single crystal, and controlling the thickness and the total thickness deviation (TTV) of the crystal; rough polishing is carried out on the YIG single crystal, and subsurface damage of the wafer is eliminated; and finally, carrying out ultra-precision polishing on the YIG crystal to realize surface planarization with sub-nano-scale surface roughness. According to the method, the surface roughness of the yttrium iron garnet single crystal can be controlled below 1nm.

The utility model relates to the technical field of single crystal preparation by a liquid phase epitaxy method, in particular to a leading forced convection introducing device for single crystal growth by a resistance heating LPE method, which comprises a graphite crucible and a graphite heating component arranged on the outer side of the graphite crucible, one end of the graphite seed crystal rod extends into the graphite crucible and is connected with the graphite seed crystal support; the seed crystal is adhered to the bottom surface of the graphite seed crystal support; the graphite annular turbofan is arranged in the graphite crucible; the graphite annular turbofan is connected with the graphite seed rod through a jackscrew clamp; the other end of the graphite seed crystal rod is externally connected with a seed crystal lifting and rotating mechanism; and the graphite seed crystal rod drives the seed crystal and the graphite annular turbofan to do lifting and rotating motion. According to the device, the influence of adverse convection on the whole flow field is weakened, and the controllability of the whole flow field can be improved; and meanwhile, an ideal temperature field for growing high-quality silicon carbide crystals in the growth cavity is ensured.

The invention provides a silicon carbide trench MOSFET device with a three-side trench structure and a preparation method thereof, and the method comprises the steps: growing a silicon carbide epitaxy on a silicon carbide substrate, and carrying out the injection to form a P-well region; forming a first barrier layer on the P-well region, and performing injection to form a P + region; removing the first barrier layer to form a second barrier layer, and performing injection to form an N + region; removing the second barrier layer, and simultaneously performing rapid thermal annealing on the P-well region, the P + region and the N + region; forming a third barrier layer, and etching to form a gate trench region; removing the third barrier layer, and performing dry-oxygen thermal oxidation to form a gate oxide layer; forming polycrystalline silicon by using chemical vapor deposition; after the polycrystalline silicon is doped, etching is carried out to form a grid electrode; and depositing metal to form a drain electrode and a source electrode, and performing rapid thermal annealing on the drain electrode and the source electrode to form ohmic contact. By arranging the three-side groove structure, the area of the channel is increased, and conduction resistance is reduced.

The invention discloses an LTO film thickness uniformity optimization method through an APCVD method, and particularly relates to the technical field of semiconductor manufacturing, and the method comprises the following steps: S1, prefabricating a silicon wafer; s2, selecting a tungsten filament ring; s3, installing a tungsten filament ring; s4, depositing an LTO thin film; s5, measuring the thickness of the LTO thin film of the silicon wafer; and S6, confirming the service life of the tungsten filament ring. According to the LTO film thickness uniformity optimization method through the APCVD method, the silicon wafer is chamfered, stress concentration and dislocation are reduced, wafer edge breakage and inward movement of thermal stress defects are effectively prevented, a more stable substrate is provided for follow-up film deposition, a tungsten filament ring of a specific specification is selected and correctly installed, and the uniformity of the thickness of the LTO film is improved. The diffusion and transmission conditions of gas in the APCVD process can be improved, the problems of stacking faults, crystal points, self-doping and the like after epitaxy caused by non-uniform films are reduced, and the consistency and reliability of device performance are improved.

The invention provides an epitaxial process concentration monitoring method, which comprises the following steps of: providing a substrate, and forming an N-type epitaxial layer on the substrate; a deep groove is formed in the epitaxial layer, P columns are formed in the deep groove through epitaxy, and one P-type column and one corresponding adjacent N-type column form a super junction unit; selecting at least one test area on the P column to carry out P-type ion heavy doping injection so as to form a P-type heavy doping area; and forming a metal silicide layer of which the resistance value is not higher than a preset value on the P-type heavily doped region, and performing an electrical test by using the metal silicide layer to obtain a resistance test value of the P column, the resistance test value being used for representing the quantity of charges filled in the deep trench epitaxy so as to monitor the PN charge matching state of the super junction. According to the method, the metal silicide process which is simple in process and short in period is adopted, and the purpose of monitoring the epitaxial process concentration can be achieved quickly.

The invention relates to a method for controlling BMD of a heavily boron-doped substrate and a lightly boron-doped epitaxial wafer through RTP, which belongs to the technical field of silicon wafer processing, and comprises the following operation steps of: 1, drawing a single crystal by adopting a Czochralski method, and doping Bo metal during crystal drawing; and 2, slicing, grinding and thinning, polishing, cleaning and epitaxy processes are carried out. Step 3, dividing the silicon wafers after completion into three groups A, B and C for annealing treatment; and meanwhile, a group of reference silicon wafers without RTP annealing treatment are manufactured. And 4, carrying out low-temperature heat treatment, wherein the low-temperature treatment is used for promoting nucleation of oxygen precipitation. And 5, performing high-temperature heat treatment which is used for promoting the growth of an oxygen precipitation nucleation center in the silicon wafer body so as to form high-density oxygen precipitation and induced defects thereof in the silicon wafer body. The method improves the yield of silicon wafers, greatly shortens the time consumed in the annealing process in the manufacturing of an integrated circuit, meets the actual requirement for low temperature in the manufacturing process of the integrated circuit, reduces the technological process, and saves the cost.

The invention discloses a semiconductor laser and a preparation method thereof, which can be used in the field of semiconductor device preparation, and the method comprises the steps: firstly, providing a first conductive type substrate; then, epitaxially growing a buffer layer of a first conduction type, a lower optical waveguide limiting layer, a quantum well active light-emitting layer, an upper optical waveguide limiting layer, a corrosion barrier layer, a current injection layer and an intrinsic ohmic contact layer on the substrate in sequence to obtain a multi-layer epitaxial layer; then, etching the multi-layer epitaxial layer to the corrosion barrier layer based on a preset pattern to form a ridge-shaped table which starts from the intrinsic ohmic contact layer and is deeply cut off to the corrosion barrier layer; and finally, performing particle doping in a region corresponding to the ridge-shaped table, and converting one sides, close to the corrosion barrier layer, of the intrinsic ohmic contact layer, the current injection layer, the corrosion barrier layer and the upper optical waveguide limiting layer into a second conduction type. Therefore, current limitation can be realized without performing multiple epitaxy like a traditional buried heterojunction, and the production cost and the process difficulty are greatly reduced.

The invention provides a buried heterojunction structure, a preparation method thereof and a laser. The preparation method comprises the following steps: primary epitaxy: growing an N-type InP buffer layer, a multi-layer quantum well structure and a P-type InP protective layer on an N-type InP substrate by using an MOCVD (Metal Organic Chemical Vapor Deposition) technology; growing an etching stop layer on the P-type InP protection layer, wherein the etching stop layer is made of an III-V group material; depositing an insulating medium as a mask on the etching stop layer, and etching the etching stop layer and the basic structure layer in a dry or wet etching mode to form a mesa structure; removing the mask on the mesa structure by wet etching; secondary epitaxy: growing a current limiting layer on the mesa structure by adopting an MOCVD (Metal Organic Chemical Vapor Deposition) technology, wherein the current limiting layer covers the whole mesa structure; and forming a funnel-shaped opening on the current limiting layer by wet etching to expose the etching stop layer. According to the invention, the difficulty of growing the current limiting layer by using the MOCVD technology is greatly reduced; the problem of current leakage is effectively suppressed; the current injection efficiency is improved; and the method has good process repeatability and controllability.

Methods and systems for direct-write liquid phase epitaxy of ionic materials are provided for herein, and relate to the manufacture of metal halide optics among other applications. Deposition of the ionic material is induced by mixing at least two fluids of differing composition, wherein the solubility limit of the ionic material in the mixed solution is lower than predicted from a linear combination of the original fluids. This deposition process is spatially controlled using a printhead, enabling localized material deposition and the ability to create arbitrary geometries in turn. In some cases, at least one of the fluids is saturated with the ionic material and surrounds the substrate upon which deposition occurs.

The present application relates to a kind of methods and applications of growing bismuth-doped rare-earth iron garnet BRIG crystal by guided mode pulling-top seed crystal method.For solving the problems of large internal stress, many defects, difficult to prepare thick film of single crystal in the current liquid phase epitaxy method of growing BRIG crystal;And the problems of long growth cycle, difficult to obtain seed crystal in top seed crystal method, the present application combines the fast growth of guided mode pulling crystal and the high-quality single crystal growth of top seed crystal method, and invents guided mode pulling-top seed crystal method to realize the fast growth of high-quality BRIG single crystal.First, the large-size doped rare-earth iron garnet crystal with high lattice matching and similar composition is quickly grown by guided mode pulling method, which is cut into centimeter-level seed crystal, and high-quality BRIG bulk single crystal is quickly grown by TSSG method.The crystal grown by this method has the advantages of small internal stress, less cracking, good uniformity, fast crystal growth, etc., and has obvious advantages in high-performance magneto-optical isolator.

The invention provides a DTI structure based on SiNx / SiO2 Liner. The DTI structure comprises a silicon substrate arranged at the bottom, a buried layer arranged on the surface of the top of the silicon substrate, an epitaxy formed by growing on the silicon substrate, and a buried layer reverse extension arranged between the buried layer and the epitaxy, the DTI deep groove sequentially penetrates through the epitaxy, the buried layer reverse extension and the buried layer and extends into the silicon substrate, the ISSG SiO2 bottom layer of the Line, the SiNx top layer of the Line and the HARP SiO2 layer are sequentially arranged in the DTI deep groove in a covering mode, and the DTI deep groove is filled with a polycrystalline silicon layer. The invention further provides a preparation method of the DTI structure based on the SiNx / SiO2 Liner, Liner oxide is replaced by two layers of NO LINs of the SiNx top layer and the ISSG SiO2 bottom layer, the additional high-temperature annealing step is reduced, the breakdown voltage of the DTI is improved, isolation electric leakage is reduced, and stress accumulation can be reduced; and meanwhile, the process of filling the HARP SiO2 layer twice and annealing twice is adopted, so that the possibility of stripping caused by overlarge stress of the HARP SiO2 layer is avoided.

The embodiment of the invention provides a device and method for inhibiting white spots on the back of a wafer in the epitaxy process, the device for inhibiting the white spots on the back of the wafer in the epitaxy process is optimized, the device comprises a graphite disc, a cyclone tray, a supporting piece and a gas supply device, the top of the graphite disc is used for placing a substrate, the graphite disc is provided with a through type air hole, and the cyclone tray is arranged in the through type air hole; the cyclone tray is arranged at the bottom of the graphite plate; the supporting piece is used for supporting the graphite disc, so that an airflow space is formed between the graphite disc and the cyclone tray, and the airflow space is communicated with the air hole; the cyclone tray can drive the graphite disc to rotate through the supporting piece; the gas supply device is used for generating gas flow into the gas flow space, so that the pressure intensity of the lower surface of the substrate is smaller than that of the upper surface, the Bernoulli effect is generated, the substrate is fully attached to the graphite disc, and therefore the probability that epitaxial growth gas makes contact with the lower surface of the substrate is reduced; the problem of back white mist abnormity caused by the fact that epitaxial gas enters the carbon surface of the substrate to participate in the reaction is solved, and the yield of the epitaxial wafer is further improved.

According to the diamond power device, the preparation method thereof and the electronic device provided by the embodiment of the invention, the field effect transistors are arranged on the two sides of one diamond single crystal epitaxy, so that the field effect transistors with double-sided structures are formed, and the cost is effectively reduced; moreover, the first source electrode and the second source electrode of the double-sided field effect transistor are electrically connected, and the first drain electrode and the second drain electrode of the double-sided field effect transistor are electrically connected, so that compared with a single-sided field effect transistor, the device disclosed by the invention can increase the current density under the condition of keeping the same high withstand voltage level; and the diamond power device with high current density and high voltage resistance is obtained at the same time.

A method for making a two-dimensional heterostructure where one or more van der Waals template precursors may be deposited on a substrate such that a van der Waals template grows on the substrate, and one or more crystal layer precursors may be deposited on a surface of the van der Waals template such that a crystal layer grows on the van der Waals template, wherein the crystal layer is an epitaxial crystal layer. Also provided is an epitaxially-grown two-dimensional heterostructure with at least two components, wherein a plurality of the components engage in dative bonding.

A wafer suitable for epitaxial growth of gallium nitride (GaN) in a Metal Oxide Chemical Vapor Deposition (MOCVD) process. The wafer includes a silicon substrate having a front side and a back side and an edge extending between the front side and the back side, the edge including a front bevel surface connected to the front side and a back bevel surface connected to the back side, wherein the silicon substrate comprises an oxygen denuded silicon layer surrounding a core. The wafer further includes a protection layer being a thermally grown silicon oxide (SiO2) layer substantially covering the front bevel surface and the back bevel surface of the edge, while leaving at least a central region of the front side of the silicon substrate exposed, for preventing meltback during the MOCVD process.

The invention discloses a method for improving the light emitting performance of an AlGaInP red light Micro LED. The method comprises the following steps: S1, preparing an epitaxial structure: processing a substrate and a buffer layer, growing an etching barrier layer and an ohmic contact layer, and stacking and extending a functional layer; s2, patterning the silicon-based substrate; s3, carrying out epitaxial wafer pretreatment and Mesa etching; s4, side wall repairing and wet oxidation treatment; s5, performing secondary epitaxy and side wall passivation; s6, preparing a metal reflecting layer and a protective layer; s7, bonding and removing the substrate; s8, optimizing an n-side electrode and performance; according to the invention, the defects of low luminous efficiency and poor stability caused by side wall non-radiative recombination aggravation, carrier transverse leakage and easy side wall corrosion of the existing AlGaInP red light Micro LED in a small-size and high-PPI scene are overcome, and the synchronous improvement of the luminous performance and the working stability is realized through the preparation method of'epitaxial layer wet oxide layer design + multi-process collaborative optimization '.

The invention relates to a method for obtaining a layer at least partially made of a nitride (N), first comprising the provision of a stack comprising at least one assembly of pads (1000A1-1000B4) extending from a substrate (100). Each pad comprises at least one creep section (220A1-220A5) and one crystalline section (300A1,300A5) surmounting the creep section (200A1-200A5). Then, a crystallite (510A1-510A5) is epitaxially grown on at least some of said pads until coalescence of the crystallites, so as to form a nitride layer (550A). The pads of the assembly are distributed over the substrate, such that the relative arrangement of the pads of the assembly is such that during the epitaxy of the crystallites, the progressive coalescence of the crystallites is always done between, on the one hand, a crystallite or a plurality of coalesced crystallites and, on the other hand, an isolated crystallite.

The invention relates to the technical field of semiconductors, in particular to an epitaxial structure and a preparation method thereof.The epitaxial structure comprises a substrate, a combined buffer layer comprising at least one buffer unit and a drift layer which are sequentially stacked from bottom to top; wherein each buffer unit comprises a nitrogen-doped buffer unit and a phosphorus-doped buffer unit. According to the epitaxial structure provided by the invention, by performing nitrogen and phosphorus doping on the surface of the substrate to form epitaxy of the composite structure buffer layer, the induction probability of stacking fault in the initial epitaxy stage can be reduced, and meanwhile, a large amount of atomic phosphorus is doped in the epitaxy process, and the lattice constant can be expanded, so that the problem that the nitrogen-doped lattice constant is reduced in the mass production process is solved, and the yield of the product is improved. Therefore, the wafer warping is improved, and the yield is improved.

The invention provides a single-mode 660nm semiconductor laser device with a superlattice structure and a preparation method of the single-mode 660nm semiconductor laser device, and belongs to the technical field of photoelectrons. The multi-quantum-well multi-quantum-well light-emitting diode sequentially comprises a GaAs substrate, a buffer layer, a sectional lower limiting layer, a lower waveguide layer, a multi-quantum-well active region, an AlInP / GaP superlattice, an upper waveguide layer, a sectional upper limiting layer, a band gap transition layer and a GaAs cap layer from bottom to top. The preparation method comprises the processes of substrate processing, buffer layer growth, V-group source switching, limiting layer and waveguide layer epitaxy, multi-quantum well and superlattice structure growth, cap layer deposition and the like. Through the segmented design of the superlattice structure and the limiting layer, the hole injection efficiency and the carrier limiting capability are improved, and the high-temperature working characteristic of the device is effectively improved. Stable output of single-mode laser in the 660nm wave band is achieved, reliable power output of 120mW can be kept in a high-temperature environment of 60 DEG C, and meanwhile, low loss, high conversion efficiency and excellent photoelectric performance are achieved.

The invention discloses a beta-phase gallium oxide epitaxial layer and a preparation method and application thereof. The preparation method comprises the following steps: growing a low-rate gallium oxide buffer layer on a substrate at a rate of 0.5-1 [mu] m / h by using a halide vapor phase epitaxy method, then growing a kappa-phase gallium oxide buffer layer on the low-rate gallium oxide buffer layer, and then converting kappa-phase gallium oxide into beta-phase gallium oxide by raising the temperature of the substrate, and growing a beta-phase gallium oxide epitaxial layer on the kappa-phase gallium oxide buffer layer. According to the preparation method, a halide vapor phase epitaxy method is used, kappa-Ga2O3 grown at a low temperature is used as a buffer layer, and a high-quality beta-phase gallium oxide epitaxial layer is grown on the buffer layer, so that the twin crystal orientation and defect density can be effectively reduced, the crystal quality and uniformity are improved, and a new idea is provided for epitaxial growth of a large-size gallium oxide material.

The invention relates to a preparation method of a transition region of a thick film epitaxial gradient layer. The preparation method comprises the following steps: S100, carrying out surface pretreatment on a heavily doped N-type silicon substrate to reduce interface defects; s200, the pretreated substrate is conveyed to an epitaxial cavity, and a stable lattice interface is formed through gradient temperature rise; s300, in the growth stage of the transition region, epitaxial gas and doping gas are introduced, the flow of the doping gas is dynamically adjusted, the resistivity is monitored in real time, and the resistivity of the transition region is made to be matched with the resistivity of the flat region; s400, switching to a flat region growth stage, keeping constant doping gas flow and adjusting epitaxial parameters until the total thickness reaches the standard; s500, gradient cooling and post-processing are carried out on the substrate after epitaxy is completed, the resistivity is monitored in real time by dynamically adjusting the doping gas flow and controlling the epitaxy time, resistivity matching between a transition region and a flat region is ensured, the overall quality of the epitaxial layer is improved, the transition region length and resistivity change are more stable through accurate control, and the yield of the epitaxial layer is improved. And the performance fluctuation caused by mismatching of the resistivity is reduced.

Example methods, compositions and structures are presented whereby sub-10-nm-thick strain-relieving Si1-xGex layers can be realized by Ge ion implantation, into, and selective oxidation of, Si(111) wafers. The resulting Ge-rich layers are fully strain relaxed via a network of misfit dislocations at the Si / Si1-xGe, interface, which do not propagate through the Si1-xGex film. The dislocation network has been found to coincide with a periodic variation in the composition at the Si / Si1-xGex interface and is believed to result from the defect-medicated diffusion of Si atoms from the Si substrate through the Si1-xGex layer to the above SiO2 layer. The epitaxial growth of GaAs on such ultra-thin substrates is demonstrated, presenting a promising approach for solving the long-standing challenge of local, monolithic integration of III-V optoelectronics on the Si platform.

The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor epitaxial structure forming method and a semiconductor device.The semiconductor epitaxial structure forming method comprises the following steps that photoetching and etching are conducted on the back face of a substrate, and photoetching marks are formed; extending a first-layer first-type doped epitaxial layer on the front surface of the substrate, and spin-coating photoresist on the surface of the first-layer first-type doped epitaxial layer; or growing an oxide layer on the front surface of the substrate as a hard mask, and then spin-coating photoresist on the surface of the oxide layer; the exposure mark on the front face of the substrate is aligned with the photoetching mark on the back face of the substrate, exposure of the layer is completed, for a multi-layer epitaxial process scheme, alignment of each epitaxial layer is carried out through the method, the influence of the epitaxial process on the photoetching mark can be avoided, etching of the photoetching mark does not need to be carried out after epitaxy, and a large number of photoetching and etching processes are reduced; meanwhile, if each layer is aligned with the same alignment mark, exposure error accumulation between layers can be avoided.

The application discloses a vertical cavity surface emitting semiconductor laser based on a lateral epitaxial technology and a preparation method. The core of the structure is to solve the problem of presetting a lower DBR through the lateral epitaxial technology, to preset the DBR first, to open a window on the DBR, to grow the functional area of the laser on the upper side of the DBR through the lateral epitaxial technology, to complete the preparation of the lower DBR, and then to prepare the upper DBR and the metal electrodes on the two sides through common processes, so that the vertical cavity surface emitting laser is formed. The direction of the electric injection is perpendicular to the direction of the laser emission, and the influence of the current spreading layer of the ultraviolet band VCSEL on the light field absorption can be avoided. The application is favorable for reducing the damage to the device, improving the yield and the device performance, well utilizing the high-quality material area grown through the lateral epitaxial technology, improving the crystal quality, improving the light emitting efficiency and the service life, and the electric field direction is the non-polarized direction of the material, so that the quantum confinement Stark effect can be effectively reduced, and the reduction of the quantum efficiency and the wavelength drift of the device under a large voltage can be inhibited.

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof. The preparation method comprises the following steps: (1) providing a semiconductor structural member, wherein the semiconductor structural member comprises a substrate; the stacked structure is arranged on the surface of the substrate, and the stacked structure comprises a sacrificial layer and a channel layer which are sequentially arranged in a stacked mode in the direction away from the substrate; the false gate is arranged across the laminated structure; the side walls are arranged on the side surfaces of at least part of the false gates; the laminated structure which is not covered on the outer sides of the dummy gate and the side wall is a source-drain region; (2) etching the source and drain regions of the semiconductor structural member, and stopping on the surface of the substrate; (3) forming an inner side wall on the side surface of the sacrificial layer; (4) forming a protective layer on the side surface of the channel layer; (5) carrying out epitaxy on the laminated structure in the source and drain regions to form an epitaxial layer, and removing the protective layer; and (6) fusing the epitaxial layer, and then carrying out solid-phase epitaxy regrowth and crystallization to obtain the semiconductor device.

The application relates to the technical field of liquid phase epitaxy growth, and discloses a liquid phase epitaxy tool and a method for growing a thin film by using the same. The tool comprises a base, a sliding strip, a detachable supporting component, a mother liquid plate and a cover plate. The detachable supporting component comprises a sleeved inner core and an outer ring. The mother liquid plate is provided with a mother liquid groove for containing mother liquid. The base is provided with a first groove matched with the sliding strip, and the upper surface of the base is provided with a second groove. The sliding strip is located in the first groove, and is provided with a through hole penetrating through the thickness. The detachable supporting component is located in the through hole, and the upper surface of the detachable supporting component is used for placing a substrate. The depth of the second groove is not less than the thickness of the substrate, the width of the second groove is matched with the thickness of the outer ring, and the outer ring falls into the second groove when the sliding strip moves to above the second groove, so that the edge of the substrate protrudes from the inner core. The mother liquid plate is located on the upper surface of the base and the sliding strip. The tool can disconnect the thin film from the surrounding when the mother liquid is in a molten state, and the yield of the thin film is improved.

The invention relates to a method for producing a piezoelectric layer (10) on a substrate (11), characterized in that it comprises the following steps:-forming a pseudo-seed layer (102) of a first piezoelectric material on a donor substrate (100) by a first epitaxy; -transferring the seed layer (102) and a portion (103) of the donor substrate (100) onto the acceptor substrate (110) via at least one electrically insulating layer and / or at least one electrically conductive layer (105) adapted to allow relaxation of the seed layer; -removing the transferred portion (103) of the donor substrate (100) in order to expose the surface of the seed layer (102); -forming a single crystal layer (104) of a second piezoelectric material on the seed layer (102).