SiGe (silicon germanium) source and drain area manufacturing method

A manufacturing method and drain region technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of increasing the difficulty of SiGe epitaxy process in grooves, the decrease of device yield, and the decrease of process stability, so as to achieve enhanced Effect of process stability, stress increase, avoidance of stress relaxation
CN104201108AActive Publication Date: 2014-12-10SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
Publication Date
2014-12-10

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Abstract

The invention discloses a SiGe (silicon germanium) source and drain area manufacturing method. A multi-layer structure which comprises alternately stacked buffer layers and main body layers is formed by a method that the SiGe epitaxial growth of the buffer layer and the main body layers is alternated repeatedly and accordingly the thickness of every high Ge concentration of SiGe main body layer is effectively reduced and shared into every layer of main body layer and accordingly the stress relaxation due to the fact that thickness of every main body layer exceeds the critical thickness is avoided; the Ge content of every layer of SiGe main body layer is further improved to enable the stress of the SiGe source leakage on a channel to be increased; an SiGe process window is enlarged due to the repeated epitaxy and accordingly the process stability is enhanced and accordingly the device performance is improved; the stress can be effectively improved without increase of the process difficulty and accordingly the process is stable and controllable and the cost is low.
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Description

technical field

[0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing technology, in particular to a method for manufacturing SiGe source / drain regions. Background technique

[0002] With the development of semiconductor integrated circuits, the size reduction of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has continuously improved the speed, performance, density and functional unit cost of integrated circuits. After entering the 90nm process era, with the substantial reduction in the size of integrated circuit devices, the junction depth of the source / drain (elevated source / drain) is getting shallower and shallower. It is necessary to use selective epitaxy (selective epiSiGe, abbreviated as SEG) to thicken the source. The / drain is used as a sacrificial layer for subsequent silicide reactions, thereby reducing series resistance.

[0003] For the 65 / 45nm technology process, a method to improve the performance of...

Claims

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