SiGe (silicon germanium) source and drain area manufacturing method

A manufacturing method and drain region technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of increasing the difficulty of SiGe epitaxy process in grooves, the decrease of device yield, and the decrease of process stability, so as to achieve enhanced Effect of process stability, stress increase, avoidance of stress relaxation

Active Publication Date: 2014-12-10
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method increases the difficulty of the etching of the groove and the SiGe epitaxial process, reduces the stability of the process, and reduces the yield of the device.

Method used

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  • SiGe (silicon germanium) source and drain area manufacturing method
  • SiGe (silicon germanium) source and drain area manufacturing method
  • SiGe (silicon germanium) source and drain area manufacturing method

Examples

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no. 1 example

[0035] see Figure 4 , the manufacturing method of the SiGe source / drain region of the present embodiment comprises the following steps:

[0036] Step S01, providing an N-type wafer silicon substrate formed with gates, and etching grooves for forming source / drain regions on the silicon substrate;

[0037] Step S02, epitaxially growing a SiGe buffer layer in the groove;

[0038] Step S03, epitaxially growing a SiGe main body layer on the buffer layer, the concentration of Ge in the main body layer is higher than that of the buffer layer;

[0039] Step S04, repeating steps S02 to S03 once, that is, growing a buffer layer and a main layer on the main layer grown in step S03 to form a multi-layer structure with alternately stacked buffer layers and main layers;

[0040] Step S05 , epitaxially growing a Si capping layer on the multilayer structure formed in step S04 to form a PMOS source / drain region with SiGe.

[0041]This embodiment adopts the method of alternating SiGe epitax...

no. 2 example

[0043] see Figure 5a to Figure 5h , the manufacturing method of the SiGe source / drain region of the present embodiment comprises the following steps:

[0044] Step S01, such as Figure 5a As shown, an N-type wafer silicon substrate 301 formed with a gate 304 is provided. The gate 304 is protected by a sacrificial layer, and the silicon substrate 301 between the gate 304 and the shallow trench isolation STI302 is etched to be Form the groove 303 of source / drain region; Wherein, the depth of groove 303 is

[0045] Step S02, such as Figure 5b As shown, a low-temperature epitaxy method is used to deposit a first buffer layer (SiGe film) 305 in the groove 303; wherein, the first buffer layer contains a Ge concentration of 20% and a thickness of

[0046] Step S03, such as Figure 5c As shown, the low temperature epitaxy method is used to deposit the first bulk layer (SiGe thin film) 306 on the first buffer layer 305; wherein, the first bulk layer contains Ge concentration ...

no. 3 example

[0063] The method for manufacturing the SiGe source / drain region of this embodiment includes the following steps:

[0064] Step S01, providing an N-type wafer silicon substrate formed with a gate, the gate is protected by a sacrificial layer, and etching a source / drain region to be formed on the silicon substrate between the gate and the shallow trench isolation STI groove; where the depth of the groove is

[0065] Step S02, using a low-temperature epitaxy method to deposit a first buffer layer in the groove; wherein, the first buffer layer contains a Ge concentration of 15% and a thickness of The epitaxy temperature is 720°C;

[0066] Step S03, using a low-temperature epitaxy method to deposit a first body layer on the first buffer layer; wherein, the first body layer contains a Ge concentration of 35% and a thickness of B doping concentration 1e 19 cm -3 , the epitaxy temperature is 640°C;

[0067] Step S04, using a low-temperature epitaxy method to deposit a seco...

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Abstract

The invention discloses a SiGe (silicon germanium) source and drain area manufacturing method. A multi-layer structure which comprises alternately stacked buffer layers and main body layers is formed by a method that the SiGe epitaxial growth of the buffer layer and the main body layers is alternated repeatedly and accordingly the thickness of every high Ge concentration of SiGe main body layer is effectively reduced and shared into every layer of main body layer and accordingly the stress relaxation due to the fact that thickness of every main body layer exceeds the critical thickness is avoided; the Ge content of every layer of SiGe main body layer is further improved to enable the stress of the SiGe source leakage on a channel to be increased; an SiGe process window is enlarged due to the repeated epitaxy and accordingly the process stability is enhanced and accordingly the device performance is improved; the stress can be effectively improved without increase of the process difficulty and accordingly the process is stable and controllable and the cost is low.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing technology, in particular to a method for manufacturing SiGe source / drain regions. Background technique [0002] With the development of semiconductor integrated circuits, the size reduction of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has continuously improved the speed, performance, density and functional unit cost of integrated circuits. After entering the 90nm process era, with the substantial reduction in the size of integrated circuit devices, the junction depth of the source / drain (elevated source / drain) is getting shallower and shallower. It is necessary to use selective epitaxy (selective epiSiGe, abbreviated as SEG) to thicken the source. The / drain is used as a sacrificial layer for subsequent silicide reactions, thereby reducing series resistance. [0003] For the 65 / 45nm technology process, a method to improve the performance of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/28
CPCH01L29/0847
Inventor 钟旻
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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