255 results about "Process window" patented technology

The invention provides a process parameter optimization method and system, an in-situ online detection device, computer equipment and a storage medium. The process parameter optimization method comprises the following steps: acquiring process parameters and measurement data in a preset window; based on the measurement data, extracting characteristic parameters representing a wafer surface growth physical state; inputting the characteristic parameters and the process parameters into a pre-trained prediction model to obtain prediction results representing the growth state trend and the photoelectric characteristic change trend; and optimizing process parameters based on the prediction result, wherein the optimized process parameters are used for the epitaxial growth process of the wafer in the next preset window. By the adoption of the scheme, the feature parameters representing the growth physical state are extracted from the original measurement data, based on the feature parameters, the method does not need to depend on a prior model and parameters, the high-dimensional relation among the multiple parameters is automatically analyzed, the globally optimal process window is found, the generated prediction result is consistent with the actual growth mechanism, and the prediction efficiency is improved. And the accuracy of the technological process and the product yield are effectively improved.

The invention provides a semiconductor device and a manufacturing method thereof, and electronic equipment. The manufacturing method comprises the following steps: forming a stack structure on a substrate; forming a plurality of initial isolation structures arranged along the first direction in the stacked structure, wherein the initial isolation structures extend along the second direction; wherein a cavity exists in at least one initial isolation structure; a groove is formed in at least one side of the two opposite sides of the initial isolation structures in the second direction, the groove extends in the first direction, and the multiple initial isolation structures are exposed out of the side wall of the groove; transversely etching the plurality of initial isolation structures based on the grooves until the cavity is exposed; the removed space and the cavity of the initial isolation structure are filled with an isolation material based on the groove, and the remaining initial isolation structure and the isolation material form an isolation structure. According to the isolation structure after the cavity is eliminated, the consistency of the isolation performance between the functional devices located on the two opposite sides of the isolation structure in the first direction can be improved, and the reliability of a process window and a device during semiconductor device preparation is improved.

This application provides a method, system, in-situ online detection device, computer equipment, and storage medium for optimizing process parameters. The method involves acquiring process parameters and measurement data within a preset window; extracting characteristic parameters representing the physical state of wafer surface growth based on the measurement data; inputting the characteristic parameters and process parameters into a pre-trained prediction model to obtain prediction results representing the growth state trend and photoelectric property change trend; optimizing the process parameters based on the prediction results, and using the optimized process parameters for the epitaxial growth process of the wafer in the next preset window. By employing this approach, the application extracts characteristic parameters representing the physical state of growth from the original measurement data. Based on these characteristic parameters, the application automatically analyzes the high-dimensional relationships between multiple parameters and finds the globally optimal process window without relying on prior models and parameters. The generated prediction results are consistent with the actual growth mechanism, effectively improving the accuracy of the process and product yield.

The invention relates to the field of integrated circuit manufacturing, in particular to a light source mask collaborative optimization method and device, and the method comprises the steps: obtaining an initial light source and an initial mask pattern; the initial mask pattern is a binary image; determining the adjusted initial light source and the adjusted initial mask pattern corresponding to the minimum function value of the light source mask collaborative optimization loss function as an optimized light source and an optimized mask pattern; the light source mask collaborative optimization loss function comprises a main pattern edge error item and a sub-resolution auxiliary pattern printing item; obtaining a simulation photoetching image, and judging whether a sub-resolution auxiliary pattern is printed in the simulation photoetching image or not; when the printed sub-resolution auxiliary pattern exists, outputting the latest optimized mask pattern as a process iteration mask pattern; calculating a proportion value; and when the proportion value does not exceed the qualified upper limit value, outputting an optimized light source and process iteration mask pattern. The method can ensure that no sub-resolution auxiliary pattern is printed and a larger process window is reserved.

A virtual fabrication environment for semiconductor device fabrication that includes an analytics module for performing process window optimization is discussed.

The invention discloses an environment monitoring management system and method for a precision workshop, and relates to the technical field of environment monitoring and control, and the method comprises the steps: synchronously collecting multi-dimensional environment parameters through a distributed sensor network, accessing a manufacturing execution system in real time, analyzing the requirements of a process window, and carrying out the real-time monitoring of the environment parameters; and performing fusion and abnormality diagnosis on the data under a unified space-time reference, generating a closed-loop regulation and control instruction, and coordinating and controlling an execution mechanism. The system comprises a multi-mode environment perception unit, a process semantic analysis unit, a space-time fusion and abnormality diagnosis engine, an intelligent regulation and control decision unit and an execution mechanism cooperative control unit. According to the invention, deep understanding of environment disturbance and production process relevance can be realized, compound environment abnormity can be accurately identified, production task requirements can be adapted in real time, environment parameters are ensured to be always in an optimal process tolerance band, the product yield and the process repeatability are obviously improved, and millisecond-level response and cooperative linkage control are realized.

The invention provides a display backboard stamping process optimization method and system, and relates to the technical field of process optimization. According to the method, multi-area differential mesh division is carried out on a plate finite element model, fine meshes are adopted for a high-strain small-curvature area and a high-strain area, rough meshes are adopted for a trimming allowance area, and medium meshes are adopted for other areas. The deformation behavior of the key area is accurately captured, and the reliability of simulation prediction is remarkably improved under the same computing resource. And then, reverse compensation iterative correction and rapid convergence are performed on the initial molded surface based on a springback prediction result to obtain an optimized molded surface model, and source control is directly performed for springback errors, so that the number of times and period of mold testing which traditionally depends on experience are greatly reduced. According to the method, through linkage of simulation and real-time sensing data, dynamic optimization and closed-loop control of the process window are achieved, and the forming quality and production stability of the display backboard are effectively improved.

The invention provides a method for determining an optimal focus. The method comprises the following steps of: providing a wafer which is subjected to photoetching treatment under different focus settings; performing optical critical dimension measurement on the photoresist pattern on the wafer to obtain a plurality of side wall angle values respectively corresponding to different focus settings; based on the plurality of side wall angle values and different focus settings, establishing a relationship between the side wall angles and the focuses; and according to the relationship, determining a focus when the side wall angle is the preset target angle as an optimal focus. According to the method, by directly utilizing the side wall angle parameter strongly related to the focusing quality, the measurement interference of a traditional method is avoided, and the optimal focus of the photoetching process can be determined more accurately and reliably, so that the process window is widened, and the process stability and the product yield are improved.

The invention relates to the related technical field of semiconductors, in particular to a chip processing production line monitoring method and system, and the method comprises the steps: collecting photoetching process monitoring data; setting a feature matrix; determining a focusing window boundary; configuring a focal length offset compensation amount based on the feature matrix in combination with a focusing window boundary and photolithographic process monitoring data; and determining a deviation amplitude score by using an edge placement error model to perform graded reminding. The technical problems that window boundary definition monitored by a chip processing production line depends on experience to set a fixed standard, focal length offset cannot be effectively compensated, and the risk that edge placement errors exceed the standard exists are solved, and coupling analysis of an optical proximity effect and a process window is carried out in a mask layer, a lens layer and a photoresist layer and a feature matrix is constructed, so that the edge placement error is accurately determined. And the compensation parameters and the error trend are dynamically matched, the focal length offset compensation precision is improved, an edge placement error model is used for determining a deviation amplitude score and carrying out graded reminding, and the technical effect of abnormity processing timeliness is enhanced.

The invention provides a thick copper twelve-layer plate lamination white point defect prediction and process window optimization method, which comprises the steps of constructing multi-source process parameter input of time-space alignment, denoising and standardization, performing branch feature extraction through a Transform main branch and a graph neural network embedded with causal logic, performing adaptive weighted integration of features through a gating fusion mechanism, and performing optimization of the lamination white point defect prediction and process window optimization of the thick copper twelve-layer plate lamination white point defect prediction and process window optimization of the thick copper twelve-layer plate lamination white point defect. High-confidence prediction of the occurrence probability and spatial distribution of white spot defects is realized, adaptive calibration and online incremental training of a model are driven by predicting uncertainty, and finally, an optimal temperature-pressure-vacuum degree process parameter combination is generated based on a multi-objective optimization method. According to the invention, the accuracy of white point defect early warning and the adaptive optimization capability of the system process are improved.

The invention belongs to the technical field of battery diaphragms, and relates to a wet-process bidirectional asynchronous and synchronous coexisting diaphragm preparation method, which comprises the following operation steps: material mixing and extrusion, longitudinal stretching, synchronous small-draw-ratio stretching, primary transverse stretching, extraction, secondary transverse stretching, and diaphragm forming and rolling. According to the technology, synchronous stretching and bidirectional asynchronous stretching are combined in the wet process field, transverse stretching of a membrane is divided into two times, synchronous small-draw-ratio stretching operation is set between longitudinal stretching and one-time transverse stretching, transverse and longitudinal simultaneous stretching is completed after longitudinal stretching, the obtained lattice structure is firm, and the consistency of molecular orientation is guaranteed; the diaphragm prepared by the process has the characteristics of high strength, low thickness, high gap uniformity and consistency and the like; the process mode is flexible and changeable, the diversity of wet process adjustment can be increased, more possibilities are provided for new product development, product performance is optimized, and a larger process window is provided for development of ultra-thin and ultra-strong products.

The invention relates to an optical proximity correction method and correction device, a mask, equipment and a storage medium. The method comprises the following steps: determining a correction limited graph from original correction graphs; wherein the correction limited pattern is a pattern which triggers edge placement error limitation, and the original correction pattern is a pattern obtained after first optical proximity correction is carried out on the photoetching design pattern; determining a to-be-corrected graph in the photoetching design graph based on the position of the correction limited graph in the original correction graph; performing second optical proximity correction on the to-be-corrected graph to obtain a target corrected graph; and processing the original correction graph based on the target correction graph to obtain a mask graph. According to the mask pattern, the influence of edge placement error limitation on the correction process can be eliminated, the correction precision of the photoetching design pattern after optical proximity correction is improved, the abnormities of narrowing, retraction and the like of the photoetching pattern are improved, the process window is improved, and the process risk is reduced.

The invention provides a method for measuring impedance of a capacitively coupled plasma source, which comprises the following steps of: under the condition that plasma is not ignited, dividing a cavity into an upper part and a lower part along an electrical middle plane, and establishing an equivalent circuit model comprising five elements to be determined; three measurement ports are defined, five independent measurement boundary conditions are set, sweep frequency measurement is carried out by using a network analyzer, and multiple groups of Z parameter data are obtained; then, on each frequency point, joint fitting is carried out on a theoretical impedance expression of the equivalent circuit and actually measured data, and parameter values of all undetermined elements are solved; and finally, outputting a parameter curve of each element along with frequency change and a cavity equivalent impedance spectrum. According to the method, the problem that equivalent parameters cannot be identified is solved through multi-working-condition data redundancy, universal, accurate and reproducible measurement of the impedance of the pure cavity is realized, and a reliable quantitative basis is provided for matching network design, process window prediction and cavity optimization.

The invention discloses an SRAF placement method based on a Bayesian model. The method comprises the steps that historical SRAF configuration parameters and photoetching simulation data are collected and preprocessed; based on the preprocessed data, using kernel density estimation to construct prior probability distribution; constructing a likelihood function of multiple photoetching result indexes in combination with a Hopins photoetching model; calculating approximate distribution of a posterior probability through variation inference by using the Bayesian theorem; and finally selecting an optimal SRAF configuration parameter according to the posterior distribution, and verifying the manufacturing feasibility of the process window and the mask. According to the method, historical prior knowledge and real-time photoetching data are organically integrated through the Bayesian model, and high-precision, high-efficiency and high-robustness optimization of the SRAF layout is realized by combining specific technical characteristics such as preprocessing, kernel density estimation, a Hopkinson physical model and variation approximation; the problems of complex rule base, time-consuming calculation and insufficient adaptability in the prior art are effectively solved.

The invention provides a mask pattern optimization method, a medium, a product and equipment. The method comprises the following steps: acquiring a mask pattern to be corrected and a corresponding ideal photoetching pattern; calling an artificial intelligence model in the inversion photoetching tool to generate a photoetching simulation result according to the mask pattern to be corrected; calculating a cost value according to the photoetching simulation result and the ideal photoetching graph; correcting the mask pattern to be corrected based on the cost value by using an inversion photoetching algorithm to obtain a corrected mask pattern; and taking the corrected mask pattern as a to-be-corrected mask pattern, and repeatedly executing the step of calling the artificial intelligence model in the inversion photoetching tool to generate a photoetching simulation result according to the to-be-corrected mask pattern until a preset cycle ending condition is met, thereby obtaining an optimized mask pattern. Through the method, the inversion photoetching tool can be highly matched with an OPC tool of a corresponding manufacturer, so that a process window of a dead pixel area is effectively improved, and a solid foundation is laid for improvement of the overall yield of technical nodes.

The application relates to the field of photoetching technology, and particularly relates to a method and device for rapidly screening overlay mark manufacturability and computer equipment, which comprises the following steps: inputting preset range of process window conditions, selecting upper limit value and lower limit value as extreme process window conditions; calculating initial process variation bandwidth value based on the extreme process window conditions, and performing first screening on the initial process variation bandwidth value based on a preset screening ratio; calculating to-be-processed process window values corresponding to the screened process variation bandwidth values; performing second screening on the to-be-processed process window values based on a preset standard range to obtain final process window values; and screening the overlay marks corresponding to the final process window values. The application further provides a device and computer equipment. The problems of time and labor consumption in screening overlay mark manufacturability are solved.

A method of correcting image data of an image sensor provided herein includes collecting a process window from the image sensor; obtaining weight factors of the process window in various directions based on readout values of the second photodiodes in the process window; obtaining interpolated values of the second photodiodes at positions of the first photodiodes in the first pixel groups in the process window by using the weight factors; and estimating a corrected value Btarget of a target first photodiode by an equation I: Btarget=Gint×(Bmean / Gmean), wherein Gint is the interpolated value of the second photodiodes at a position of the target first photodiode, Bmean is a mean of readout values of first photodiodes in a corresponding first pixel group including the target first photodiode and Gmean is a mean of the interpolated values of the second photodiodes at positions of the first photodiodes in the corresponding first pixel group.

The invention discloses a manufacturing method of a cold-rolled sheet. The cold-rolled sheet comprises the following chemical components in percentage by mass: 0.105%-0.125% of C, 0.20%-0.30% of Si, 2.30%-2.55% of Mn, less than or equal to 0.020% of P, less than or equal to 0.010% of S, 0.020%-0.050% of Alt, 0.50%-0.60% of Cr, 0.10%-0.20% of Mo, 0.020%-0.030% of Nb, 0.015%-0.025% of Ti, 0.0008%-0.0020% of Ca, less than or equal to 0.0070% of N and the balance of Fe. And the balance Fe and impurities. The invention further discloses key process control parameters. According to the method, the excellent effect is achieved through fine metallurgical design and process control of the whole process, especially innovative chemical component design and process window optimization of key procedures.

The application provides a method for increasing the process window of an ILD filling of a flash memory device, which comprises the following steps: providing a semiconductor structure, which comprises a semiconductor substrate, a gate dielectric layer, a word line polysilicon, a floating gate and a control gate; forming an oxide layer on the surface of the semiconductor structure, and forming a nitride layer on the surface of the oxide layer; etching the nitride layer and the oxide layer by an etching process to form a first side wall on the outside of the floating gate, the control gate, the intermediate dielectric layer and the word line side wall; cleaning the semiconductor structure with the first side wall by a first wet cleaning process; ion implanting the semiconductor substrate to form a source region and a drain region on both sides of the first side wall; and cleaning the semiconductor structure with the source region and the drain region by a second wet cleaning process. The application solves the problem of the existing flash memory device in the ILD filling process.

The invention discloses an exposure dose determination method, device and equipment and a storage medium, which are applied to the technical field of photoetching, and the method comprises the following steps: obtaining a target critical size and a line width drift tolerance limit between an exposure pattern formed after photoresist exposure and an etched functional layer pattern; obtaining an exposure dose slope; the exposure dose slope is a slope value determined based on the critical dimensions of the corresponding exposure patterns under different exposure doses; determining an exposure dose step length according to the line width drift tolerance limit and the exposure dose slope; and determining a target exposure dose corresponding to the target key size according to the exposure dose step length. The exposure dose step length is calculated based on the line width drift tolerance limit between the exposure pattern formed after exposure and the functional layer pattern formed after etching, so that the target exposure dose can ensure that the line width drift between the exposure pattern formed after exposure and the functional layer pattern formed after etching meets the requirement; therefore, the process window loss can be reduced.

The application discloses a process window determination method, a semiconductor processing method and equipment, and relates to the technical field of semiconductor manufacturing. In view of the problems of time loss and poor exhaust mode compatibility caused by the fact that the prior art relies on pressure gauge reading stability to determine the process window, the application determines the process window start time by recording the switching period of the measured pressure between two stable pressures and combining the flow switching instruction time; further, the pre-calibration stage and the process stage are distinguished, the switching period is obtained in the pre-calibration stage, and a database is established, and in the process stage, the parameters are directly reused for open-loop operation, and multiple exhaust modes such as fixed opening of the vacuum valve and feedback regulation are compatible. The application can start the process without waiting for the pressure gauge reading to be completely stable, effectively increases the process window time, significantly improves the equipment productivity and process adaptability, and is suitable for rapid pressure switching cyclic semiconductor processes such as atomic layer etching and atomic layer deposition.

The invention discloses a short-process preparation method of an ultra-high-speed laser cladding coating on the surface of a shaft part and the obtained coating, and the method comprises the following steps: firstly, based on energy conservation and momentum balance, calculating and determining a stable process window of ultra-high-speed laser cladding; based on a geometrical optical model, the horizontal offset distance of the laser head relative to the central axis of the workpiece is calculated and controlled. Based on molten pool stress analysis under a rotating coordinate system, the relation between the rotating direction of a workpiece for restraining flowing of a molten pool and the offset direction of a laser head relative to the central axis of the workpiece is determined, under the determined conditions, ultra-high-speed laser cladding is conducted on the outer circle surface of the shaft part, and single-pass precision grinding is directly conducted after cladding. According to the method, the thin-layer coating with the smooth surface and the uniform thickness is obtained through physical stability control, the machining route of cladding-turning-grinding is simplified into cladding-single-pass precision grinding, and the machining allowance and the production cost are remarkably reduced.

The invention discloses a photoetching mask process window analysis method and system, and belongs to the technical field of photoetching processes, and the method comprises the following steps: collecting exposure process parameters, photoetching pattern parameters, window evaluation parameters and auxiliary parameters to construct an exposure analysis vector; selecting historical exposure analysis vectors to form a historical vector set, and constructing a sensitivity matrix; a real-time feature vector is constructed through online detection, and the current process state is judged in combination with a sensitivity matrix so as to identify window abnormity; once the window is identified to be abnormal, through multi-exposure condition simulation, constructing an index simulation value corresponding to a process window index for each group of exposure parameters, and screening an optimal exposure regulation and control group; converting the optimal exposure regulation and control group into an exposure execution instruction, and issuing the exposure execution instruction to execute exposure operation; and after the exposure operation is completed, deviation comparison verification is carried out, and a case sample is constructed to iteratively update the sensitivity matrix, so that the process suitability and the prediction precision are improved, and the automatic production requirement of a photoetching mask preparation production line is effectively met.

The invention provides a processing method of a metal layer layout, and belongs to the technical field of semiconductor manufacturing, and the method comprises the steps: obtaining the metal layer layout and a through hole layer layout corresponding to the metal layer layout; extracting a first process hot spot pattern in the metal layer layout and a background pattern within a preset range around the first process hot spot pattern according to a first preset rule; carrying out edge shrinkage processing on a convex angle edge on the convex angle pattern at a first preset displacement to obtain a pre-processing layout; performing optical proximity effect correction processing on the preprocessed layout to obtain a corrected layout of the metal layer layout; and performing simulation processing on the corrected layout according to a second preset rule to obtain a simulation image. According to the optical proximity correction method, the process hot spot of the convex angle pattern during exposure can be eliminated under a small-size process window, and the defect that the OPC technology is difficult to fully correct the small-feature-size pattern is overcome.

The invention discloses a TOPCon-0BB assembly multi-stage welding method based on a low-temperature welding strip, relates to the technical field of photovoltaic assembly manufacturing, and effectively prevents a packaging adhesive film from permeating into a contact interface in the main welding process through partition scanning preheating and generation of a controllable adhesive film pre-wetting state. A clean initial condition is created for forming high-quality metallurgical bonding; in combination with closed-loop monitoring and regulation of the growth state of the IMC layer, it is ensured that a welding spot has enough mechanical strength, meanwhile, the brittleness problem caused by the too thick IMC layer is avoided, and therefore a welding interface has excellent conductivity and toughness, multiple physical fields are innovatively introduced to intervene and optimize the welding process, and the welding quality is improved. The structural stability and the anti-fatigue performance of the assembly are greatly enhanced; according to the method, the self-adaptive calibration parameters for different packaging material systems are dynamically generated by acquiring and identifying the welding process route identifier of the assembly, so that the process window is greatly widened, and the compatibility of different materials is enhanced.

The invention relates to the technical field of coating processes, and discloses a method for optimizing a middle coating process of a tab slot. The method comprises the following steps: respectively formulating a corresponding single-factor control test group based on a control group of each test slurry; for each piece of test slurry, respectively adopting the corresponding single factor to control the coating process parameter combination of the test group, and carrying out a tab slot middle coating process test; key parameters influencing the cleanliness of the slot and key parameters influencing the edge thickness consistency of the slot are screened out according to the test data; according to the method, the key parameters influencing the cleanliness of the slot position and the consistency of the edge thickness of the slot position are respectively screened out through a single-factor control test, so that a scientific fact basis is provided for process optimization, the optimal process window is conveniently and quickly determined, and engineering application and development of middle coating of the tab are promoted.

There is provided a system and method of process window qualification. The method includes obtaining a wafer comprising a plurality of dies respectively printed under a plurality of process window conditions characterized by varying values of focus and exposure, wherein the wafer is fabricated in accordance with a chip design containing a pattern of interest (POI) comprising a surface structure and an underneath structure; inspecting the wafer at POI locations to obtain a plurality of images each capturing an occurrence of the POI; and providing a group of measurements from the plurality of images, comprising, for each given image: extracting a surface contour of the surface structure and an underneath contour of the underneath structure; shifting one of the contours relative to the other one or more times to simulate one or more overlay variations; and measuring a critical metric between the contours following each shift.

The application relates to a metal line and via layout optical proximity effect correction method and related equipment, which comprises the following steps: obtaining an original metal line and via layout, wherein the direction perpendicular to the extension direction of the interconnection metal line in the plane of the interconnection metal line layer is the width direction, the metal line adjacent to the interconnection metal line in the width direction in the metal line layer is an influence metal line, the influence metal line comprises an influence metal line segment, and the influence metal line segment is a projection area line segment of a connecting via on the influence metal line in the width direction; performing hole expansion processing on each connecting via in the width direction to form an expanded connecting via; translating each influence metal line segment in the width direction in a direction away from the interconnection metal line by a certain distance to form a pretreated metal line and via layout; performing optical proximity correction on the pretreated metal line and via layout to obtain a corrected metal line and via layout, so that the photolithography process window can be increased, and the metal line is not prone to defects such as bridging.

The invention provides a graph splitting method for cracking odd-numbered rings of a metal cutting layer. The graph splitting method comprises the following steps: step 1, generating default splitting identifiers about a current graph and an adjacent graph based on a default splitting rule; 2, screening out graphs forming an odd number ring from the graphs for calibrating the default splitting identifiers, adjusting the splitting rules of the graphs forming the odd number ring, and calibrating specific splitting identifiers among the graphs violating the line end rule and the angle-to-angle rule; and step 3, dividing the adjacent graph with the specific splitting identifier or the default splitting identifier calibrated between the current graph and the adjacent graph into a first metal cutting mask, and dividing the rest adjacent graphs and the current graph into a second metal cutting mask. On the premise that the process difficulty and cost are not increased, uncontrollability, caused by rule conflicts, of the splitting structure is broken, various splitting results possibly existing in the splitting process are avoided, then the purpose of optimizing a metal cutting layer process window is achieved, and the risk of short circuit or open circuit of a metal wire is effectively reduced.

The present disclosure provides a method that includes receiving a circuit layout that includes circuit features and a mark pattern to be formed on a same material layer over an integrated circuit (IC) substrate, the circuit features being longitudinally oriented along a first direction and being distanced from each other along a second direction that is orthogonal to the first direction; fragmenting the mark pattern to generate a fragmented mark pattern having fragmented mark features such that the fragmented mark features are configured in parallel and are longitudinally oriented along a third direction; and generating a modified circuit layout for circuit fabrication, the modified circuit layout including the circuit features and the fragmented mark pattern.