318 results about "Process window" patented technology

The invention relates to the technical field of machining control, and discloses a forging part machining process control method and system based on digital twinning. The method comprises the following steps: acquiring temperature field and stress field data streams of large oil press equipment and forgings at multiple points in different areas; performing organization-defect association mode recognition on the data stream to generate a forging process database; a constitutive unit nesting method is adopted to construct a digital twinborn model, and a microstructure evolution unit is embedded in a macroscopic unit; performing nonlinear progressive simulation to obtain a critical deformation condition and a defect threshold value; and carrying out reverse solution on the process window to obtain an optimal process parameter combination. According to the method, the forging digital twin model is established through the constitutive unit nesting method, bidirectional coupling of macroscopic deformation and microstructure evolution is achieved, a stable process parameter combination is determined through the process window reverse solution technology, and therefore the quality stability and production efficiency of forged parts are improved.

The invention provides a process parameter optimization method and system, an in-situ online detection device, computer equipment and a storage medium. The process parameter optimization method comprises the following steps: acquiring process parameters and measurement data in a preset window; based on the measurement data, extracting characteristic parameters representing a wafer surface growth physical state; inputting the characteristic parameters and the process parameters into a pre-trained prediction model to obtain prediction results representing the growth state trend and the photoelectric characteristic change trend; and optimizing process parameters based on the prediction result, wherein the optimized process parameters are used for the epitaxial growth process of the wafer in the next preset window. By the adoption of the scheme, the feature parameters representing the growth physical state are extracted from the original measurement data, based on the feature parameters, the method does not need to depend on a prior model and parameters, the high-dimensional relation among the multiple parameters is automatically analyzed, the globally optimal process window is found, the generated prediction result is consistent with the actual growth mechanism, and the prediction efficiency is improved. And the accuracy of the technological process and the product yield are effectively improved.

The invention discloses an intelligent injection molding product quality prediction method, which comprises the steps of collecting product structure information, mold parameters and injection molding equipment operation parameters, and constructing a scientific mold testing process window based on simulation analysis; designing an orthogonal experiment scheme to generate a simulation data set, and forming a multi-source data training sample in combination with field test model data; training a quality prediction model by using a distributed gradient boosting tree model, inputting process parameters, and outputting quality indexes such as product gram weight, volume shrinkage and buckling deformation; the model interpretability is realized through a shop value analysis method, and the influence weight of the process parameters on the quality indexes is evaluated; the model is deployed in a production control system or a cloud platform, the product quality is predicted in real time, a dynamic feedback mechanism is established, and when the error between actual detection data and a predicted value exceeds a threshold value, model retraining and parameter correction are automatically triggered to form closed-loop control. The method effectively improves the accuracy, transparency and engineering adaptability of quality prediction of the injection molding product, and can be popularized.

The invention provides a semiconductor device and a manufacturing method thereof, and electronic equipment. The manufacturing method comprises the following steps: forming a stack structure on a substrate; forming a plurality of initial isolation structures arranged along the first direction in the stacked structure, wherein the initial isolation structures extend along the second direction; wherein a cavity exists in at least one initial isolation structure; a groove is formed in at least one side of the two opposite sides of the initial isolation structures in the second direction, the groove extends in the first direction, and the multiple initial isolation structures are exposed out of the side wall of the groove; transversely etching the plurality of initial isolation structures based on the grooves until the cavity is exposed; the removed space and the cavity of the initial isolation structure are filled with an isolation material based on the groove, and the remaining initial isolation structure and the isolation material form an isolation structure. According to the isolation structure after the cavity is eliminated, the consistency of the isolation performance between the functional devices located on the two opposite sides of the isolation structure in the first direction can be improved, and the reliability of a process window and a device during semiconductor device preparation is improved.

Various embodiments of improved process flows and methods are provided herein for etching high aspect ratio (HAR) features in carbon-containing hard mask layers. In the disclosed embodiments, the improved process flows and methods combine sidewall passivation and mask de-clogging steps in a single plasma process step to improve throughput when etching HAR features (such as vias, contact holes, trenches, etc.) within a carbon-containing hard mask layer. In doing so, the improved process flows and methods disclosed herein protect the sidewall surfaces of the carbon-containing hard mask layer and prevent bowing during the HAR etch process, while also reducing processing time and improving throughput.

This application provides a method, system, in-situ online detection device, computer equipment, and storage medium for optimizing process parameters. The method involves acquiring process parameters and measurement data within a preset window; extracting characteristic parameters representing the physical state of wafer surface growth based on the measurement data; inputting the characteristic parameters and process parameters into a pre-trained prediction model to obtain prediction results representing the growth state trend and photoelectric property change trend; optimizing the process parameters based on the prediction results, and using the optimized process parameters for the epitaxial growth process of the wafer in the next preset window. By employing this approach, the application extracts characteristic parameters representing the physical state of growth from the original measurement data. Based on these characteristic parameters, the application automatically analyzes the high-dimensional relationships between multiple parameters and finds the globally optimal process window without relying on prior models and parameters. The generated prediction results are consistent with the actual growth mechanism, effectively improving the accuracy of the process and product yield.

The invention relates to the field of integrated circuit manufacturing, in particular to a light source mask collaborative optimization method and device, and the method comprises the steps: obtaining an initial light source and an initial mask pattern; the initial mask pattern is a binary image; determining the adjusted initial light source and the adjusted initial mask pattern corresponding to the minimum function value of the light source mask collaborative optimization loss function as an optimized light source and an optimized mask pattern; the light source mask collaborative optimization loss function comprises a main pattern edge error item and a sub-resolution auxiliary pattern printing item; obtaining a simulation photoetching image, and judging whether a sub-resolution auxiliary pattern is printed in the simulation photoetching image or not; when the printed sub-resolution auxiliary pattern exists, outputting the latest optimized mask pattern as a process iteration mask pattern; calculating a proportion value; and when the proportion value does not exceed the qualified upper limit value, outputting an optimized light source and process iteration mask pattern. The method can ensure that no sub-resolution auxiliary pattern is printed and a larger process window is reserved.

The invention discloses a method for preparing an aluminum alloy capillary structure based on a selective laser melting technology, which comprises the following steps of: comprehensively regulating and controlling technological parameters of selective laser melting according to laser energy density by utilizing the forming principle of'incomplete melting pores' and'keyhole pores' in a selective laser melting forming process; and the porosity-adjustable aluminum alloy capillary structure is prepared. The method mainly comprises the following steps that firstly, aluminum alloy spherical powder with the particle size range suitable for the selective laser melting process is selected; secondly, a laser energy density reference value is selected according to the optimal technological parameters of selective laser melting forming of the aluminum alloy solid structure; then, according to the laser energy density, the laser power, the scanning rate, the scanning interval and other technological parameters are comprehensively regulated and controlled, the powder laying layer thickness is set, and the aluminum alloy capillary structure is prepared; and finally, the porosity of the capillary structure is measured, the correlation between the technological parameters and the porosity is established, a technological window is determined, and the aluminum alloy capillary structure with the adjustable porosity is prepared.

The invention relates to an epitaxial layer manufacturing method, an epitaxial layer and a super junction power device with an enlarged process window. The method comprises the following steps: providing an N-type substrate with high doping concentration, growing an N-type semiconductor with low doping concentration, and forming a first epitaxial layer; growing an N-type semiconductor on the first plane to form a second epitaxial layer; forming a first barrier layer on the front surface of the wafer; etching the front surface of the wafer to form a plurality of first trapezoidal grooves; growing an N-type semiconductor on the front surface of the wafer, filling the first trapezoidal groove, and forming an N-type column of the super junction power device by the N-type semiconductor in the first trapezoidal groove; forming a second barrier layer on the front surface of the wafer; etching the front surface of the wafer to form a plurality of second trapezoidal grooves; and growing a P-type semiconductor on the front surface of the wafer, filling the second trapezoidal groove, and forming a P-type column of the super junction power device by the P-type semiconductor in the second trapezoidal groove. According to the invention, the problem of error amplification of a grooving filling process is solved.

A virtual fabrication environment for semiconductor device fabrication that includes an analytics module for performing process window optimization is discussed.

The invention discloses an environment monitoring management system and method for a precision workshop, and relates to the technical field of environment monitoring and control, and the method comprises the steps: synchronously collecting multi-dimensional environment parameters through a distributed sensor network, accessing a manufacturing execution system in real time, analyzing the requirements of a process window, and carrying out the real-time monitoring of the environment parameters; and performing fusion and abnormality diagnosis on the data under a unified space-time reference, generating a closed-loop regulation and control instruction, and coordinating and controlling an execution mechanism. The system comprises a multi-mode environment perception unit, a process semantic analysis unit, a space-time fusion and abnormality diagnosis engine, an intelligent regulation and control decision unit and an execution mechanism cooperative control unit. According to the invention, deep understanding of environment disturbance and production process relevance can be realized, compound environment abnormity can be accurately identified, production task requirements can be adapted in real time, environment parameters are ensured to be always in an optimal process tolerance band, the product yield and the process repeatability are obviously improved, and millisecond-level response and cooperative linkage control are realized.

The invention provides a display backboard stamping process optimization method and system, and relates to the technical field of process optimization. According to the method, multi-area differential mesh division is carried out on a plate finite element model, fine meshes are adopted for a high-strain small-curvature area and a high-strain area, rough meshes are adopted for a trimming allowance area, and medium meshes are adopted for other areas. The deformation behavior of the key area is accurately captured, and the reliability of simulation prediction is remarkably improved under the same computing resource. And then, reverse compensation iterative correction and rapid convergence are performed on the initial molded surface based on a springback prediction result to obtain an optimized molded surface model, and source control is directly performed for springback errors, so that the number of times and period of mold testing which traditionally depends on experience are greatly reduced. According to the method, through linkage of simulation and real-time sensing data, dynamic optimization and closed-loop control of the process window are achieved, and the forming quality and production stability of the display backboard are effectively improved.

The invention provides a method for determining an optimal focus. The method comprises the following steps of: providing a wafer which is subjected to photoetching treatment under different focus settings; performing optical critical dimension measurement on the photoresist pattern on the wafer to obtain a plurality of side wall angle values respectively corresponding to different focus settings; based on the plurality of side wall angle values and different focus settings, establishing a relationship between the side wall angles and the focuses; and according to the relationship, determining a focus when the side wall angle is the preset target angle as an optimal focus. According to the method, by directly utilizing the side wall angle parameter strongly related to the focusing quality, the measurement interference of a traditional method is avoided, and the optimal focus of the photoetching process can be determined more accurately and reliably, so that the process window is widened, and the process stability and the product yield are improved.

The invention relates to the related technical field of semiconductors, in particular to a chip processing production line monitoring method and system, and the method comprises the steps: collecting photoetching process monitoring data; setting a feature matrix; determining a focusing window boundary; configuring a focal length offset compensation amount based on the feature matrix in combination with a focusing window boundary and photolithographic process monitoring data; and determining a deviation amplitude score by using an edge placement error model to perform graded reminding. The technical problems that window boundary definition monitored by a chip processing production line depends on experience to set a fixed standard, focal length offset cannot be effectively compensated, and the risk that edge placement errors exceed the standard exists are solved, and coupling analysis of an optical proximity effect and a process window is carried out in a mask layer, a lens layer and a photoresist layer and a feature matrix is constructed, so that the edge placement error is accurately determined. And the compensation parameters and the error trend are dynamically matched, the focal length offset compensation precision is improved, an edge placement error model is used for determining a deviation amplitude score and carrying out graded reminding, and the technical effect of abnormity processing timeliness is enhanced.

This application relates to the field of processing control technology, and discloses a method and system for controlling the forging processing process based on digital twin. The method includes: collecting data streams of the temperature field and stress field of large hydraulic press equipment and forgings at multiple points in partitions; performing organization-defect correlation pattern recognition on the data streams to generate a forging process database; constructing a digital twin model using the constitutive unit nesting method, with macroscopic units embedding microscopic tissue evolution units; performing non-linear progressive simulation to obtain critical deformation conditions and defect thresholds; performing reverse solution of the process window to obtain the optimal process parameter combination. This application establishes a forging digital twin model through the constitutive unit nesting method, realizes the bidirectional coupling of macroscopic deformation and microscopic tissue evolution, and determines a robust process parameter combination through the reverse solution technology of the process window, thereby improving the quality stability and production efficiency of forgings.

The invention provides a photoresist process parameter compensation method and a compensation control system, and the method comprises the steps: building a Lasso regression model through collected process parameters in a plurality of batches of photoresist processes, and carrying out the data training, the method comprises the following steps: reversely analyzing a nonlinear influence mechanism of an external environment temperature on the photoresist thickness through a model, then obtaining a compensation rule of a real-time environment temperature through a Lasso regression model, and dynamically adjusting a photoresist spin-coating rotating speed in a current batch photoresist process so as to maintain the thickness of the current batch photoresist to be constant; according to the method, the stability of the critical dimension (CD) of the photoetching process is improved, a photoetching process window is expanded (the exposure dose fluctuation range of a photoetching machine is widened and the debugging cost of the photoetching process is reduced), accurate temperature compensation of the photoetching process is realized, so that the no-load energy consumption of the photoetching machine is reduced, and the product yield and the reliability are improved.

The invention provides a thick copper twelve-layer plate lamination white point defect prediction and process window optimization method, which comprises the steps of constructing multi-source process parameter input of time-space alignment, denoising and standardization, performing branch feature extraction through a Transform main branch and a graph neural network embedded with causal logic, performing adaptive weighted integration of features through a gating fusion mechanism, and performing optimization of the lamination white point defect prediction and process window optimization of the thick copper twelve-layer plate lamination white point defect prediction and process window optimization of the thick copper twelve-layer plate lamination white point defect. High-confidence prediction of the occurrence probability and spatial distribution of white spot defects is realized, adaptive calibration and online incremental training of a model are driven by predicting uncertainty, and finally, an optimal temperature-pressure-vacuum degree process parameter combination is generated based on a multi-objective optimization method. According to the invention, the accuracy of white point defect early warning and the adaptive optimization capability of the system process are improved.

The invention belongs to the technical field of battery diaphragms, and relates to a wet-process bidirectional asynchronous and synchronous coexisting diaphragm preparation method, which comprises the following operation steps: material mixing and extrusion, longitudinal stretching, synchronous small-draw-ratio stretching, primary transverse stretching, extraction, secondary transverse stretching, and diaphragm forming and rolling. According to the technology, synchronous stretching and bidirectional asynchronous stretching are combined in the wet process field, transverse stretching of a membrane is divided into two times, synchronous small-draw-ratio stretching operation is set between longitudinal stretching and one-time transverse stretching, transverse and longitudinal simultaneous stretching is completed after longitudinal stretching, the obtained lattice structure is firm, and the consistency of molecular orientation is guaranteed; the diaphragm prepared by the process has the characteristics of high strength, low thickness, high gap uniformity and consistency and the like; the process mode is flexible and changeable, the diversity of wet process adjustment can be increased, more possibilities are provided for new product development, product performance is optimized, and a larger process window is provided for development of ultra-thin and ultra-strong products.

The invention relates to an optical proximity correction method and correction device, a mask, equipment and a storage medium. The method comprises the following steps: determining a correction limited graph from original correction graphs; wherein the correction limited pattern is a pattern which triggers edge placement error limitation, and the original correction pattern is a pattern obtained after first optical proximity correction is carried out on the photoetching design pattern; determining a to-be-corrected graph in the photoetching design graph based on the position of the correction limited graph in the original correction graph; performing second optical proximity correction on the to-be-corrected graph to obtain a target corrected graph; and processing the original correction graph based on the target correction graph to obtain a mask graph. According to the mask pattern, the influence of edge placement error limitation on the correction process can be eliminated, the correction precision of the photoetching design pattern after optical proximity correction is improved, the abnormities of narrowing, retraction and the like of the photoetching pattern are improved, the process window is improved, and the process risk is reduced.

The invention provides a method for measuring impedance of a capacitively coupled plasma source, which comprises the following steps of: under the condition that plasma is not ignited, dividing a cavity into an upper part and a lower part along an electrical middle plane, and establishing an equivalent circuit model comprising five elements to be determined; three measurement ports are defined, five independent measurement boundary conditions are set, sweep frequency measurement is carried out by using a network analyzer, and multiple groups of Z parameter data are obtained; then, on each frequency point, joint fitting is carried out on a theoretical impedance expression of the equivalent circuit and actually measured data, and parameter values of all undetermined elements are solved; and finally, outputting a parameter curve of each element along with frequency change and a cavity equivalent impedance spectrum. According to the method, the problem that equivalent parameters cannot be identified is solved through multi-working-condition data redundancy, universal, accurate and reproducible measurement of the impedance of the pure cavity is realized, and a reliable quantitative basis is provided for matching network design, process window prediction and cavity optimization.

The invention discloses an SRAF placement method based on a Bayesian model. The method comprises the steps that historical SRAF configuration parameters and photoetching simulation data are collected and preprocessed; based on the preprocessed data, using kernel density estimation to construct prior probability distribution; constructing a likelihood function of multiple photoetching result indexes in combination with a Hopins photoetching model; calculating approximate distribution of a posterior probability through variation inference by using the Bayesian theorem; and finally selecting an optimal SRAF configuration parameter according to the posterior distribution, and verifying the manufacturing feasibility of the process window and the mask. According to the method, historical prior knowledge and real-time photoetching data are organically integrated through the Bayesian model, and high-precision, high-efficiency and high-robustness optimization of the SRAF layout is realized by combining specific technical characteristics such as preprocessing, kernel density estimation, a Hopkinson physical model and variation approximation; the problems of complex rule base, time-consuming calculation and insufficient adaptability in the prior art are effectively solved.

The invention provides a mask pattern optimization method, a medium, a product and equipment. The method comprises the following steps: acquiring a mask pattern to be corrected and a corresponding ideal photoetching pattern; calling an artificial intelligence model in the inversion photoetching tool to generate a photoetching simulation result according to the mask pattern to be corrected; calculating a cost value according to the photoetching simulation result and the ideal photoetching graph; correcting the mask pattern to be corrected based on the cost value by using an inversion photoetching algorithm to obtain a corrected mask pattern; and taking the corrected mask pattern as a to-be-corrected mask pattern, and repeatedly executing the step of calling the artificial intelligence model in the inversion photoetching tool to generate a photoetching simulation result according to the to-be-corrected mask pattern until a preset cycle ending condition is met, thereby obtaining an optimized mask pattern. Through the method, the inversion photoetching tool can be highly matched with an OPC tool of a corresponding manufacturer, so that a process window of a dead pixel area is effectively improved, and a solid foundation is laid for improvement of the overall yield of technical nodes.

The application relates to the field of photoetching technology, and particularly relates to a method and device for rapidly screening overlay mark manufacturability and computer equipment, which comprises the following steps: inputting preset range of process window conditions, selecting upper limit value and lower limit value as extreme process window conditions; calculating initial process variation bandwidth value based on the extreme process window conditions, and performing first screening on the initial process variation bandwidth value based on a preset screening ratio; calculating to-be-processed process window values corresponding to the screened process variation bandwidth values; performing second screening on the to-be-processed process window values based on a preset standard range to obtain final process window values; and screening the overlay marks corresponding to the final process window values. The application further provides a device and computer equipment. The problems of time and labor consumption in screening overlay mark manufacturability are solved.

The present invention provides a layout correction method for improving the process window of a metal layer. A first corrected pattern after optical proximity correction of a pattern to be corrected is provided, and a first exposure profile thereof is obtained according to the first corrected pattern. An area where the line width in the first exposure profile does not meet the design standard is defined as a hot spot pattern; the first pattern is moved a partial distance to the side away from the third pattern to obtain a fourth pattern; the original pattern corresponding to the hot spot pattern is subjected to optical proximity correction according to the second to fourth patterns to obtain a second corrected pattern, and a second exposure profile thereof is obtained according to the second corrected pattern, so that the line width in the second corrected pattern meets the design standard, and the exposed profile after correction of the second pattern wraps the exposed profile after correction of the fourth pattern. The present invention increases the correction movement space of the hot spot line width of the metal layer and improves its process window, and does not cause the problem of insufficient wrapping area.

A method for forming a semiconductor structure, the method comprising: providing a substrate including a target layer for forming a target pattern, forming a pattern definition layer on the target layer, and forming a first sacrificial layer in the pattern definition layer; removing the first sacrificial layer at the junction of the pattern definition layer and the first sacrificial layer to form a first opening; forming a first sidewall layer on the sidewall of the first opening, the first sidewall layer including a first sub-sidewall layer and a second sub-sidewall layer; filling a second sacrificial layer in the first opening, the second sacrificial layer and the first sacrificial layer constituting a sacrificial structure; removing the sacrificial structure in contact with the sidewall of the first sub-sidewall layer or the sidewall of the second sub-sidewall layer to form a second opening surrounded by the sacrificial structure, the second sub-sidewall layer, and the target layer; forming a second sidewall layer on the sidewall of the second opening; and transferring the patterns of the first sidewall layer and the second sidewall layer to the target layer to form a target pattern. The present invention not only increases the process window but also reduces the pitch between target patterns.

A method of correcting image data of an image sensor provided herein includes collecting a process window from the image sensor; obtaining weight factors of the process window in various directions based on readout values of the second photodiodes in the process window; obtaining interpolated values of the second photodiodes at positions of the first photodiodes in the first pixel groups in the process window by using the weight factors; and estimating a corrected value Btarget of a target first photodiode by an equation I: Btarget=Gint×(Bmean / Gmean), wherein Gint is the interpolated value of the second photodiodes at a position of the target first photodiode, Bmean is a mean of readout values of first photodiodes in a corresponding first pixel group including the target first photodiode and Gmean is a mean of the interpolated values of the second photodiodes at positions of the first photodiodes in the corresponding first pixel group.

The invention discloses a manufacturing method of a cold-rolled sheet. The cold-rolled sheet comprises the following chemical components in percentage by mass: 0.105%-0.125% of C, 0.20%-0.30% of Si, 2.30%-2.55% of Mn, less than or equal to 0.020% of P, less than or equal to 0.010% of S, 0.020%-0.050% of Alt, 0.50%-0.60% of Cr, 0.10%-0.20% of Mo, 0.020%-0.030% of Nb, 0.015%-0.025% of Ti, 0.0008%-0.0020% of Ca, less than or equal to 0.0070% of N and the balance of Fe. And the balance Fe and impurities. The invention further discloses key process control parameters. According to the method, the excellent effect is achieved through fine metallurgical design and process control of the whole process, especially innovative chemical component design and process window optimization of key procedures.

The invention discloses a method for determining the optimal exposure focal length difference, which comprises the following steps: obtaining exposure data sets of various types of semiconductor products, the exposure data sets comprising the optimal exposure focal length difference and pattern spacing of the corresponding type of products, the optimal exposure focal length difference is the difference value of the maximum exposure focal length of the exposure process window in the two exposure processes; fitting according to the exposure data set to obtain a mapping relationship, wherein the mapping relationship is a relationship between the optimal exposure focal length and the pattern spacing; and determining the optimal exposure focal length of the target type product according to the mapping relation and the pattern spacing of the target product. According to the method, the exposure data sets of the semiconductor products of various types are obtained, the mapping relation between the optimal exposure focal length difference and the pattern spacing is obtained through fitting according to the exposure data sets, and then the optimal exposure focal length difference of the product in two exposure processes is determined according to the mapping relation and the pattern spacing of the product of the target type.

The invention provides a guide hole and a pattern correction method thereof, and belongs to the field of semiconductors. The guide hole pattern correction method comprises the steps that an initial pattern is provided, the initial pattern comprises a metal layer and a guide hole layer, and guide hole patterns located in an isolated area are screened to serve as guide hole patterns to be corrected; amplifying the to-be-corrected guide hole pattern to obtain a sub-pattern; the sprite is corrected, a corrected graph is obtained, the projection of the corrected graph on the metal layer graph is located in the metal layer graph, and the area of the corrected graph is larger than or equal to the area of the sprite. According to the method, the side length of the first side of the sub-pattern is shortened, the side length of the second side of the sub-pattern is increased, and the corrected pattern is obtained, so that on the premise of improving a guide hole pattern process window, defects of a metal layer pattern are avoided, and the connection reliability of the metal layer is improved.

The application provides a method for increasing the process window of an ILD filling of a flash memory device, which comprises the following steps: providing a semiconductor structure, which comprises a semiconductor substrate, a gate dielectric layer, a word line polysilicon, a floating gate and a control gate; forming an oxide layer on the surface of the semiconductor structure, and forming a nitride layer on the surface of the oxide layer; etching the nitride layer and the oxide layer by an etching process to form a first side wall on the outside of the floating gate, the control gate, the intermediate dielectric layer and the word line side wall; cleaning the semiconductor structure with the first side wall by a first wet cleaning process; ion implanting the semiconductor substrate to form a source region and a drain region on both sides of the first side wall; and cleaning the semiconductor structure with the source region and the drain region by a second wet cleaning process. The application solves the problem of the existing flash memory device in the ILD filling process.