189 results about "Process window" patented technology

The invention provides a semiconductor device and a manufacturing method thereof, and electronic equipment. The manufacturing method comprises the following steps: forming a stack structure on a substrate; forming a plurality of initial isolation structures arranged along the first direction in the stacked structure, wherein the initial isolation structures extend along the second direction; wherein a cavity exists in at least one initial isolation structure; a groove is formed in at least one side of the two opposite sides of the initial isolation structures in the second direction, the groove extends in the first direction, and the multiple initial isolation structures are exposed out of the side wall of the groove; transversely etching the plurality of initial isolation structures based on the grooves until the cavity is exposed; the removed space and the cavity of the initial isolation structure are filled with an isolation material based on the groove, and the remaining initial isolation structure and the isolation material form an isolation structure. According to the isolation structure after the cavity is eliminated, the consistency of the isolation performance between the functional devices located on the two opposite sides of the isolation structure in the first direction can be improved, and the reliability of a process window and a device during semiconductor device preparation is improved.

The invention relates to the field of integrated circuit manufacturing, in particular to a light source mask collaborative optimization method and device, and the method comprises the steps: obtaining an initial light source and an initial mask pattern; the initial mask pattern is a binary image; determining the adjusted initial light source and the adjusted initial mask pattern corresponding to the minimum function value of the light source mask collaborative optimization loss function as an optimized light source and an optimized mask pattern; the light source mask collaborative optimization loss function comprises a main pattern edge error item and a sub-resolution auxiliary pattern printing item; obtaining a simulation photoetching image, and judging whether a sub-resolution auxiliary pattern is printed in the simulation photoetching image or not; when the printed sub-resolution auxiliary pattern exists, outputting the latest optimized mask pattern as a process iteration mask pattern; calculating a proportion value; and when the proportion value does not exceed the qualified upper limit value, outputting an optimized light source and process iteration mask pattern. The method can ensure that no sub-resolution auxiliary pattern is printed and a larger process window is reserved.

The invention discloses an environment monitoring management system and method for a precision workshop, and relates to the technical field of environment monitoring and control, and the method comprises the steps: synchronously collecting multi-dimensional environment parameters through a distributed sensor network, accessing a manufacturing execution system in real time, analyzing the requirements of a process window, and carrying out the real-time monitoring of the environment parameters; and performing fusion and abnormality diagnosis on the data under a unified space-time reference, generating a closed-loop regulation and control instruction, and coordinating and controlling an execution mechanism. The system comprises a multi-mode environment perception unit, a process semantic analysis unit, a space-time fusion and abnormality diagnosis engine, an intelligent regulation and control decision unit and an execution mechanism cooperative control unit. According to the invention, deep understanding of environment disturbance and production process relevance can be realized, compound environment abnormity can be accurately identified, production task requirements can be adapted in real time, environment parameters are ensured to be always in an optimal process tolerance band, the product yield and the process repeatability are obviously improved, and millisecond-level response and cooperative linkage control are realized.

The invention provides a display backboard stamping process optimization method and system, and relates to the technical field of process optimization. According to the method, multi-area differential mesh division is carried out on a plate finite element model, fine meshes are adopted for a high-strain small-curvature area and a high-strain area, rough meshes are adopted for a trimming allowance area, and medium meshes are adopted for other areas. The deformation behavior of the key area is accurately captured, and the reliability of simulation prediction is remarkably improved under the same computing resource. And then, reverse compensation iterative correction and rapid convergence are performed on the initial molded surface based on a springback prediction result to obtain an optimized molded surface model, and source control is directly performed for springback errors, so that the number of times and period of mold testing which traditionally depends on experience are greatly reduced. According to the method, through linkage of simulation and real-time sensing data, dynamic optimization and closed-loop control of the process window are achieved, and the forming quality and production stability of the display backboard are effectively improved.

The invention relates to the related technical field of semiconductors, in particular to a chip processing production line monitoring method and system, and the method comprises the steps: collecting photoetching process monitoring data; setting a feature matrix; determining a focusing window boundary; configuring a focal length offset compensation amount based on the feature matrix in combination with a focusing window boundary and photolithographic process monitoring data; and determining a deviation amplitude score by using an edge placement error model to perform graded reminding. The technical problems that window boundary definition monitored by a chip processing production line depends on experience to set a fixed standard, focal length offset cannot be effectively compensated, and the risk that edge placement errors exceed the standard exists are solved, and coupling analysis of an optical proximity effect and a process window is carried out in a mask layer, a lens layer and a photoresist layer and a feature matrix is constructed, so that the edge placement error is accurately determined. And the compensation parameters and the error trend are dynamically matched, the focal length offset compensation precision is improved, an edge placement error model is used for determining a deviation amplitude score and carrying out graded reminding, and the technical effect of abnormity processing timeliness is enhanced.

The invention provides a thick copper twelve-layer plate lamination white point defect prediction and process window optimization method, which comprises the steps of constructing multi-source process parameter input of time-space alignment, denoising and standardization, performing branch feature extraction through a Transform main branch and a graph neural network embedded with causal logic, performing adaptive weighted integration of features through a gating fusion mechanism, and performing optimization of the lamination white point defect prediction and process window optimization of the thick copper twelve-layer plate lamination white point defect prediction and process window optimization of the thick copper twelve-layer plate lamination white point defect. High-confidence prediction of the occurrence probability and spatial distribution of white spot defects is realized, adaptive calibration and online incremental training of a model are driven by predicting uncertainty, and finally, an optimal temperature-pressure-vacuum degree process parameter combination is generated based on a multi-objective optimization method. According to the invention, the accuracy of white point defect early warning and the adaptive optimization capability of the system process are improved.

The invention provides a method for measuring impedance of a capacitively coupled plasma source, which comprises the following steps of: under the condition that plasma is not ignited, dividing a cavity into an upper part and a lower part along an electrical middle plane, and establishing an equivalent circuit model comprising five elements to be determined; three measurement ports are defined, five independent measurement boundary conditions are set, sweep frequency measurement is carried out by using a network analyzer, and multiple groups of Z parameter data are obtained; then, on each frequency point, joint fitting is carried out on a theoretical impedance expression of the equivalent circuit and actually measured data, and parameter values of all undetermined elements are solved; and finally, outputting a parameter curve of each element along with frequency change and a cavity equivalent impedance spectrum. According to the method, the problem that equivalent parameters cannot be identified is solved through multi-working-condition data redundancy, universal, accurate and reproducible measurement of the impedance of the pure cavity is realized, and a reliable quantitative basis is provided for matching network design, process window prediction and cavity optimization.

The invention discloses an SRAF placement method based on a Bayesian model. The method comprises the steps that historical SRAF configuration parameters and photoetching simulation data are collected and preprocessed; based on the preprocessed data, using kernel density estimation to construct prior probability distribution; constructing a likelihood function of multiple photoetching result indexes in combination with a Hopins photoetching model; calculating approximate distribution of a posterior probability through variation inference by using the Bayesian theorem; and finally selecting an optimal SRAF configuration parameter according to the posterior distribution, and verifying the manufacturing feasibility of the process window and the mask. According to the method, historical prior knowledge and real-time photoetching data are organically integrated through the Bayesian model, and high-precision, high-efficiency and high-robustness optimization of the SRAF layout is realized by combining specific technical characteristics such as preprocessing, kernel density estimation, a Hopkinson physical model and variation approximation; the problems of complex rule base, time-consuming calculation and insufficient adaptability in the prior art are effectively solved.

The invention provides a mask pattern optimization method, a medium, a product and equipment. The method comprises the following steps: acquiring a mask pattern to be corrected and a corresponding ideal photoetching pattern; calling an artificial intelligence model in the inversion photoetching tool to generate a photoetching simulation result according to the mask pattern to be corrected; calculating a cost value according to the photoetching simulation result and the ideal photoetching graph; correcting the mask pattern to be corrected based on the cost value by using an inversion photoetching algorithm to obtain a corrected mask pattern; and taking the corrected mask pattern as a to-be-corrected mask pattern, and repeatedly executing the step of calling the artificial intelligence model in the inversion photoetching tool to generate a photoetching simulation result according to the to-be-corrected mask pattern until a preset cycle ending condition is met, thereby obtaining an optimized mask pattern. Through the method, the inversion photoetching tool can be highly matched with an OPC tool of a corresponding manufacturer, so that a process window of a dead pixel area is effectively improved, and a solid foundation is laid for improvement of the overall yield of technical nodes.

The application relates to the field of photoetching technology, and particularly relates to a method and device for rapidly screening overlay mark manufacturability and computer equipment, which comprises the following steps: inputting preset range of process window conditions, selecting upper limit value and lower limit value as extreme process window conditions; calculating initial process variation bandwidth value based on the extreme process window conditions, and performing first screening on the initial process variation bandwidth value based on a preset screening ratio; calculating to-be-processed process window values corresponding to the screened process variation bandwidth values; performing second screening on the to-be-processed process window values based on a preset standard range to obtain final process window values; and screening the overlay marks corresponding to the final process window values. The application further provides a device and computer equipment. The problems of time and labor consumption in screening overlay mark manufacturability are solved.

A method of correcting image data of an image sensor provided herein includes collecting a process window from the image sensor; obtaining weight factors of the process window in various directions based on readout values of the second photodiodes in the process window; obtaining interpolated values of the second photodiodes at positions of the first photodiodes in the first pixel groups in the process window by using the weight factors; and estimating a corrected value Btarget of a target first photodiode by an equation I: Btarget=Gint×(Bmean / Gmean), wherein Gint is the interpolated value of the second photodiodes at a position of the target first photodiode, Bmean is a mean of readout values of first photodiodes in a corresponding first pixel group including the target first photodiode and Gmean is a mean of the interpolated values of the second photodiodes at positions of the first photodiodes in the corresponding first pixel group.

The invention discloses a manufacturing method of a cold-rolled sheet. The cold-rolled sheet comprises the following chemical components in percentage by mass: 0.105%-0.125% of C, 0.20%-0.30% of Si, 2.30%-2.55% of Mn, less than or equal to 0.020% of P, less than or equal to 0.010% of S, 0.020%-0.050% of Alt, 0.50%-0.60% of Cr, 0.10%-0.20% of Mo, 0.020%-0.030% of Nb, 0.015%-0.025% of Ti, 0.0008%-0.0020% of Ca, less than or equal to 0.0070% of N and the balance of Fe. And the balance Fe and impurities. The invention further discloses key process control parameters. According to the method, the excellent effect is achieved through fine metallurgical design and process control of the whole process, especially innovative chemical component design and process window optimization of key procedures.

The application provides a method for increasing the process window of an ILD filling of a flash memory device, which comprises the following steps: providing a semiconductor structure, which comprises a semiconductor substrate, a gate dielectric layer, a word line polysilicon, a floating gate and a control gate; forming an oxide layer on the surface of the semiconductor structure, and forming a nitride layer on the surface of the oxide layer; etching the nitride layer and the oxide layer by an etching process to form a first side wall on the outside of the floating gate, the control gate, the intermediate dielectric layer and the word line side wall; cleaning the semiconductor structure with the first side wall by a first wet cleaning process; ion implanting the semiconductor substrate to form a source region and a drain region on both sides of the first side wall; and cleaning the semiconductor structure with the source region and the drain region by a second wet cleaning process. The application solves the problem of the existing flash memory device in the ILD filling process.

The invention discloses an exposure dose determination method, device and equipment and a storage medium, which are applied to the technical field of photoetching, and the method comprises the following steps: obtaining a target critical size and a line width drift tolerance limit between an exposure pattern formed after photoresist exposure and an etched functional layer pattern; obtaining an exposure dose slope; the exposure dose slope is a slope value determined based on the critical dimensions of the corresponding exposure patterns under different exposure doses; determining an exposure dose step length according to the line width drift tolerance limit and the exposure dose slope; and determining a target exposure dose corresponding to the target key size according to the exposure dose step length. The exposure dose step length is calculated based on the line width drift tolerance limit between the exposure pattern formed after exposure and the functional layer pattern formed after etching, so that the target exposure dose can ensure that the line width drift between the exposure pattern formed after exposure and the functional layer pattern formed after etching meets the requirement; therefore, the process window loss can be reduced.

The application discloses a process window determination method, a semiconductor processing method and equipment, and relates to the technical field of semiconductor manufacturing. In view of the problems of time loss and poor exhaust mode compatibility caused by the fact that the prior art relies on pressure gauge reading stability to determine the process window, the application determines the process window start time by recording the switching period of the measured pressure between two stable pressures and combining the flow switching instruction time; further, the pre-calibration stage and the process stage are distinguished, the switching period is obtained in the pre-calibration stage, and a database is established, and in the process stage, the parameters are directly reused for open-loop operation, and multiple exhaust modes such as fixed opening of the vacuum valve and feedback regulation are compatible. The application can start the process without waiting for the pressure gauge reading to be completely stable, effectively increases the process window time, significantly improves the equipment productivity and process adaptability, and is suitable for rapid pressure switching cyclic semiconductor processes such as atomic layer etching and atomic layer deposition.

The invention discloses a short-process preparation method of an ultra-high-speed laser cladding coating on the surface of a shaft part and the obtained coating, and the method comprises the following steps: firstly, based on energy conservation and momentum balance, calculating and determining a stable process window of ultra-high-speed laser cladding; based on a geometrical optical model, the horizontal offset distance of the laser head relative to the central axis of the workpiece is calculated and controlled. Based on molten pool stress analysis under a rotating coordinate system, the relation between the rotating direction of a workpiece for restraining flowing of a molten pool and the offset direction of a laser head relative to the central axis of the workpiece is determined, under the determined conditions, ultra-high-speed laser cladding is conducted on the outer circle surface of the shaft part, and single-pass precision grinding is directly conducted after cladding. According to the method, the thin-layer coating with the smooth surface and the uniform thickness is obtained through physical stability control, the machining route of cladding-turning-grinding is simplified into cladding-single-pass precision grinding, and the machining allowance and the production cost are remarkably reduced.

The invention discloses a photoetching mask process window analysis method and system, and belongs to the technical field of photoetching processes, and the method comprises the following steps: collecting exposure process parameters, photoetching pattern parameters, window evaluation parameters and auxiliary parameters to construct an exposure analysis vector; selecting historical exposure analysis vectors to form a historical vector set, and constructing a sensitivity matrix; a real-time feature vector is constructed through online detection, and the current process state is judged in combination with a sensitivity matrix so as to identify window abnormity; once the window is identified to be abnormal, through multi-exposure condition simulation, constructing an index simulation value corresponding to a process window index for each group of exposure parameters, and screening an optimal exposure regulation and control group; converting the optimal exposure regulation and control group into an exposure execution instruction, and issuing the exposure execution instruction to execute exposure operation; and after the exposure operation is completed, deviation comparison verification is carried out, and a case sample is constructed to iteratively update the sensitivity matrix, so that the process suitability and the prediction precision are improved, and the automatic production requirement of a photoetching mask preparation production line is effectively met.

The invention provides a processing method of a metal layer layout, and belongs to the technical field of semiconductor manufacturing, and the method comprises the steps: obtaining the metal layer layout and a through hole layer layout corresponding to the metal layer layout; extracting a first process hot spot pattern in the metal layer layout and a background pattern within a preset range around the first process hot spot pattern according to a first preset rule; carrying out edge shrinkage processing on a convex angle edge on the convex angle pattern at a first preset displacement to obtain a pre-processing layout; performing optical proximity effect correction processing on the preprocessed layout to obtain a corrected layout of the metal layer layout; and performing simulation processing on the corrected layout according to a second preset rule to obtain a simulation image. According to the optical proximity correction method, the process hot spot of the convex angle pattern during exposure can be eliminated under a small-size process window, and the defect that the OPC technology is difficult to fully correct the small-feature-size pattern is overcome.

The invention discloses a TOPCon-0BB assembly multi-stage welding method based on a low-temperature welding strip, relates to the technical field of photovoltaic assembly manufacturing, and effectively prevents a packaging adhesive film from permeating into a contact interface in the main welding process through partition scanning preheating and generation of a controllable adhesive film pre-wetting state. A clean initial condition is created for forming high-quality metallurgical bonding; in combination with closed-loop monitoring and regulation of the growth state of the IMC layer, it is ensured that a welding spot has enough mechanical strength, meanwhile, the brittleness problem caused by the too thick IMC layer is avoided, and therefore a welding interface has excellent conductivity and toughness, multiple physical fields are innovatively introduced to intervene and optimize the welding process, and the welding quality is improved. The structural stability and the anti-fatigue performance of the assembly are greatly enhanced; according to the method, the self-adaptive calibration parameters for different packaging material systems are dynamically generated by acquiring and identifying the welding process route identifier of the assembly, so that the process window is greatly widened, and the compatibility of different materials is enhanced.

The invention relates to the technical field of coating processes, and discloses a method for optimizing a middle coating process of a tab slot. The method comprises the following steps: respectively formulating a corresponding single-factor control test group based on a control group of each test slurry; for each piece of test slurry, respectively adopting the corresponding single factor to control the coating process parameter combination of the test group, and carrying out a tab slot middle coating process test; key parameters influencing the cleanliness of the slot and key parameters influencing the edge thickness consistency of the slot are screened out according to the test data; according to the method, the key parameters influencing the cleanliness of the slot position and the consistency of the edge thickness of the slot position are respectively screened out through a single-factor control test, so that a scientific fact basis is provided for process optimization, the optimal process window is conveniently and quickly determined, and engineering application and development of middle coating of the tab are promoted.

There is provided a system and method of process window qualification. The method includes obtaining a wafer comprising a plurality of dies respectively printed under a plurality of process window conditions characterized by varying values of focus and exposure, wherein the wafer is fabricated in accordance with a chip design containing a pattern of interest (POI) comprising a surface structure and an underneath structure; inspecting the wafer at POI locations to obtain a plurality of images each capturing an occurrence of the POI; and providing a group of measurements from the plurality of images, comprising, for each given image: extracting a surface contour of the surface structure and an underneath contour of the underneath structure; shifting one of the contours relative to the other one or more times to simulate one or more overlay variations; and measuring a critical metric between the contours following each shift.

The invention provides a graph splitting method for cracking odd-numbered rings of a metal cutting layer. The graph splitting method comprises the following steps: step 1, generating default splitting identifiers about a current graph and an adjacent graph based on a default splitting rule; 2, screening out graphs forming an odd number ring from the graphs for calibrating the default splitting identifiers, adjusting the splitting rules of the graphs forming the odd number ring, and calibrating specific splitting identifiers among the graphs violating the line end rule and the angle-to-angle rule; and step 3, dividing the adjacent graph with the specific splitting identifier or the default splitting identifier calibrated between the current graph and the adjacent graph into a first metal cutting mask, and dividing the rest adjacent graphs and the current graph into a second metal cutting mask. On the premise that the process difficulty and cost are not increased, uncontrollability, caused by rule conflicts, of the splitting structure is broken, various splitting results possibly existing in the splitting process are avoided, then the purpose of optimizing a metal cutting layer process window is achieved, and the risk of short circuit or open circuit of a metal wire is effectively reduced.

The application discloses an additive manufacturing method based on non-complete melting metal powder and belongs to the technical field of metal additive manufacturing. The additive manufacturing method based on non-complete melting metal powder comprises the following steps: obtaining a three-dimensional model of a target component, slicing and layering the three-dimensional model and planning a scanning path, and importing slice data and scanning path planning data into an additive manufacturing device; laying metal powder on a substrate to form a powder layer; controlling an energy beam to scan the powder layer according to slice data of the target component; repeating the powder layer laying and scanning steps to process layer by layer to obtain the component. The application precisely controls the energy density of the energy beam within a process window in which the surface of the metal powder is melted and bonded while the core is not melted, and the component is formed by layer-by-layer scanning, thereby solving the technical problems of high residual stress, cracks and poor organization performance caused by complete melting in the powder bed melting technology in the prior art.

The invention discloses a carbon electrode process control method and system, and the method comprises the steps: carrying out the secondary index division of multi-source data indexes of a carbon raw material, and constructing a comparable data space of the indexes of the raw material; establishing a comprehensive index system based on the comparable data space, and constructing a two-stage linear weight coupling structure based on the comprehensive index system to form an index fusion weight vector; based on the index fusion weight vector, constructing a multi-path evaluation decision model, and performing weighted calculation on each index in the comparable data space according to the index fusion weight to generate a corresponding sorting result; based on the sorting result, establishing a standard reaching probability prediction model, and correcting the sorting result according to the standard reaching probability; based on the corrected sorting result, unification processing of the process window is achieved, and a process parameter map is constructed; and carrying out process execution optimization and process monitoring on the carbon electrode production process based on the process parameter atlas. According to the method, the stability and reusability of the carbon electrode process decision are improved.

The invention discloses an HKMG gate work function adjusting process method. The HKMG gate work function adjusting process method comprises the steps of 1, forming an interface layer and a high dielectric constant layer on a semiconductor substrate; and 2, forming a lanthanum oxide layer on the top surface of the high dielectric constant layer. And step 3, performing graphical etching on the lanthanum oxide layer to remove the lanthanum oxide layer outside the first region and retain the lanthanum oxide layer of the first region, wherein the outside of the first region is a region which does not need to reduce the work function of the grid electrode. 4, annealing is carried out to push lanthanum into the high dielectric constant layer, after lanthanum is pushed into the high dielectric constant layer, an electric dipole is formed at the interface of the high dielectric constant layer and the interface layer, and the grid work function of the first area is reduced through the electric dipole. And step 5, removing the residual lanthanum oxide layer. According to the invention, a threshold voltage adjusting process window can be expanded, so that the threshold voltage is matched with a target value to the greatest extent and the device performance is improved.

The invention provides a process window calculation method and system based on block intersection, a medium, a product and a terminal. The method comprises the following steps: determining a plurality of to-be-evaluated areas on a target mask plate in advance; obtaining a process change curve of each to-be-evaluated area through the transmission spectrum distribution based on the target mask plate; the method comprises the following steps: determining at least one corresponding sub-process window according to a process change curve of each to-be-evaluated region; wherein the sub-process windows are represented by geometric figures; performing intersection operation on the sub-process windows of all the to-be-evaluated areas to obtain candidate public process windows; according to a preset screening condition, a target public process window is screened out from candidate public process windows. Compared with a traditional process window calculation method, the method has the advantages that through partition design, geometric figure representation and intersection operation, the solving logic of the public process window is greatly simplified, and the calculation efficiency and precision are effectively balanced and improved.

The application relates to a high-entropy photocatalytic material synthesis method and system. First, experimental plan data containing formula parameters and process parameters are generated under a set high-entropy constraint condition, then precursor preparation and heat treatment are performed according to the experimental plan data to obtain a high-entropy photocatalytic material sample, and synthesis process parameters and post-processing parameters are recorded; then structure characterization and photocatalytic performance evaluation are performed on the sample to obtain photocatalytic performance index parameters, and the experimental plan data, the synthesis process parameters, the post-processing parameters and the photocatalytic performance index parameters are stored as a process pedigree; finally, based on a preset data-driven model and the process pedigree, multi-objective optimization is performed under the same set high-entropy constraint condition, and optimal formula parameters and optimal process parameters are determined. According to the scheme, a process window that truly meets the high-entropy effect and has excellent performance can be quickly converged, so that the research and development efficiency and reproducibility of the high-entropy photocatalytic material are greatly improved.

The application discloses a kind of based on three-dimensional phase diagram straight writing line topography regulation and control method, device, equipment and medium, it is related to printing technical field, comprising: by obtaining the rheological test result of different viscosity ink, printing process parameters and line form characterization data, apparent viscosity and boundary parameter are obtained by integration and power law fitting, construct with normalized height, normalized velocity, apparent viscosity as three-dimensional dimension process phase diagram, then by matching adaptive parameter or ink rheological property obtains target form.This introduces apparent viscosity as the third dimension, optimizes the limitation that two-dimensional phase diagram only adapts specific viscosity ink, quantifies the correlation of process parameters, rheological property and line form, only three core parameters can realize cross-ink system form accurate prediction and regulation, compatible with multiple viscosity inks, significantly reduce parameter optimization time consumption, avoid experience trial and error, accurately identify material process window, provide quantitative target for ink formula optimization, improve printing process adaptability.

A method for determining a process window of a patterning process based on a failure rate. The method includes obtaining a plurality of features printed on a substrate, grouping, based on a metric, the features into a plurality of groups, and generating, based on measurement data associated with a group of features, a base failure rate model for the group of features, wherein the base failure rate model identifies the process window related to the failure rate of the group of features. The method can further include generating, using the base failure rate model, a feature-specific failure rate model for a specific feature, wherein the feature-specific failure rate model identifies a feature-specific process window such that an estimated failure rate of the specific feature is below a specified threshold.

The application discloses an OPC correction sub-resolution auxiliary pattern layout method. A data acquisition module acquires a layout to be corrected by OPC; process windows of isolated patterns and dense patterns in the layout are calculated; SRAF initial rules are acquired, and SRAFs are inserted into the isolated patterns, and the SRAFs are exposed by a lithography model; SRAF widths are set according to SRAF exposure results; distances between the SRAFs and the isolated patterns are updated; and the SRAFs are inserted into the isolated patterns according to updated process parameters. According to a difference between a center position of a process window of the isolated patterns after the SRAFs are inserted and a center position of a process window of the dense patterns, adjustment of SRAF insertion parameters is realized, the SRAF insertion is suitable for isolated patterns of different sizes, is universal, can improve process windows of isolated patterns of various sizes, and finally improves product yield.