13 results about "Design rule checking" patented technology

This disclosure provides a layout test case generation method, apparatus, and related equipment. The layout test cases are used for design rule checking of semiconductor devices. The method includes: converting the design rules of the semiconductor device into a first numerical vector using a first encoding method; converting the first layout test cases into a second numerical vector using a second encoding method; calling a pre-trained neural network model, and using the neural network model to output a second layout test case based on the first and second numerical vectors; wherein the first and second numerical vectors are one-dimensional numerical sequences including multiple values.

The invention relates to a chip layout design method, which belongs to the technical field of semiconductor laser design, solves the technical problems of low efficiency and high possibility of errors in chip design, and comprises the steps of self-adaptive adjustment of design parameters, modular layout design, combination of automation and manual intervention and wiring strategy optimization. The method comprises the steps of multi-objective balance of power consumption, performance and area optimization, real-time integration of design rule check DRC and circuit consistency check LVS, design optimization aiming at an advanced process, and functional module expansion. The design method is used for chip layout design, especially layout design of advanced process nodes.

This application discloses a computational system for implementing yield improvement tools. It extracts cell characteristics from a physical layout design for integrated circuits, determines the location of empty regions in the physical layout design, and applies electrical design rules for manufacturing integrated circuits to the extracted characteristics to identify cells in the physical layout design that will violate the electrical design rules. The computational system can select fill cells for empty regions based at least in part on the extracted characteristics of cells adjacent to empty regions and the electrical design rules, and insert the selected fill cells into the empty regions of the physical design layout. The computational system can perform a design rule checking operation that applies the electrical design rules to the physical design layout where the selected fill cells have been inserted.

The application discloses a layout design rule generation method and device based on a multi-modal intelligent agent technology and a medium, relates to the field of electric digital data processing, and converts a design rule manual into a structured text format and divides the structured text format according to process levels. A visual model is used to perform semantic extraction on a schematic diagram in the manual, generate an image description text, and fuse the image description text with an original rule text. A candidate function set is screened from a function library, historical experience rule library is combined, and a function or function combination required by a current rule is decided. Detailed usage information is acquired, process level auxiliary constraints and global instructions are retrieved from the manual, code specifications are retrieved from the experience knowledge base, all knowledge is enhanced to guide rule semantic restatement, image information selection, function parameter analysis and pre-output self-checking, and layout design rule checking code is generated. The application solves the problems of low manual conversion efficiency and errors, and has the advantages of high generation efficiency, accurate results and good interpretability.

Embodiments of the present disclosure relate to methods, devices, media and program products for layout mapping. Some embodiments of the present disclosure provide a method for layout mapping. In the method according to the present disclosure, constraint information for layout and routing is extracted from the original layout and original circuit to be mapped, and a new circuit under a new process is automatically laid out and routed based on the extracted constraint information to obtain a new layout for implementing the new circuit. In this way, the scheme according to the present disclosure avoids the misalignment, overlap and design rule checking problems caused by direct replacement of hierarchy or parameterized cells in the conventional scheme to the greatest extent, so that the workload of the designer can be greatly reduced.

The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor yield analysis optimization method, system, device and medium based on multi-module cooperation; first, a data collection and integration module is used to collect multi-type data of the whole process of semiconductor manufacturing, and cleaning, standardization and integration processing are performed; second, based on the integrated data, a comprehensive yield analysis model is constructed through historical data statistical analysis and physical model simulation, and the key factors affecting yield are located; then, the analysis results and the expected yield are verified through design rule checking, electrical rule checking and yield prediction verification based on the model; finally, based on the verified analysis results, process parameter optimization and design optimization schemes are formulated and executed, and through a feedback iteration mechanism, continuous optimization is carried out to improve yield.

The application discloses a layout design rule generation method and device based on a multi-modal intelligent agent technology and a medium, relates to the field of electric digital data processing, and converts a design rule manual into a structured text format and divides the structured text format according to process levels. A visual model is used to perform semantic extraction on a schematic diagram in the manual, generate an image description text, and fuse the image description text with an original rule text. A candidate function set is screened from a function library, historical experience rule library is combined, and a function or function combination required by a current rule is decided. Detailed usage information is acquired, process level auxiliary constraints and global instructions are retrieved from the manual, code specifications are retrieved from the experience knowledge base, all knowledge is enhanced to guide rule semantic restatement, image information selection, function parameter analysis and pre-output self-checking, and layout design rule checking code is generated. The application solves the problems of low manual conversion efficiency and errors, and has the advantages of high generation efficiency, accurate results and good interpretability.

Aspects described herein relate to physical verification of a design of an integrated circuit to be fabricated on a semiconductor die. One example method involves inserting a dummy partition cell into a parent cell of a layout of the design of the integrated circuit (54). Sub-cells of the parent cell have a first portion that overlaps the dummy partition cell and a second portion that is outside the dummy partition cell (54-1). The method also includes creating, by one or more processors, a cell hierarchy having the sub-cells and the dummy partition cell descended from the parent cell, where the sub-cells have multiple instances in the hierarchy of cells (54-2), and performing a design rule check run set on the parent cell based on the hierarchy (56).

This disclosure provides a design rule checking method, system, electronic device, and storage medium, relating to the field of quantum chip technology. A design rule checking method includes: sending the DRC information of the chip to be checked to a blockchain network based on a design checking center; performing boundary checks on the chip based on the DRC information through a boundary check blockchain network to obtain boundary check results; performing device connection checks on the chip based on the DRC information through a connection check blockchain network to obtain connection check results; performing device overlap checks on the chip based on the DRC information through an overlap check blockchain network to obtain overlap check results; performing transmission line checks on the chip based on the DRC information through a transmission line check blockchain network to obtain transmission line check results; and displaying at least one check result based on the design checking center. This improves the efficiency and accuracy of design rule checking.

The utility model discloses a kind of packaging structures for preventing transformer straight down threading in the field of circuit board design, including the transformer being set on circuit board, the transformer is below being provided with forbidden wiring area, copper skin is provided in the forbidden wiring area.This utility model solves the problem that the signal line is set in the directly below transformer by the current designer, the utility model is below the transformer is provided with forbidden wiring area, avoid signal line or power line threading, to effectively reduce the adverse effects of electromagnetic interference and heat on circuit, if circuit is set in the directly below transformer area, then circuit board design rule check (DRC) system will issue error prompt, facilitate designer to check in time and correct design error, prevent designer from accidentally setting signal line in the directly below transformer, and copper skin has good electromagnetic shielding effect, can further block the electromagnetic field generated by transformer to leak outward, effectively isolate the electromagnetic interference generated by transformer.

The application discloses a macro unit automatic synthesis method based on splicable analog unit and belongs to the technical field of electronic design automation (EDA). The method aims to solve the problem that device matching constraint, layout area efficiency and design rule check cannot be considered in the existing analog layout automatic process. The method mainly comprises the following steps: receiving a circuit netlist with layout intention annotation, mapping devices into Acells; placing initial row bases according to a symmetric mode; executing a compression algorithm for keeping constraints, optimizing area by removing specific redundant polysilicon structures at the interfaces of adjacent Acells; performing legalization processing based on contact polysilicon spacing and power ground line spacing; finally, adopting a wiring method based on the satisfiability of module theory, automatically generating internal connections under the premise of ensuring geometric symmetry. The application can generate analog macro units meeting the requirements of DRC / LVS, compact in area and high in matching characteristics, and can be directly integrated into a digital layout and wiring process.

The application discloses an integrated circuit layout verification method and device, and belongs to the technical field of integrated circuit design. The method comprises the following steps: obtaining arrangement information of selected target units from an integrated circuit layout; performing out-expanding processing on to-be-detected metal lines of the target units according to design rule spacing requirements, and generating an auxiliary layer pattern; performing copy processing on the auxiliary layer pattern according to the arrangement information, and forming an auxiliary layer pattern set covering all target unit regions; performing Boolean operation on the auxiliary layer pattern set and global metal lines on the same layer, and generating an identification layer; when the identification layer is empty, it is determined that the to-be-detected metal lines meet the design rule spacing requirements; and when the identification layer is not empty, a spacing violation region indicated by the identification layer is output. The application realizes efficient and accurate spacing violation detection, and improves the automation degree and reliability of design rule checking.

This invention discloses a method for designing a radiation-resistant test chip to evaluate various single-event effects, comprising: design data preparation; chip placement and routing: constructing test chain circuits based on the design data, placing and routing each test chain circuit, exporting placement and routing data after passing preliminary design rule checks, and extracting parasitic parameter files based on the placement and routing data; static timing analysis: performing timing analysis based on the current placement and routing data and parasitic parameter files to determine if there are timing violations. If so, return to the previous step for redeposition and routing; otherwise, proceed to the next step; physical verification: using physical verification tools to perform DRC design rule checks and LVS comparisons. If errors are found, return for redeposition and routing; otherwise, proceed to the next step; formal verification: determining whether the logical functions of the netlist files before and after placement and routing are completely equivalent. If not, return for redeposition and routing; if equivalent, the design ends.