133 results about "Design rule checking" patented technology

The invention discloses a digital back-end full-process script design method, and relates to the field of digital integrated circuit design, and the method comprises the steps: receiving an RTL behavior level netlist, a process library file and a constraint file as input, and generating a library configuration file valeeb.tcl; a gate-level netlist and a corresponding comprehensive report are generated by using a library configuration file valerib.tcl; performing logic synthesis according to the behavior level netlist and the make syn to generate a gate level netlist, and generating layout and wiring data through make out; according to the layout and wiring data, antenna inspection is carried out through a make ant command, design rule inspection is carried out through a make drc command, and comparison inspection of a generated layout and a schematic diagram is carried out through a make lvs command; performing power consumption analysis according to the layout and wiring data; and performing IR analysis according to the parasitic parameters. Aiming at the problem that the chip digital back-end design process is low in efficiency in the prior art, the design efficiency is improved.

The invention relates to an application method of a GPU (Graphics Processing Unit) in design rule inspection in the field of integrated circuits, in particular to a layout design rule inspection method, system and equipment, a medium and a product. The layout design rule checking method comprises the following steps: inputting initial layout data, analyzing a design rule checking task to be executed, and marking the priority and complexity level of the task; the method comprises the following steps: dividing layout data into a plurality of data blocks according to regions on the basis of regional characteristics of the layout data, distributing tasks and corresponding data blocks to a GPU computing core according to task priorities and complexity levels, and distributing new data blocks according to the overall load condition of the GPU computing core after the GPU computing core completes data block processing, and repeating the steps until all tasks are executed, and outputting a layout design rule check result. The system, the computer equipment, the computer readable storage medium and the computer program product have the same beneficial effects as the layout design rule checking method.

The invention discloses an EDA design rule checking method and system based on a decision tree algorithm. According to the method, geometric, topological and other features in design layout are extracted, a decision tree model is trained based on the features, and rule violation terms in design are automatically identified and judged. Compared with a traditional DRC method based on a hard coding rule, automation and intellectualization of the checking process are achieved through the machine learning technology, and the method can adapt to complex rule sets and large-scale layout design. According to the method, the inspection speed is increased, meanwhile, high accuracy is kept, the requirement for manual intervention is reduced, the design period is remarkably shortened, and the method has wide industrial application value and market prospects.

The invention discloses a quantum chip design process DRC detection method, device and equipment and a storage medium, and relates to the technical field of quantum computing, and the method comprises the steps: building a distributed learning framework, and carrying out the initialization of a design rule check model on the distributed learning framework, and obtaining a to-be-trained DRC detection model; obtaining model updating parameters provided by each chip designer, and carrying out aggregation processing on the model updating parameters to obtain global model parameters; the model updating parameters are data obtained by training a to-be-trained DRC detection model on a distributed learning framework locally by each chip design party by using local chip design data; and sending the global model parameter to each chip design party, so that each chip design party detects the quantum chip design process by using a target DRC detection model obtained by updating the local DRC detection model based on the global model parameter to obtain a DRC detection result. Therefore, the design rule checking efficiency of the layout can be improved.

The invention provides a design rule checking method and device based on a multi-modal large model, a terminal, a medium and a product. The method comprises the following steps: acquiring a to-be-analyzed multi-modal DRC rule file; generating a JSON code corresponding to the DRC rule file by utilizing a visual language model according to a preset JSON code format; and converting the JSON code into a corresponding DRC code by using a pre-constructed knowledge base, and carrying out conflict detection on the JSON code through a large language model to obtain a corresponding conflict detection result. According to the method and the device, the multi-modal DRC rule file can be processed, the rule file analysis efficiency is relatively high, and the conflict detection efficiency and the accuracy are relatively high.

The invention discloses a design rule checking method and related equipment, and the method comprises the steps: obtaining a design rule needed by wiring, and carrying out the analysis of the design rule, and obtaining an analyzed design rule; in the wiring process, obtaining each unit element in a metal wire path, and obtaining a shape coordinate, corresponding to each unit element, in the three-dimensional wire rail grid coordinate; according to the analyzed design rule, performing a first processing operation on a shape represented by each shape coordinate, performing prediction according to a processing result of the first processing operation, and according to the analyzed design rule, determining a related violation condition and avoiding the related violation condition; after wiring is completed, each actual unit element in each actual metal wire path in all wiring is obtained, and actual shape coordinates of each actual unit element are obtained; and according to the analyzed design rule, carrying out second processing operation on the actual shape represented by each actual shape coordinate, and determining an inspection result of violation or not.

The invention provides a development method of a heterogeneous integrated PCB (Printed Circuit Board) device library based on a silicon-based CMOS (Complementary Metal Oxide Semiconductor) under Cadence Virtuoso. The development method comprises the following steps: S1, compiling a tecfile.tf file, a display.drf file and a CMOS. Layermap file based on CMOS process information; s2, creating a heterogeneous integration library; s3, in the heterogeneous integrated library, creating a view symbol corresponding to the device according to the type of the device, and setting a CDF parameter attribute of the corresponding device according to a parameter file of the device; s4, creating a callback.il file of a callback function of the device, and carrying out abnormal value detection; s5, creating a layout Pcell of the device; 6, developing a design rule check file based on an interconnection process between the CMOS device and the PCB device by using a skill language; by means of the method, the application range of the PDK is widened, and heterogeneous integration of the silicon-based CMOS technology and the PCB library is completed; and a method for checking the design rule of the interconnection process between the CMOS device and the PCB device is provided, so that the PDK can be used for drawing and developing a board-level circuit, and the limitation of development under different platforms is broken through.

The embodiment of the invention provides a chip layout image processing method and device, electronic equipment and a storage medium, and the method comprises the steps: determining a basic structure type corresponding to a target graph according to the line segment position information in an obtained chip layout image; and determining a refined structure type corresponding to the target graph according to the line segment position information and the line segment angle information. And performing rule inspection on the target graph based on standard structure parameters preset for the refined structure type. The defect that only a graph parallel to the transverse axis direction or the longitudinal axis direction of a two-dimensional rectangular plane coordinate system or a graph with a specific bevel edge angle can be recognized at the present stage is effectively overcome and solved, and then the inspection precision and the inspection efficiency of design rule inspection or mask rule inspection are remarkably improved. The practicability and reliability of the rule checking process and the subsequent image adjusting process for the target graph are improved to a certain extent, so that the performance and the yield of the finally produced chip are powerfully guaranteed.

The invention relates to a circuit testability-oriented design rule checking method and device and a storage medium, and the method comprises the steps: calculating simulation values of all time sequence elements in a circuit netlist under different signal excitation scene information; acquiring a clock signal corresponding to each time sequence element, and determining a driving clock of each time sequence element based on the simulation value and the clock signal; under the driving clock, according to the judgment result of whether the simulation values of the time sequence elements are constant values or not, binding elements with constant output port values are determined from all the time sequence elements, and the time sequence elements except the binding elements are determined as elements to be detected; based on the scanning test rule and the violation level, performing rule inspection on the to-be-inspected element to obtain a violation element; generating a violation result based on the binding element and / or the violation element; and if the binding element and the violation element are not detected, generating an inspection passing result. According to the invention, efficient and customizable design defect detection is realized.

According to the OPC detection and early warning method for the layout graph exceeding the process capability problem, when DRC check is completed and an error is reported, the following detection is carried out: a graph at an error reporting position of design rule check is marked and is used as a graph with a large risk class; and performing regular classification on the risk large-class graphs according to the graph features to divide the risk large-class graphs into first-class graphs and second-class graphs. The first-class graphs are high-risk graphs exceeding the process capability, and when the first-class graphs exist, the first-class graphs are fed back to the layout design end. The second type of graphs are potential risk graphs, when the second type of graphs exist, second screening is carried out on the second type of graphs, and the second screening comprises the step of carrying out local OPC correction to obtain the first layout layer. And adopting an OPC AEI model to carry out local OPC to judge whether a defect risk graph exists or not, and feeding back the defect risk graph to a layout design end when the defect risk graph exists. According to the method and the device, the defect problem caused by the problem layout graph exceeding the process capability can be quickly and comprehensively screened, so that the publishing efficiency can be improved.

The invention discloses an automatic layout method of a filter chip layout and computer equipment. The method comprises the following steps: reading circuit netlist information of a filter; searching a shortest signal path between input and output of the circuit as a main path, and extracting all circuit elements on the main path; performing initial layout on elements on the main path, and storing coordinates of the elements in a coordinate dictionary; an improved force steering algorithm is adopted to carry out layout on the remaining elements, and coordinates of the elements are stored in a coordinate dictionary; judging whether geometric overlap exists among the elements, if yes, eliminating the geometric overlap through adjustment, and meanwhile, ensuring that the connection relationship of the elements corresponds to the netlist; adding an input / output port and adding a scribing channel at the edge of the chip; and performing design rule check and comparison check of the layout and the schematic diagram, if the check is passed, outputting the layout, otherwise, returning to perform overlap detection and adjustment. The design efficiency can be improved, human errors are reduced, and the circuit performance is optimized.

The invention discloses an analog integrated circuit wiring method and system, electronic equipment and a storage medium, and the method comprises the steps: obtaining a preset net, and generating a minimum spanning tree according to the preset net; wherein the minimum spanning tree comprises a plurality of preset pin areas; determining pin priority data corresponding to the preset pin area according to a preset sorting mechanism; wherein the preset sorting mechanism is determined through a Manhattan distance algorithm; performing wiring planning through a mode wiring algorithm according to the pin priority data and the minimum spanning tree to obtain preset wiring data; performing design rule inspection on the preset wiring data to obtain an inspection result; and when it is determined that the inspection result is passed, generating a target wiring file according to preset wiring data. According to the embodiment of the invention, the wiring efficiency and quality of the analog integrated circuit can be effectively improved, so that the performance and reliability of the analog integrated circuit are improved. The circuit can be widely applied to the technical field of integrated circuits.

The invention discloses an STDCell pin adaptive selection method and related equipment, and the method comprises the steps: carrying out the preprocessing operation of basic design rule check data, so as to obtain the rule data needed by a DRC rule engine through calculation; reading a user chip design file to perform pre-design operation to form pre-design data; generating a 3D space candidate VIA access point coordinate set of the metal layer where the pin is located, and generating a three-dimensional DRC evaluation value corresponding to each candidate coordinate; according to a VIA generation rule, pre-generated VIA information and pin physical information, performing physical information matching operation based on geometric operation to generate combined data with a three-dimensional DRC evaluation value; according to the three-dimensional DRC evaluation value in the combined data, performing optimization operation by adopting a target optimal algorithm so as to determine optimal combined data and a sequence thereof; and performing wiring access operation based on the optimal combination data and the sequence thereof to generate constrained six-degree-of-freedom wiring information.

Design rule violations (“DRVs”) may be predicted using a design rule check (“DRC”) density map during a physical synthesis operation prior to executing a routing operation.

The invention discloses an integrated circuit layout verification method and device, and belongs to the technical field of integrated circuit design, and the method comprises the steps: obtaining the arrangement information of a selected target unit from an integrated circuit layout; performing external expansion processing on the to-be-detected metal wire of the target unit according to a design rule spacing requirement to generate an auxiliary layer pattern; copying the auxiliary layer graph according to the arrangement information to form an auxiliary layer graph set covering all target unit areas; performing Boolean operation on the auxiliary layer graph set and the global metal wire on the same layer to generate an identification layer; when the identification layer is empty, determining that the to-be-detected metal wire meets the design rule spacing requirement; and when the identification layer is not empty, outputting the interval violation area indicated by the identification layer. According to the method and the device, efficient and accurate interval violation detection is realized, and the automation degree and the reliability of design rule inspection are improved.

The invention belongs to the technical field of semiconductor design automation, and provides a design rule checking method for a chip layout and related equipment. The method comprises the following steps: acquiring a to-be-processed chip layout comprising at least one graphic layer; a process rule interval of a target graph layer in the chip layout and factor weights of the target graph layer on a plurality of process risk factors are obtained, the process rule interval is the minimum graph interval meeting process production, and the factor weights are used for representing the interference degree of the corresponding process risk factors on chip manufacturing; calling a conflict quantification model to calculate a conflict risk value of each adjacent graph in the target graph layer based on the process rule spacing, the factor weight and the actual spacing of each adjacent graph in the target graph layer; and based on the conflict risk value, carrying out design rule check on the target graph layer. Through the technical scheme provided by the invention, the precision of chip layout design verification can be improved.

Embodiments of the present disclosure provide a system for automatically generating design rule checking (DRC) code for a design rule. The DRC code is generated using a first large-language model (LLM) agent and a second LLM agent. The first LLM agent generates a plurality of design rule conditions based on a multi-modal description of the design rule. The second LLM agent generates executable DRC code based on the plurality of design rule conditions. The executable DRC code is executed on example layouts to generate corresponding outputs. The executable DRC code is evaluated by comparing the outputs with corresponding reference outputs. The executable DRC code is iteratively regenerated based on the evaluation, where the evaluation includes providing a performance report to the first LLM agent and / or to the second LLM agent.

The invention discloses a communication chip layout defect automatic identification method based on artificial intelligence. The method comprises the following steps: analyzing a communication chip layout design file; executing design rule check and parameter extraction; an improved NCA model is constructed, state initialization is completed, and a fast-scale update parameter set and a slow-scale update parameter set are generated; executing iterative evolution based on the fast-scale updating parameter set and the slow-scale updating parameter set, and outputting an evolution intermediate representation set; conditional modulation is carried out on an update function of the improved NCA model; constructing a graph neural network topology consistency verification mechanism, and generating a verified defect region set; and performing defect discrimination and labeling, and outputting a defect type set, a defect distribution heat map and a defect coordinate set. According to the method, the communication chip layout defect identification accuracy is improved, and the cross-layer connectivity verification capability is enhanced.

This disclosure provides a layout test case generation method, apparatus, and related equipment. The layout test cases are used for design rule checking of semiconductor devices. The method includes: converting the design rules of the semiconductor device into a first numerical vector using a first encoding method; converting the first layout test cases into a second numerical vector using a second encoding method; calling a pre-trained neural network model, and using the neural network model to output a second layout test case based on the first and second numerical vectors; wherein the first and second numerical vectors are one-dimensional numerical sequences including multiple values.

The invention discloses a graph scaling method and a design rule checking method of an integrated circuit. The graph zooming method for the electronic design comprises the steps that vertex information and zooming parameters of a polygon are obtained, and the zooming parameters comprise the vertical distance between the edge of the zoomed polygon and the corresponding edge of an original polygon; finding a parallel line corresponding to each edge of the polygon according to the vertex information and the scaling parameter; and searching corresponding intersection points of the parallel lines according to a boundary sequence of new boundaries of the polygon defined by the parallel lines to obtain new vertex information, and obtaining the zoomed polygon. According to the invention, the graph zooming method with high efficiency and high precision can be provided.

The present invention belongs to the field of electronic design automation technology, and specifically relates to a multi-module collaborative electronic product design rule checking system, comprising a bill of materials (BOM) processing module, a rule processing module, and a core processing module. The core processing module receives a standardized bill of materials (BOM) output by the BOM processing module and reads a corresponding rule directory from the rule processing module based on the attributes of the standardized BOM. The core processing module then performs a design rule check on the schematic diagram based on the read rule directory and the standardized BOM, and outputs a check report. This invention improves design efficiency and quality while shortening lead times and reducing R&D costs.

A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.

Integrated circuit (IC) design based on timing slack according to an example includes accessing physical design data for an IC layout, wherein the physical design data comprises a netlist including active metal shapes of a metal shapes infrastructure forming signal path nets connecting different parts of the IC layout. Timing-based design rule checking of the physical design data is performed to identify slack stealing information for the signal path nets. Shape-based density design rule checking of the metal shapes infrastructure is performed, based on the slack stealing information, to perform fill insertion of metal fill shapes to satisfy density requirements in the IC layout.

The invention relates to a chip layout design method, which belongs to the technical field of semiconductor laser design, solves the technical problems of low efficiency and high possibility of errors in chip design, and comprises the steps of self-adaptive adjustment of design parameters, modular layout design, combination of automation and manual intervention and wiring strategy optimization. The method comprises the steps of multi-objective balance of power consumption, performance and area optimization, real-time integration of design rule check DRC and circuit consistency check LVS, design optimization aiming at an advanced process, and functional module expansion. The design method is used for chip layout design, especially layout design of advanced process nodes.

The present invention provides a device system for manufacturing a semiconductor, comprising: an unverified body layout representing a semiconductor device, the system configured to generate: a feature extraction module configured to extract a body feature at least partially containing the unverified body layout; and a design rule (DR) execution module including a design rule check (DRC) module and a layout modifier (LDM) module, the DRC module configured to check whether the subject features conform to the corresponding design rules in the settings and identify which design rules are violated and the corresponding subject features violating the DR, the LDM module is configured to attempt to reduce DR violations by modifying subject features that violate the DR, thereby producing a validated subject layout; the DRC module is based on the first neural network; and the LDM module is based on the second neural network.

To provide an agile prototyping system and method based on meta learning.SOLUTION: A hardware design flow includes: usually preparing system specifications 110 as a target and requirement such as clock frequency, latency, power consumption, accuracy, and footprints; designing (120) computing architecture to meet the specifications; describing (130) its functional design and logic design onto register-transistor logic (RTL); synthesizing (140) the RTL design to gate logics; physically designing (150) the gate logics so as to be placed onto a plane; conducting (160) design rule check (DRC) and other physical verification; fabricating a chiplet (170); packaging and testing (180) the chiplet; and deploying the chiplet as a custom computing chip 190.SELECTED DRAWING: Figure 1

This invention discloses a tank design method, apparatus, equipment, and medium based on design rule checking. The method is applied to the digital and parametric intelligent design of tank equipment, including: generating a first design file for the tank to be designed based on received first tank parameters; performing interference checks based on constructed design rules to identify first violation information in the first design file that does not meet the interference check conditions; adjusting the first tank parameters according to the first violation marker to generate second tank parameters; determining the target design file corresponding to the tank to be designed based on the second tank parameters; and performing detailed design rule checks during the design file implementation process. The technical solution of this invention can perform interference checks on the generated design file, automatically identify existing violations, eliminate the need for manual calculations, reduce errors that may propagate downstream during the design process, lower design costs associated with repeated modifications, meet practical application needs, and improve overall efficiency.

This application discloses a computational system for implementing yield improvement tools. It extracts cell characteristics from a physical layout design for integrated circuits, determines the location of empty regions in the physical layout design, and applies electrical design rules for manufacturing integrated circuits to the extracted characteristics to identify cells in the physical layout design that will violate the electrical design rules. The computational system can select fill cells for empty regions based at least in part on the extracted characteristics of cells adjacent to empty regions and the electrical design rules, and insert the selected fill cells into the empty regions of the physical design layout. The computational system can perform a design rule checking operation that applies the electrical design rules to the physical design layout where the selected fill cells have been inserted.

The application relates to a file generation method and device, a storage medium and electronic equipment, and relates to the technical field of chip electronic design automation. The method comprises the following steps: obtaining a design rule document to be parsed, performing structural analysis on the design rule document, and obtaining layer mapping information, metal layer configuration information and design rule information of the design rule document; generating layer definition code, a design rule framework and design rule code of the design rule document based on the structural data files corresponding to the layer mapping information, the metal layer configuration information and the design rule information; and generating a verification rule file corresponding to the design rule document according to the layer definition code, the design rule framework and the design rule code. By applying the technical solution of the application, the generation efficiency of the design rule check file is improved, syntax errors in the manual writing process are avoided, and the accuracy of the verification rule file is improved.

The invention relates to a microstrip network layout optimization method based on Fourier series, and belongs to the technical field of radio frequency circuit design. The method aims at solving the problems of topology dependence, boundary discontinuity and low efficiency caused by sharp increase of optimization parameters along with the area in a traditional rectangular spliced microstrip network. The core of the technical scheme is that a microstrip network boundary is modeled into a plane closed curve, the curve is represented through Fourier series decomposition, and a Fourier coefficient is optimized by taking circuit performance as a target drive, so that a microstrip layout with any shape and a continuous and smooth boundary is generated. According to the method, automatic design rule checking and port adding processes are integrated, and finally electromagnetic simulation iteration is carried out until a design target is met. The method can break through the limitation of the traditional topology, effectively improves the electromagnetic performance and design efficiency, and is widely applied to the microstrip network design of broadband matching, multi-band matching, harmonic control and the like.