The present invention relates to a circuit
layout technique for automatically generating analog and
hybrid signals, and in particular, to a modular MOS
transistor layout structure having a
standard cell, and a usage method. The objective of the present invention is to solve the problem of failing to realize automatic
layout generation, placement and routing because existing automatically generated MOS
transistor layouts lack a standard structure and therefore cannot be abutted. The main solution comprises an MOS
transistor layout design for a
standard cell-
modular structure. Each
standard cell includes two pieces of dummy polysilicon, a placement and routing boundary, a power supply rail and a ground rail, and is regular in terms of shape and size, can be abutted to the same type of standard
cell in any direction, and can be recognized by an EDA tool, thereby adapting to the EDA tool and improving the placement efficiency. In addition, further provided in the present invention is a usage method. Automatic placement and routing is performed by means of an EDA tool. First, automatic placement and routing is performed on a circuit consisting of NMOS transistors, so as to form an NMOS module; then, automatic placement and routing is performed on a circuit consisting of PMOS transistors, so as to form a PMOS module; and finally,
automatic routing is performed on a connection relationship between the two modules. Therefore, automatic generation of a circuit structure layout consisting of MOS transistors in analog and
hybrid circuits is realized, thereby improving the layout generation efficiency.