2556 results about "Shared memory" patented technology

A method to share remote DMA (RDMA) pointers to a key-value store among a plurality of clients. The method allocates a shared memory and accesses the key-value store with a key from a client and receives an information from the key-value store. The method further generates a RDMA pointer from the information, maps the key to a location in the shared memory, and generates a RDMA pointer record at the location. The method further stores the RDMA pointer and the key in the RDMA pointer record and shares the RDMA pointer record among the plurality of clients.

The invention relates to the field of natural language understanding in an artificial intelligence technology man-machine dialogue system, in particular to a psychological accompanying dialogue method based on multi-agent collaboration and a storage medium. The psychological accompanying dialogue with individuation, high naturalness and accurate emotion recognition is provided, the user experience is effectively improved, and the psychological support requirement of the user is met. According to the main scheme, the method comprises the steps of performing multi-mode emotion evaluation on user input to obtain user emotion state description; retrieving related dialogue states and external knowledge from a shared memory module according to user questions and user emotional state description; according to the retrieved dialogue state and external knowledge, the strategy planning module generates a reply strategy to obtain a strategy group; the dialogue content generation module calls a corresponding vertical domain agent according to the generated reply strategy to generate specific reply content; and storing the user questions and model replies in the current round into the short-term memory of the shared memory module, and updating the long-term memory. The method is used for AI dialogues.

The invention discloses a real-time interactive digital human system supporting high concurrency and an implementation method thereof, and relates to the technical field of digital human interaction.The system comprises a model instance pool module used for loading the weight of a deep learning model to a shared memory area through the memory mapping technology; the multi-thread scheduling module is used for scheduling user requests by adopting a lock-free queue and a dynamic priority algorithm; the asynchronous pipeline processing module is composed of decoupled micro-services, and the modules are connected in series through asynchronous message queues; the client SDK is used for dynamically switching a rendering mode according to terminal hardware performance and network conditions; the elastic capacity expansion and contraction module is used for monitoring resource loads in real time and automatically adjusting the number of service instances; and the audio and video synchronization calibration module is used for ensuring that the synchronization error of the audio and video frames is lower than a preset threshold value through a timestamp alignment algorithm. According to the scheme, core challenges in a high-concurrency digital human interaction scene can be systematically solved, and innovative support is provided for large-scale real-time application.

The invention discloses a tensor core-based method for accelerating arbitrary precision sparse matrix multiplication and addition operation, which comprises the following steps of: aiming at an architecture of a tensor core on A100 and a programming model thereof, combining program characteristics of deep learning parallel processing sparse matrix, combining an arbitrary precision sparse matrix multiplication and addition operation operator with parallel computing acceleration equipment, and performing parallel computing acceleration on the sparse matrix. The method comprises the following steps: decomposing a general matrix into a sparse matrix in a set format, partitioning the sparse matrix and assigning a corresponding parallel computing hardware unit for the sparse matrix, reducing memory conflicts and access delay by using a shared memory, calling a high-level language API function library to execute loading, computing and storing processes of a computing data volume, and finally performing specification on output data of a function. Therefore, the final result of the random-precision sparse matrix multiplication and addition operation on the parallel computing acceleration equipment is obtained. According to the method, parallel computing resources such as the tensor core on the A100 can be fully utilized, the program calculation amount and the communication overhead are effectively reduced, and the program operation performance is greatly improved.

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and / or an external memory.

The invention discloses a cross-container application fusion switching method of a swan monk system, which comprises the following steps: a system service layer deploys a container application management service, an application framework layer realizes a proxy application manager, when a container application is started, a container side allocates a shared memory and configures authority, the container manager collects metadata to initiate registration, and the application framework layer realizes a proxy application manager; the container application management service converts a memory handle into a texture handle, allocates a unique identifier and triggers a proxy application manager to generate a proxy application, and the proxy application initializes a Vulkan rendering environment; the container side renders an application interface to a shared memory, the proxy application imports texture and constructs a lightweight Vulkan rendering pipeline, and scaling sampling is carried out to generate a thumbnail of the container application; and when the container application exits, the shared memory is released, the container application management service cleans the shared memory reference, triggers and destroys the proxy application, and recycles the texture resources through the reference counter, so that seamless fusion, low-delay switching and efficient resource utilization of the container application in a native application thumbnail form are realized.

The invention discloses an android container rendering optimization method based on cross-domain hard real-time Fen synchronization, which comprises the following steps: by taking a swan-mong system as a host and an android system as a container, creating a hash table, a synchronous thread and a shared memory corresponding to a GPU core when the host is started, acquiring VSync cycle registration callback, transmitting shared memory FD to the container, and finishing shared memory mapping and alignment by the container. Registering a GPU queue to complete callback; when the Android application is started, a container obtains a queue and a physical address of a rendering buffer area, creates a Fen and binds the Fen to the queue, after the queue is submitted, metadata is written into a shared memory to inform a host, after the host receives the metadata, nodes are created and stored in a hash table, and an overtime timer is registered; after the GPU completes the command queue, the container calls back an update state and a verification value to notify the host, and after the host is verified to be valid, the corresponding hash table is updated, the timer is reset, and asynchronous screen loading is triggered; and the host executes buffer area synthesis and submission of the display equipment to finish on-screen, so that the stability of the rendering frame rate is improved, and the reliability of cross-domain synchronization is ensured.

The invention discloses an SDR-oriented heterogeneous task scheduling and transmission system and method.The system comprises a heterogeneous platform composed of an ARM and an FPGA, a dynamic scheduling decision engine is arranged in the ARM and receives a task feature vector and a platform state parameter set as input, and the dynamic scheduling decision engine evaluates income and cost of task allocation to the ARM or the FPGA for execution to make a task allocation decision; the data generated in the task execution process or the execution completion result are interacted and synchronized between the ARM and the FPGA through the heterogeneous shared memory area HSM. The method realizes reduction of signal processing pipeline delay, improvement of data throughput and optimization of system power consumption, and is suitable for communication, electronic countermeasure and other scenes needing high-performance real-time signal processing.

The invention provides an LDPC code parallel GPU decoding method and system, and relates to the technical field of communication, and the method comprises the steps: reading an LDPC code through a CPU; distributing the check matrix parameters to a constant memory space of the GPU, and initializing the constant memory space; allocating a global memory space for the channel information, the decoding hard decision result and the C2V through the GPU; quantizing the channel information into signed character type data; setting a GPU thread block based on the sub-block dimension of the check matrix; performing layered updating on the LDPC code through floating point operation by using intra-frame parallelism; storing the layered information into a shared memory space of the GPU, and initializing the layered information through channel information; iteratively updating the initialized hierarchical information to generate a decoding result of the to-be-transmitted data; transmitting a decoding result to a host memory space of the CPU; and after code word decoding is completed, resource release is carried out.

The invention provides a multi-core heterogeneous system-oriented startup deployment and cooperative processing method, which comprises the following steps of: when the system runs, obtaining startup codes after a master core and a slave core are electrified, respectively obtaining mirror image files of Linux and RTOS (Real Time Operating System) on the basis of synchronous running and storage partition, and running the mirror image files on the master core and the slave core after moving the mirror image files; and after the heterogeneous operating system is loaded, generating an interrupt signal based on inter-core interrupt and a corresponding register through a CLINT module in the main core, and realizing data communication between the main core and each slave core based on the interrupt signal and the shared memory. By means of the method, after the system is powered on, the multiple cores can synchronously run the starting codes, and time delay and uncertainty possibly caused by one-by-one starting of the single cores are avoided; communication and data transmission among multiple cores are realized through interruption and memory sharing, the synchronism and consistency of data are ensured, and misjudgment and decision errors caused by data delay and inconsistency are avoided, so that the real-time performance of the system is remarkably improved.

The invention discloses a video multi-target intelligent detection method and system based on mercuric chloride hardware. A hardware decoding module decodes an input video stream in real time, generates video frames and stores the video frames in a shared memory queue. And inputting the video frame into the YOLOv5 model converted by the mercuric chloride OMG tool, pre-loading a plurality of model instances into a memory by using an ACL interface of the mercuric chloride NPU, calling different model instances through a polling scheduling mechanism, and outputting structured data comprising a multi-target detection frame, a category label and confidence. And carrying out non-maximum suppression processing on the reasoning result, and judging whether the target is in an alarm monitoring area or not by adopting a central point detection method. According to the invention, real-time multi-target intelligent detection of the input video stream can be realized. And the decoded video frames are stored in a shared memory queue, so that efficient data transmission and processing are realized. The multi-model parallel reasoning improves the detection precision, and is suitable for the application scene of real-time video multi-target intelligent detection.

The invention relates to the field of satellite navigation anti-interference and the technical field of computers, and discloses a multi-processor core communication method and device, electronic equipment and a storage medium, and the method comprises the steps that a second processor core writes target information into a shared memory, and obtains a first idle channel number; the second processor obtains a first interrupt signal based on an interrupt trigger register corresponding to the first idle channel number; the first processor core reads target information in a shared memory according to the first interrupt signal; the first processor core processes the target information to obtain a processing result, and writes the processing result into the shared memory to obtain a second idle channel number; the first processor core obtains a second interrupt signal based on an interrupt trigger register corresponding to the second idle channel number; and the second processor core reads the processing result in the shared memory according to the second interrupt signal, and writes the processing result into the cache region. The multi-processor core communication method is suitable for different operating systems and is high in transportability.

The invention discloses a container application on-screen method based on texture full-process optimization, which comprises the following steps: taking a swan-gap system as a host and an Android system as a container, distributing a plurality of first buffers by the host, screening out a first texture format by the container, writing original textures of the format generated by rendering into frame buffers, identifying a dirty area of the rendered textures, and displaying the original textures in the frame buffers; packaging the texture data of the region, storing the packaged texture data into a shared memory, transmitting a file descriptor FD to a host, binding an idle first buffer setting priority, a state, a generation timestamp and a texture data pointer at the same time, and obtaining the texture data by the host through the FD; the host establishes a fixed thread task pool, executes multiple tasks in parallel to obtain on-screen texture data, and then updates the state of the first buffer and a texture data pointer; and finally, the host queries the first buffer with the processed state, reads the texture data after sorting according to the priorities and the generation timestamps to finish on-screen, and resets the state of the first buffer to be idle, so that the on-screen delay is effectively reduced, and the actual frame rate of the Android application is improved.

The invention discloses an information processing method and device, electronic equipment and a storage medium, and is applied to the field of information processing. The information processing method comprises the steps that a first utilization rate is determined in combination with a data flow between a memory and a shared memory when a processor executes a general matrix multiplication operator, and the first utilization rate is used for indicating performance evaluation of the general matrix multiplication operator at a processor level; determining a second utilization rate in combination with a data stream between a shared memory and a register file in a single computing unit when the processor executes the general matrix multiplication operator, the second utilization rate being used for indicating performance evaluation of the general matrix multiplication operator at the computing unit level; and based on the smaller one of the first utilization rate and the second utilization rate, determining the theoretical performance of the processor when executing the universal matrix multiplication operator. At present, only chip-level performance evaluation is considered in performance evaluation of a GEMM operator, and double-level-dimension theoretical performance evaluation is provided, so that the evaluation result is more accurate.

The invention discloses a method, a product and equipment for sharing a file system by multiple hosts and a storage medium, and relates to the technical field of computers, which comprises the following steps: configuring a shared memory device as a character device, directly mapping to a user mode virtual address space, bypassing a kernel page cache, and directly reading and writing a physical address of the shared memory. A shared memory is divided into a super block area, a metadata area, a log area and a data area during formatting, all hosts perform unified operation through the shared metadata area, stand-alone cache interference is avoided, a hidden metadata file is created to map a non-data area during mounting, a log item is scanned to reconstruct a directory file structure, and the mounting efficiency is improved. All hosts generate a directory file structure completely consistent with the shared memory through log replay, the problem of data consistency caused by a cache strategy in a traditional multi-host file system is solved, and the effects that multiple hosts share a unified memory view, operation is real-time and synchronous, and data access delay is reduced are achieved.

The invention discloses a cross-host memory sharing method, system and device and a medium, the memory sharing system comprises a master node and a plurality of slave nodes, the memory sharing method is applied to the master node, and the method comprises the steps that a memory application request of a target slave node is received; applying for a target memory in a target memory sharing area according to a memory size requirement corresponding to the request, feeding back memory information of the target memory to a target slave node, so that the target slave node judges a corresponding memory type according to the memory information, and if a process corresponding to the target slave node executes a memory mapping method, sending the target memory to the target slave node. If yes, the target memory can be mapped to the proceeding virtual address space according to the target type and the offset corresponding to the target memory, so that the process can use the distributed target memory. Therefore, it can be guaranteed that when one node writes the memory, other nodes cannot synchronously write the memory, and then the data consistency of the shared memory accessed by multiple hosts is guaranteed.

The invention relates to the technical field of artificial intelligence chips, and provides a convolution operation method and device, electronic equipment and a storage medium, and the method comprises the steps: traversing convolution kernel elements, and determining a current to-be-loaded data block based on the shape of a target data block and the coordinates of the traversed current convolution kernel element block; based on the current to-be-loaded data block, determining a to-be-covered data block and a newly-added data block, and loading the newly-added data block into the shared memory; based on the initial position, reading the input data block from the shared memory, applying the input data block and the current convolution kernel element block, performing matrix multiply-accumulate operation, and accumulating an operation result to an output result; and determining a convolution operation result based on an output result obtained by accumulation after traversal is completed. According to the method and the device, only the newly added data blocks are loaded into the shared memory, so that repeated data loading can be avoided, the data volume loaded each time is reduced, and the memory bandwidth is saved.

The invention discloses an intelligent monitoring method and system for the construction progress of a building decoration curtain wall. The method comprises the steps that multi-source construction data of a construction site are collected through Internet of Things equipment and a high-definition camera; constructing a multi-dimensional tensor model and extracting data association features by applying a local reversible mapping algorithm to generate a standardized feature data set; performing parallel computing through shared memory hierarchical process mapping by utilizing the standardized feature data set, and outputting a project progress state evaluation result; constructing a decision diagram based on the project progress state evaluation result, and generating a construction progress deviation report; predicting a construction progress trend by adopting a sample optimal private regression algorithm and generating an optimization scheme; and visually displaying the construction progress prediction report and carrying out early warning. According to the invention, the problems of low data integration efficiency, delayed decision response and weak multi-dimensional data association analysis capability of traditional curtain wall construction monitoring are solved, and intelligent and efficient monitoring of the construction progress of the building decoration curtain wall is realized.

The embodiment of the invention provides a network card equipment switching method and device based on a bonding mode, and relates to the technical field of network card equipment. The method comprises the following steps: in response to a switching operation of network card equipment based on a bonding mode, generating a switching operation message, and transmitting the switching operation message to a preset callback interface; calling a switching operation message from a preset callback interface based on the remote direct memory access driving module; and based on the remote direct memory access driving module, switching the current data information of the first network card device to the second network card device through the shared memory according to the switching operation message, and executing the current data information in the second network card device. By adopting the technical scheme, when one network card device has only one port, a communication mode of remote direct memory access with other devices can be carried out, so that the stability of data transmission is improved.

The embodiment of the invention relates to the technical field of data processing, in particular to a data processing system and method, a product, equipment and a storage medium, and aims to improve the data transmission speed between a central processing unit and a graphics processing unit. The data processing system comprises a central processing unit cluster which comprises a plurality of central processing unit cores and a first cluster sharing cache; the graphics processor cluster comprises a plurality of graphics processor cores and a second cluster shared cache; a shared memory; each central processing unit core in the central processing unit cluster is provided with a secondary private cache; each graphics processor core in the graphics processor cluster is provided with a first-level private cache; and writing corresponding data into the second cluster shared cache by any central processing unit core in the central processing unit cluster under the condition that an address contained in a received data writing request is a graphics processor address.

The invention discloses a visual Transform accelerator implementation method and system, and belongs to the technical field of computer vision, the visual Transform accelerator is implemented based on an annular reconfigurable architecture, and the annular reconfigurable architecture forms an annular topology by a plurality of Transform acceleration cores, a storage unit and a shared memory through an AXI bus; the method comprises the following steps: constructing a Transform calculation unit by adopting a pipeline architecture, wherein the Transform calculation unit comprises a multi-head attention unit and a multi-layer perceptron unit; and the multi-head attention unit and the multi-layer perceptron unit multiplex a matrix multiplication subunit and a layer normalization unit to realize normalization and multiplication and addition operation of data. According to the method, the execution speed of the visual Transform model can be greatly improved, more innovation space can be provided for developers, and the computer vision technology is promoted to be developed to wider application fields.

The invention provides a DCU-based high-performance sparse stiffness matrix vector multiplication method, which comprises the following steps of: according to a sparse stiffness matrix, dividing a non-zero element into a plurality of calculation unit blocks by rows, pre-loading non-zero element data to an L1 shared memory or a register file through an on-chip shared memory controller of the DCU, a high-bandwidth crossbar switch of the DCU is used for realizing data copying and transmission; starting multi-row fusion execution for a short row of which the row non-zero element is lower than a DCU single-instruction multi-data width threshold value; constructing a wavefront scheduler based on a DCU asynchronous computing engine: binding an independent instruction cache region for each wavefront, and loading a multiply-add operation instruction set in advance through a prefetch instruction queue; a calculation unit state register is established, and when a wavefront scheduler ready signal is triggered, a scalar unit of the DCU is activated to execute calculation; and realizing cross-thread block reduction by adopting a DCU atomic operation accelerator. According to the method, the calculation throughput and the memory bandwidth utilization rate of large-scale structural mechanics stiffness matrix vector multiplication are effectively improved.

The invention discloses a micro-kernel Hypervisor-based virtual machine cross-operating system communication method, which comprises the following steps of: creating virtual machines which independently run in respective operating system environments by a micro-kernel Hypervisor, then constructing a shared memory between two virtual machines with communication requirements, respectively initializing virtual machine shared equipment by the two virtual machines, and storing the virtual machine shared equipment in the shared memory; according to the cross-operating-system communication method, the shared memory is mapped to a virtual address of the shared memory, when one virtual machine needs to transmit data to the opposite side, communication is initiated to write the data into the shared memory, and the virtual machine receiving the data reads the data from the shared memory, so that cross-operating-system communication of the virtual machines is realized. Based on the shared memory technology, the communication process of the shared memory and the virtual machines is managed by using the microkernel Hypervisor, and cross-operating system communication between the virtual machines is realized.

The invention provides a multi-core AMP architecture inter-core communication method and system based on a high-security embedded real-time operating system, and the method comprises the steps: respectively operating an authentication version of a Quhua high-security embedded real-time operating system on an AMP heterogeneous multi-core platform, and guaranteeing the real-time performance of a task while providing functional security. And two driving interface mechanisms of IPC Not ify and IPC RPMsg are provided, so that the real-time performance of inter-core communication of the multi-core AMP architecture is improved. The IPC Not ify transmits messages based on the HW mailbox of the HW fifo and interrupts the receiving of core messages, and has low time delay; and a heterogeneous multi-core synchronization function is supported, so that a user does not need to concern the starting sequence of the AMP heterogeneous multi-core system and mainly focuses on development of inter-core communication application programs of the user. The IPC RPMsg provides a two-way communication link based on a channel between the cores, and supports large data volume communication interaction between the cores. A universal shared memory area is configured, and a spinlock technology is adopted to synchronize multi-core operation and prevent multi-core access conflicts. A method for sharing the same physical device by multiple cores is provided, and the problem of insufficient device hardware resources is solved.

The present application belongs to the technical field of data processing and relates to a network message processing method and apparatus, and a computer device and a storage medium. The method comprises: on the basis of a received target network message, acquiring a target memory block from a pre-constructed shared memory pool, so as to generate a message memory; on the basis of a network-interface-card driver, performing first identification processing on the target network message, so as to obtain a target network message descriptor; on the basis of the target network message descriptor, performing second identification processing on the message memory, so as to obtain a first socket buffer; and performing parsing processing on the first socket buffer by means of a network protocol stack, and on the basis of a parsing processing result, reading network message data from a virtual memory corresponding to the message memory, so as to complete the processing of the network message. In the present application, on the basis of a constructed shared memory pool, zero-copy network packet reception can be realized during network message processing, thereby avoiding performance loss caused by the memory copy of messages.

The invention discloses a network card data local preprocessing system fused with edge computing, and relates to the technical field of edge computing and artificial intelligence collaborative optimization. Comprising an edge computing unit, a hierarchical collaborative architecture, a model hot switching and generative fragmentation module, an intention recognition and adaptive scheduling module, a delay energy consumption optimization scheduling module, a CXL zero-copy sharing module, an edge computing unit integrated processor, an FPGA or ASIC and a neuromorphic computing unit. According to the method, an FPGA, an ASIC and a neuromorphic computing unit are integrated in an intelligent network card, microsecond-level dynamic connection reconfiguration and adaptive generative model fragmentation execution are realized through a reconfigurable Mesh interconnection matrix, an attention layer and a feed-forward layer of a Transform class model are fragmented and allocated to different computing units for parallel execution, and cross-card streamlined processing is realized in cooperation with a zero-copy shared memory. And the intention recognition module is deeply coupled with the model hot switching module, so that dynamic model switching and fragmentation strategy optimization based on service priorities and system loads are realized.

The invention relates to the field of edge computing and Internet of Things, and discloses a miniature data transaction device which comprises an edge computing unit used for executing a centralized or decentralized matchmaking algorithm and a transaction protocol; the multi-dimensional detection module comprises a compliance detection unit, a safety detection unit, a quality evaluation unit and a scene applicability evaluation unit; the hardware accelerator is used for accelerating a detection task and encryption operation; the communication module supports multi-protocol data transmission; the storage unit is used for caching transaction data and intelligent contract codes; the power management unit is used for controlling the total power consumption of the equipment, and the edge computing unit comprises a hierarchical trusted execution environment architecture consisting of a safe enclave and a general computing unit. According to the method, a hardware isolation architecture of the secure enclave and the general computing unit is adopted, and the dynamic key encryption shared memory technology is combined, so that the effects of privacy computing and efficient matching parallel execution are achieved.

The invention provides a sparse matrix vector multiplication parallel optimization method and system based on a CSR storage format, and relates to the technical field of high-performance parallel computing, and the method comprises the steps: obtaining sparse matrix data stored in the CSR format; splitting and integrating the sparse matrix by adopting a row grouping method, dividing rows with similar non-zero element numbers into the same group, and configuring computing resources for each group; the method comprises the following steps: firstly, pre-loading sparse matrix data in each group, defining a texture memory, and pre-loading the sparse matrix data into the texture memory; an independent kernel is set for each group to execute SpMV calculation of all rows in each group, and non-zero elements of sparse matrix data and corresponding vector data are preloaded into a shared memory in the calculation execution process of the kernel; and the kernel executes SpMV calculation by adopting a hybrid static-dynamic thread scheduling method until all rows are calculated, and a final result is obtained.

The invention provides a data interaction method and device based on a shared memory, virtual electronic equipment and a storage medium, and the method comprises the steps: responding to a detected packet sending request of a first application for a first protocol stack of first virtual network equipment, and calling a first packet sending function; encapsulating the to-be-sent data into a first data packet based on the first packet sending function; obtaining a storage address of the first data packet, and mapping the storage address in a mode of directly accessing a mapping interface by a memory to obtain a mapped physical address; and filling the physical address into a corresponding position of the descriptor of the first virtual network equipment, and updating the position of a tail pointer of the descriptor. The RC and the EP are registered as the virtual network card through the network driving technology, so that the communication function can be realized through the PCIE slot and by means of the PCIE connecting line, data message transmission can be realized without the aid of peripheral equipment such as the network card, the stability of data transmission is improved, and the configuration cost of hardware is saved.

The invention provides a memory resource access method and device, an address translation method and device, electronic equipment and a storage medium. According to the embodiment of the invention, a virtual machine management component can be used for firstly obtaining a direct memory access request of external equipment to a memory resource mounted under a virtual machine; and searching a target physical address corresponding to the target virtual address of the target memory resource from the data processing unit, so that the external equipment accesses the target memory resource by accessing the target physical address. Wherein a physical address translated by the virtual machine management component for the virtual address of the memory resource in advance is stored in the data processing unit, and the data processing unit performs data communication with the virtual machine management component through a communication drive simulated in the virtual machine management component. By adopting the scheme, the congestion of the shared memory resource (IOTLB) of the memory management unit possibly caused by excessive address query can be avoided, the consumption of the shared memory resource is reduced, and the utilization rate of the shared memory resource is improved.