50 results about "Cache hierarchy" patented technology

The invention relates to an apparatus and method for notifying a predictor with data object range information in a pointer. A processor of an aspect includes a cache hierarchy and a memory access unit coupled with the cache hierarchy. The memory access unit performs a demand load based on the Y-bit pointer such that the first one or more cache lines are loaded from the memory into the cache hierarchy. The Y-bit pointer has an X-bit virtual address field and a data object range field in one or more of the bits [Y-1: X]. A data object range field stores values. The processor also includes a prefetch unit coupled with the cache hierarchy. The prefetch unit determines whether to prefetch a second one or more cache lines adjacent to the first one or more cache lines from the memory into the cache hierarchy based at least in part on the value.

A processor of an aspect includes a cache hierarchy and a memory access unit coupled with the cache hierarchy. The memory access unit is to perform a demand load based on a Y-bit pointer to cause a first one or more cache lines to be loaded from memory into the cache hierarchy. The Y-bit pointer has an X-bit virtual address field and a data object extent field in one or more of bits [Y-1:X]. The data object extent field is to store a value. The processor also includes a prefetch unit coupled with the cache hierarchy. The prefetch unit is to determine whether or not to prefetch a second one or more cache lines, adjacent to the first one or more cache lines, from memory into the cache hierarchy based at least in part on the value. In another aspect, the prefetch unit may additionally or alternatively scan code or data for a bit pattern in bits [Y-1:X] to identify likely pointers and prefetch data referenced by such identified pointer's memory addresses. Other processors, methods, systems, and instructions are disclosed.

The invention provides a database concurrency control and memory access optimization method which can be applied to the technical field of computer system software performance optimization. According to the method, multi-level instruction-level reconstruction is carried out on an execution path of a database kernel through the characteristics of an underlying hardware instruction set of a collaborative application processor platform, and the method comprises the following collaborative implementation optimization dimensions: based on a register file and a cache hierarchical structure of the processor platform, an access mode of a database core data structure is optimized; the number of memory access instructions is reduced; the data locality is improved; on the basis of atomic instruction set extension of a processor platform, instruction-level reconstruction is carried out on key primitives in a database multi-thread synchronization mechanism so as to reduce the overhead and contention of synchronization operation; on the basis of single-instruction multi-data-stream extension of a processor platform and a vector atomic operation instruction of the single-instruction multi-data-stream extension, parallel acceleration is carried out on batch life cycle management operation of objects in a database.

The invention discloses a data caching and updating method and device and a medium, and the method comprises the steps: determining a target access data identifier and an access scene parameter according to a data access request; further determining historical access features of the target access data and state parameters of a current system, and integrating the historical access features and the state parameters to generate a multi-dimensional feature vector; inputting the multi-dimensional feature vector into a pre-trained reinforcement learning model, determining a cache hierarchy and an elimination algorithm of the target access data according to the data type and the data access frequency, and caching the target access data; when it is detected that the target access data is updated, the cached target access data are locked, the updating state of the target access data in the database is judged, and updating of the cached data is completed according to the updating state. According to the method, through a layered caching mechanism, the access efficiency of data caching is greatly improved; and through an intelligent dynamic updating mechanism, the consistency of the cached data is ensured.

The invention relates to the technical field of front-end Web development, and particularly provides a multi-label page component cache management method and system, a terminal and a medium, and the method comprises the steps: setting a cache level mark for each routing node in routing configuration, and generating a unique component identifier by intercepting a routing event; recursively screening target components based on the depth of the cache hierarchy, and constructing a precise cache list; and in response to the change of the global state, directionally updating the field of the influenced component by adopting a difference comparison mechanism. According to the method, efficient management of multi-label page cache is realized, and the memory utilization rate and the page rendering performance are improved.

The invention discloses a design space exploration method for a cache hierarchical structure in a multi-core particle system. The method aims at optimizing the cache subsystem in the multi-core particle system, and the system performance is improved by reasonably configuring the cache hierarchical structure and the interconnection network topology between the core particles. The method comprises the following specific steps: 1) modeling a cache miss rate and network delay: modeling the cache miss rate and the network delay as a function of a cache hierarchical structure and interchip interconnection network parameters; 2) optimization problem definition: defining an optimization objective and minimizing concurrency average storage access time (C-AMAT) under the constraint of cost and power consumption; and 3) solving by using a double-layer optimization algorithm: respectively optimizing the cache subsystem and the interconnection network between the chip grains through the double-layer optimization algorithm. The method provides an effective solution for cache optimization of the multi-core particle system, and has a wide application prospect.

A disclosed method can include (i) detecting, by a probe filter in a coherent fabric interconnect, an access request to a specific memory address of a cache hierarchy using a new encryption key, (ii) verifying, by the probe filter, that the specific memory address stores data encrypted using a previous and distinct encryption key, and (iii) evicting, by the probe filter in response to the verifying, references to the previous and distinct encryption key from the cache hierarchy. Various other methods, systems, and computer-readable media are also disclosed.

Embodiments herein describe a configurable engine integrated into a processor's cache hierarchy. The configurable engine can enable efficient data sharing between main memory, cache memory, and cores. The configurable engine can perform more efficient operations within the cache hierarchy. In one embodiment, the configurable engine is controlled (or configured) by software (e.g., an operating system (OS)) and is tailored to each application domain. That is, the OS can configure the engine according to the data flow profile of a particular application being executed by the processor.

System-in-packages (SiPs) having hybrid high bandwidth memory (HBM) devices, and associated systems and methods, are disclosed herein. In some embodiments, the SiP includes a base substrate, as well as a processing device and a hybrid high-bandwidth memory (HBM) device each carried by the base substrate. The processing device includes a processing unit and a first cache memory associated with a first level of a cache hierarchy. The hybrid HBM device is electrically coupled to the processing unit through a SiP bus in the base substrate. Further, the hybrid HBM device includes an interface die, one or more memory dies carried by the interface die, and a shared bus electrically coupled to the interface die and each of the memory dies. The hybrid HBM device also includes a second cache memory formed on the interface die that is associated with a second level of the cache hierarchy.

Techniques for providing a return address stack with branch mispredict recovery are disclosed. A processor core is accessed. The processor core includes a return address stack (RAS), a local cache hierarchy, and branch prediction logic. RAS state information, including a write pointer, a read pointer, and a RAS count, is sent to a branch execution unit. One or more call instructions are detected in an instruction stream. The detecting generates a predicted return address for each of the one or more call instructions which are pushed on the RAS. The pushing is directed by the write pointer. One or more return instructions are recognized in the instruction stream. The write pointer and the read pointer for the RAS are updated, based on information from the branch execution unit. The predicted return address for each of the one or more return instructions is popped from the RAS.

The invention relates to a folder sharing auditing system and method, and belongs to the technical field of computers, and the system comprises an intelligent gateway which is used for analyzing a folder carried by a received user request and sending an analyzed file processing request to a fingerprint generation cluster; the fingerprint generation cluster receives the file processing request, generates a unique identifier of a file based on the size of the file, and sends the unique identifier to the cache module; the cache module receives the unique identifier of the file, determines the cache hierarchy of the file, and sends the target file to the clustering engine module under the condition of determining that the target file does not exist in the cache hierarchy; the clustering engine module receives the target file, and sends the target file to the grading auditing module under the condition that it is determined that the target file does not have a similar group; the grading auditing module receives the target file and determines an auditing channel according to the size of the target file. According to the system, the mass file processing efficiency is improved, and the system resource utilization rate is optimized.

This invention discloses a method and system for optimizing cache management. It receives registration requests from various cache nodes and establishes long-lived communication links with each cache node. The node information of the registered cache nodes is arranged according to the cache hierarchy to generate a tree structure. The tree structure is used to record, display, and manage the cache of each cache node. This invention registers cache nodes and generates a tree structure based on the cache hierarchy, with each cache level representing a layer of tree height. Each cache node in each cache level represents a tree node. Based on this tree structure, the cache of each cache node is recorded, displayed, and managed, making the process more intuitive and efficient.

An accelerated processor includes a processor core die including a plurality of compute units, the plurality of compute units including a first level (L1) cache. The accelerated processor also includes a plurality of memory cache dies coupled to the processor core die, the plurality of memory cache dies including a last level cache (LLC) such as a level 3 (L3) cache. The accelerated processor includes an LLC controller to issue a cache access request to the LLC and, based on a latency of the cache access request, direct the cache access request to a subset of the plurality of memory cache dies.

Techniques are disclosed relating to cache control in cache hierarchies. In some embodiments, processor execution circuitry is configured to perform operations on input operand data from a first-level cache, including a first operation that reads first data from an entry in the first-level cache and signals an invalidation of the first data. Control circuitry may set an indicator, in response to the first operation, to indicate that the entry in the first-level cache has a pending invalidation (e.g., a last-use indicator). The control circuitry may, in response to a second operation overwriting the entry in the first-level cache while the indicator is set, clear the indicator without invalidating a corresponding entry in a second-level cache. This may advantageously reduce invalidate operations and bandwidth to the second-level cache.

A data hiding-based cache side-channel attack defense method employs an independent data hiding buffer outside the existing cache hierarchy to hide data blocks evicted from the last-level cache. The data hiding buffer contains the buffered data blocks, a security state associated with each data block, a secure placement policy for filtering buffered data blocks, a secure replacement policy for controlling data replacement within the buffer, and an index-based fully associative data block search policy. The security state stores metadata required for the data hiding buffer to execute the secure replacement policy. The secure placement and secure replacement policies are used when a cache line is evicted from the last-level cache, while the fully associative data block search policy is used when accessing the data hiding buffer in the event of a last-level cache miss. The present invention not only protects against two types of cache side-channel attacks simultaneously, but also avoids performance degradation and operating system modifications.

Systems and methods are disclosed for concurrent support for multiple cache inclusivity schemes using low priority evict operations. For example, some methods may include, receiving a first eviction message having a lower priority than probe messages from a first inner cache; receiving a second eviction message having a higher priority than probe messages from a second inner cache; transmitting a third eviction message, determined based on the first eviction message, having the lower priority than probe messages to a circuitry that is closer to memory in a cache hierarchy; and, transmitting a fourth eviction message, determined based on the second eviction message, having the lower priority than probe messages to the circuitry that is closer to memory in the cache hierarchy.

The disclosed computer-implemented method can include detecting, by at least one processor, a cache load from a second central processing unit (CPU) cache hierarchy onto an exclusively owned cache region of cache memory that is exclusively owned by a first CPU cache hierarchy. The method can additionally include converting, by the at least one processor, the exclusively owned cache region, in response to the detection, to a dual owner cache region at least in part by partitioning one or more fields of an entry for the dual owner cache region in a region-based probe filter. The method can also include employing, by the at least one processor, the entry for the dual owner cache region to track cache subregion subscriptions of both the first CPU cache hierarchy and the second CPU cache hierarchy. Various other methods, systems, and computer-readable media are also disclosed.

Apparatus and method for leveraging simultaneous multithreading for bulk compute operations. For example, one embodiment of a processor comprises: a plurality of cores including a first core to simultaneously process instructions of a plurality of threads; a cache hierarchy coupled to the first core and the memory, the cache hierarchy comprising a Level 1 (L1) cache, a Level 2 (L2) cache, and a Level 3 (L3) cache; and a plurality of compute units coupled to the first core including a first compute unit associated with the L1 cache, a second compute unit associated with the L2 cache, and a third compute unit associated with the L3 cache, wherein the first core is to offload instructions for execution by the compute units, the first core to offload instructions from a first thread to the first compute unit, instructions from a second thread to the second compute unit, and instructions from a third thread to the third compute unit.

A method and apparatus for a speculative request indicator is described. A method includes providing, for a cache hierarchy, a messaging protocol used for transfer operations among agents in the cache hierarchy, the messaging protocol indicating acceptable cache coherency states for a cache block indicated in a request message and providing, in the messaging protocol for selection by an agent, a speculative request indicator when sending the request message, wherein the speculative request indicator differentiates between a demand request and a speculative request with respect to the cache block.

In order to further improve the quality of texture mapping and solve the problem of large dynamic random memory bandwidth consumption and data efficiency bottleneck, the application provides a method and device for texture mapping hardware acceleration, which improves the method of output pixel texture mapping to texture pixel points, replaces the bilinear interpolation with bicubic interpolation, and designs a static memory as a multi-path group associative cache, which can set different cache layers according to different application scenarios to reduce the consumption of memory resources, and effectively reduce the redundant bandwidth. The application can flexibly configure the texture cache hierarchy size according to the required texture mapping scene, realize the hardware acceleration of texture mapping through bicubic interpolation, and is suitable for various types of three-dimensional graphics systems.

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Disclosed embodiments provide techniques for prefetching. A processor core that executes instructions out of order (OOO) is accessed. The processor core includes a local cache hierarchy, data prefetch logic, and a prefetch table and is coupled to an external memory system. A first load instruction with a first address is detected and causes a miss in the local cache hierarchy. Information pertaining to the first load instruction is saved in an entry of the prefetch table. The information includes the first address, a confidence count, and an out-of-order mask. A second load instruction with a second address is identified. The information is updated based on the detecting. The information is advanced. The second address is the next sequential address after the first address. The advancing is based on the detecting. One or more data prefetch instructions are issued to the second address plus an offset.

Apparatus and methods are provided for handling cache maintenance operations. The apparatus has a plurality of requester elements for issuing requests and at least one completer element for processing such requests. A cache hierarchy is provided having a plurality of levels of cache to store cached copies of data associated with addresses in memory. A requester element can be arranged to issue a cache maintenance operation request specifying a range of memory addresses so as to cause a block of data associated with the specified range of memory addresses to be pushed through at least one level of the cache hierarchy to a determined visibility point so as to make the block of data visible to one or more other requester elements. A given requester element can be arranged to detect when a write request needs to be issued prior to a cache maintenance operation request so as to cause a write operation to be performed for a data item within the specified range of memory addresses, and in that case to generate a combined write and cache maintenance operation request to be issued in place of the write request and the subsequent cache maintenance operation request. A recipient completer element receiving the combined write and cache maintenance operation request can then be arranged to initiate processing of the cache maintenance operation required by the combined write and cache maintenance operation request without waiting for the write operation to complete. This can significantly reduce latency in the processing of cache maintenance operations, and can provide reduced bandwidth utilisation.

Various embodiments include techniques for migrating points of coherence (PoCs) in a cache hierarchy. The techniques comprise receiving, at a first cache memory and from a second cache memory, a memory access request associated with a first scope group, and, in response to determining a first directory within the first cache memory includes a first entry indicating (i) a third cache memory is a child of the first cache memory in a tree associated with the first scope group, and (ii) the first cache memory is a root of the tree associated with the first scope group: performing one or more operations to acquire a PoC token from a descendant cache memory of the first cache memory in the tree associated with the first scope group, and updating the first entry to indicate that the first cache memory is a PoC of the tree associated with the first scope group.

Apparatuses, methods, systems, and chip-containing products are disclosed, which relate to an arrangement comprising a level N cache level and a level M cache level, where M is greater than N. The level N cache level comprises a plurality of linefill slots and performs a slot allocation procedure in response to a lookup miss in dependence on a linefill slot occupancy criterion. The slot allocation procedure comprises allocation of an available slot of the plurality of slots to a pending linefill request generated in response to the lookup miss. The level N cache level effects a modification of the slot allocation procedure in dependence on the linefill slot occupancy criterion and is responsive to the linefill slot occupancy criterion being fulfilled to cause a linefill delegation action to be instructed to the level M cache level.

Techniques are disclosed relating to cache control in cache hierarchies. In some embodiments, processor execution circuitry is configured to perform operations on input operand data from a first-level cache, including a first operation that reads first data from an entry in the first-level cache and signals an invalidation of the first data. Control circuitry may set an indicator, in response to the first operation, to indicate that the entry in the first-level cache has a pending invalidation (e.g., a last-use indicator). The control circuitry may, in response to a second operation overwriting the entry in the first-level cache while the indicator is set, clear the indicator without invalidating a corresponding entry in a second-level cache. This may advantageously reduce invalidate operations and bandwidth to the second-level cache.

The present invention designs a cache side-channel attack defense method based on hybrid randomized mapping. This method considers the performance and security requirements of each cache level at different cache hierarchies. It uses table-based randomized mapping in the first-level cache and a computation-based randomized mapping scheme in other-level caches. At the same time, in caches at all levels, the present invention adopts the design of way-skewed cache by utilizing the characteristics of cache set associativity. The present invention has the advantages of high security, good performance, strong scalability, etc.

The invention provides a data cache management method and device, a storage medium and a program product, and the method comprises the steps: determining the cache priority of target data according to the access frequency of the target data in a first preset time interval and the occupied space of the target data; according to the aging type of the target data, the access frequency of the target data in the first preset time interval and the occupied space of the target data, determining the cache hierarchy of the target data; and adjusting the caching method of the target data according to the caching priority and the caching hierarchy of the target data. The cache priority and the cache level of the target data are adjusted in real time according to the change of the access mode of the target data, so that the adaptability of cache management to complex scenes is improved; furthermore, the cache hierarchy and the cache priority of the target data are determined from multiple dimensions, so that the cache management fineness is remarkably improved, and the hit rate of the cache is improved.

System-in-packages (SiPs) having hybrid high bandwidth memory (HBM) devices, and associated systems and methods, are disclosed herein. In some embodiments, the SiP includes a base substrate, as well as a processing device and a hybrid high-bandwidth memory (HBM) device each carried by the base substrate. The processing device includes a processing unit and a first cache memory associated with a first level of a cache hierarchy. The hybrid HBM device is electrically coupled to the processing unit through a SiP bus in the base substrate. Further, the hybrid HBM device includes an interface die, one or more memory dies carried by the interface die, and a shared bus electrically coupled to the interface die and each of the memory dies. The hybrid HBM device also includes a second cache memory formed on the interface die that is associated with a second level of the cache hierarchy.

Embodiments herein describe a configurable engine that is embedded into the cache hierarchy of a processor. The configurable engine can enable efficient data sharing between the main memory, cache memories, and the core. The configurable engine can perform operations that are more efficient to be done in the cache hierarchy. In one embodiment, the configurable engine is controlled (or configured) by software (e.g., the operating system (OS)), adapting to each application domain. That is, the OS can configure the engine according to a data flow profile of a particular application being executed by the processor.