17 results about "Cache hierarchy" patented technology

The invention provides a database concurrency control and memory access optimization method which can be applied to the technical field of computer system software performance optimization. According to the method, multi-level instruction-level reconstruction is carried out on an execution path of a database kernel through the characteristics of an underlying hardware instruction set of a collaborative application processor platform, and the method comprises the following collaborative implementation optimization dimensions: based on a register file and a cache hierarchical structure of the processor platform, an access mode of a database core data structure is optimized; the number of memory access instructions is reduced; the data locality is improved; on the basis of atomic instruction set extension of a processor platform, instruction-level reconstruction is carried out on key primitives in a database multi-thread synchronization mechanism so as to reduce the overhead and contention of synchronization operation; on the basis of single-instruction multi-data-stream extension of a processor platform and a vector atomic operation instruction of the single-instruction multi-data-stream extension, parallel acceleration is carried out on batch life cycle management operation of objects in a database.

The invention relates to the technical field of front-end Web development, and particularly provides a multi-label page component cache management method and system, a terminal and a medium, and the method comprises the steps: setting a cache level mark for each routing node in routing configuration, and generating a unique component identifier by intercepting a routing event; recursively screening target components based on the depth of the cache hierarchy, and constructing a precise cache list; and in response to the change of the global state, directionally updating the field of the influenced component by adopting a difference comparison mechanism. According to the method, efficient management of multi-label page cache is realized, and the memory utilization rate and the page rendering performance are improved.

Embodiments herein describe a configurable engine integrated into a processor's cache hierarchy. The configurable engine can enable efficient data sharing between main memory, cache memory, and cores. The configurable engine can perform more efficient operations within the cache hierarchy. In one embodiment, the configurable engine is controlled (or configured) by software (e.g., an operating system (OS)) and is tailored to each application domain. That is, the OS can configure the engine according to the data flow profile of a particular application being executed by the processor.

Techniques for providing a return address stack with branch mispredict recovery are disclosed. A processor core is accessed. The processor core includes a return address stack (RAS), a local cache hierarchy, and branch prediction logic. RAS state information, including a write pointer, a read pointer, and a RAS count, is sent to a branch execution unit. One or more call instructions are detected in an instruction stream. The detecting generates a predicted return address for each of the one or more call instructions which are pushed on the RAS. The pushing is directed by the write pointer. One or more return instructions are recognized in the instruction stream. The write pointer and the read pointer for the RAS are updated, based on information from the branch execution unit. The predicted return address for each of the one or more return instructions is popped from the RAS.

The invention relates to a folder sharing auditing system and method, and belongs to the technical field of computers, and the system comprises an intelligent gateway which is used for analyzing a folder carried by a received user request and sending an analyzed file processing request to a fingerprint generation cluster; the fingerprint generation cluster receives the file processing request, generates a unique identifier of a file based on the size of the file, and sends the unique identifier to the cache module; the cache module receives the unique identifier of the file, determines the cache hierarchy of the file, and sends the target file to the clustering engine module under the condition of determining that the target file does not exist in the cache hierarchy; the clustering engine module receives the target file, and sends the target file to the grading auditing module under the condition that it is determined that the target file does not have a similar group; the grading auditing module receives the target file and determines an auditing channel according to the size of the target file. According to the system, the mass file processing efficiency is improved, and the system resource utilization rate is optimized.

This invention discloses a method and system for optimizing cache management. It receives registration requests from various cache nodes and establishes long-lived communication links with each cache node. The node information of the registered cache nodes is arranged according to the cache hierarchy to generate a tree structure. The tree structure is used to record, display, and manage the cache of each cache node. This invention registers cache nodes and generates a tree structure based on the cache hierarchy, with each cache level representing a layer of tree height. Each cache node in each cache level represents a tree node. Based on this tree structure, the cache of each cache node is recorded, displayed, and managed, making the process more intuitive and efficient.

Techniques are disclosed relating to cache control in cache hierarchies. In some embodiments, processor execution circuitry is configured to perform operations on input operand data from a first-level cache, including a first operation that reads first data from an entry in the first-level cache and signals an invalidation of the first data. Control circuitry may set an indicator, in response to the first operation, to indicate that the entry in the first-level cache has a pending invalidation (e.g., a last-use indicator). The control circuitry may, in response to a second operation overwriting the entry in the first-level cache while the indicator is set, clear the indicator without invalidating a corresponding entry in a second-level cache. This may advantageously reduce invalidate operations and bandwidth to the second-level cache.

In order to further improve the quality of texture mapping and solve the problem of large dynamic random memory bandwidth consumption and data efficiency bottleneck, the application provides a method and device for texture mapping hardware acceleration, which improves the method of output pixel texture mapping to texture pixel points, replaces the bilinear interpolation with bicubic interpolation, and designs a static memory as a multi-path group associative cache, which can set different cache layers according to different application scenarios to reduce the consumption of memory resources, and effectively reduce the redundant bandwidth. The application can flexibly configure the texture cache hierarchy size according to the required texture mapping scene, realize the hardware acceleration of texture mapping through bicubic interpolation, and is suitable for various types of three-dimensional graphics systems.

Disclosed embodiments provide techniques for prefetching. A processor core that executes instructions out of order (OOO) is accessed. The processor core includes a local cache hierarchy, data prefetch logic, and a prefetch table and is coupled to an external memory system. A first load instruction with a first address is detected and causes a miss in the local cache hierarchy. Information pertaining to the first load instruction is saved in an entry of the prefetch table. The information includes the first address, a confidence count, and an out-of-order mask. A second load instruction with a second address is identified. The information is updated based on the detecting. The information is advanced. The second address is the next sequential address after the first address. The advancing is based on the detecting. One or more data prefetch instructions are issued to the second address plus an offset.

Techniques are disclosed relating to cache control in cache hierarchies. In some embodiments, processor execution circuitry is configured to perform operations on input operand data from a first-level cache, including a first operation that reads first data from an entry in the first-level cache and signals an invalidation of the first data. Control circuitry may set an indicator, in response to the first operation, to indicate that the entry in the first-level cache has a pending invalidation (e.g., a last-use indicator). The control circuitry may, in response to a second operation overwriting the entry in the first-level cache while the indicator is set, clear the indicator without invalidating a corresponding entry in a second-level cache. This may advantageously reduce invalidate operations and bandwidth to the second-level cache.

The invention provides a data cache management method and device, a storage medium and a program product, and the method comprises the steps: determining the cache priority of target data according to the access frequency of the target data in a first preset time interval and the occupied space of the target data; according to the aging type of the target data, the access frequency of the target data in the first preset time interval and the occupied space of the target data, determining the cache hierarchy of the target data; and adjusting the caching method of the target data according to the caching priority and the caching hierarchy of the target data. The cache priority and the cache level of the target data are adjusted in real time according to the change of the access mode of the target data, so that the adaptability of cache management to complex scenes is improved; furthermore, the cache hierarchy and the cache priority of the target data are determined from multiple dimensions, so that the cache management fineness is remarkably improved, and the hit rate of the cache is improved.

Embodiments herein describe a configurable engine that is embedded into the cache hierarchy of a processor. The configurable engine can enable efficient data sharing between the main memory, cache memories, and the core. The configurable engine can perform operations that are more efficient to be done in the cache hierarchy. In one embodiment, the configurable engine is controlled (or configured) by software (e.g., the operating system (OS)), adapting to each application domain. That is, the OS can configure the engine according to a data flow profile of a particular application being executed by the processor.

Disclosed embodiments provide techniques for prefetching. A processor core that executes instructions out of order (OOO) is accessed. The processor core includes a local cache hierarchy, data prefetch logic, and a prefetch table and is coupled to an external memory system. A first load instruction with a first address is detected and causes a miss in the local cache hierarchy. Information pertaining to the first load instruction is saved in an entry of the prefetch table. The information includes the first address, a confidence count, and an out-of-order mask. A second load instruction with a second address is identified. The information is updated based on the detecting. The information is advanced. The second address is the next sequential address after the first address. The advancing is based on the detecting. One or more data prefetch instructions are issued to the second address plus an offset.

Various embodiments include techniques for migrating points of coherence (PoCs) in a cache hierarchy. The techniques comprise receiving, at a first cache memory and from a second cache memory, a memory access request associated with a first scope group, and, in response to determining a first directory within the first cache memory includes a first entry indicating (i) a third cache memory is a child of the first cache memory in a tree associated with the first scope group, and (ii) the first cache memory is a root of the tree associated with the first scope group: performing one or more operations to acquire a PoC token from a descendant cache memory of the first cache memory in the tree associated with the first scope group, and updating the first entry to indicate that the first cache memory is a PoC of the tree associated with the first scope group.

Methods, apparatus, and computer programs are disclosed for data / instruction access based on performance hints. In some embodiments, a method comprises decoding an instruction to access data or code by a core of a computer processor, the instruction to provide one or more hints on how the data or code is to be processed through a cache hierarchy of the computer processor based on the instruction, the one or more hints indicating which level of the cache hierarchy or which cache in a level of the cache hierarchy to load or store the data or code, a priority of the data or code in a cache, or how the data or code is to be shared among multiple cores of the computer processor. The method further comprises processing the data or code based on the one or more hints responsive to the decoded instruction.

Various embodiments include techniques for migrating points of coherence (PoCs) in a cache hierarchy. The techniques comprise receiving, at a first cache memory and from a second cache memory, a memory access request associated with a first scope group, and, in response to determining a first directory within the first cache memory includes a first entry indicating (i) a third cache memory is a child of the first cache memory in a tree associated with the first scope group, and (ii) the first cache memory is a root of the tree associated with the first scope group: performing one or more operations to acquire a PoC token from a descendant cache memory of the first cache memory in the tree associated with the first scope group, and updating the first entry to indicate that the first cache memory is a PoC of the tree associated with the first scope group.

The application discloses a design space exploration method for cache hierarchy in a multi-core system. The method aims to optimize the cache subsystem in the multi-core system by reasonably configuring the cache hierarchy and the inter-chiplet network topology, thereby improving the system performance. The specific steps include: 1) cache miss rate and network delay modeling: modeling the cache miss rate and the network delay as functions of the cache hierarchy and the inter-chiplet network parameters; 2) optimization problem definition: defining the optimization target under the cost and power consumption constraints, and minimizing the concurrent average memory access time (C-AMAT); and 3) solving by a double-layer optimization algorithm: performing the cache subsystem optimization and the inter-chiplet network optimization by the double-layer optimization algorithm. The method provides an effective solution for the cache optimization of the multi-core system, and has a wide application prospect.