84 results about "Uniform memory access" patented technology

Disclosed in the present application are a resource adjustment method and apparatus, an electronic device, a storage medium and a training platform, which are applied to the technical field of artificial intelligence. The method comprises: acquiring a container set of computing nodes executing a task to be trained and a container associated with same; on the basis of resource configuration information of the container set, resource occupation information of the computing nodes and user resource requirements, and in a mode that target graphics processing unit and target central processing unit cores executing said task are preferentially located in the same non-uniform memory access group, selecting target central processing unit cores needing to be bound for the container, and updating configuration information of a process group corresponding to the container, so as to complete binding of the central processing unit cores and the container. The present application can solve the problem that AI training tasks cannot be efficiently completed in the related art, and can maximally ensure the efficient completion of AI training tasks by means of resource adjustment during the execution of the AI training tasks.

The invention provides a chip system and an access method, relates to the technical field of chips, and improves the data access performance of a high-performance computing system. According to the specific scheme, the chip system comprises a snoop filter, a plurality of processor cluster nodes and a plurality of memories, the processor cluster nodes are coupled through a bus, the snoop filter is coupled with the bus, the processor cluster nodes are in one-to-one correspondence with the memories, and the snoop filter adopts a unified directory format. The snoop filter is used for obtaining an access request initiated by the processor cluster node, and the access request comprises address information. The snoop filter is further used for determining an access mode of the access request based on the address information, wherein the access mode comprises a unified memory access mode and a non-unified memory access mode. The processor cluster node is to access the memory based on the access pattern and the access request. The embodiment of the invention is used for the process of accessing the memory by the processor cluster node.

The invention relates to the technical field of computers, in particular to a method for optimizing the processing speed of a user mode program under an NUMA architecture. The method comprises the steps that in response to the optimization requirement of a user for the processing speed of an original file, first mark information representing the optimization requirement is added in the original file, a target file is generated, and the original file is a user mode program file; registering an interpreter corresponding to the target file; when a starting request corresponding to a target file is received and the starting request is scheduled to the non-uniform memory access node, calling an interpreter to process the target file to obtain a file copy; loading the file copy to a cache space of the non-uniform memory access node; according to the scheme, when the target file is executed, local access can be directly performed, so that delay and performance overhead caused by cross-node access are avoided, and the reading speed and the processing efficiency of the file copy are improved; and while the function complexity is reduced, the system stability is improved, and the system is easier to maintain and manage.

The invention discloses a data stream processing method and device, electronic equipment and a storage medium, and relates to the technical field of distributed storage. According to the data stream processing method and device, the data stream transmission mode is pre-judged to be intra-node transmission or cross-node transmission based on a hardware topology mapping table, and read-write caches are dynamically allocated according to the pre-judged data stream transmission mode; data received by the front-end network card is directly written into a controller memory buffer area of the target equipment through point-to-point direct memory access for data streams transmitted in the nodes, and is read and forwarded from the target equipment by the rear-end network card; the sending cache and the receiving cache of the data stream transmitted across the nodes are locked to the non-uniform memory access node to which the target network card belongs, and the data are sent to the target node through the remote direct memory access register memory, so that the problem that the data stream processing is not optimized in combination with hardware topology characteristics can be solved; the technical effects of reducing data replication overhead, avoiding redundant access across hardware nodes, improving data stream transmission efficiency and realizing end-to-end zero replication transmission are achieved.

The invention discloses a data transmission method, system and device and a storage medium, is applied to a host end in a non-uniform memory access architecture, and relates to the technical field of data transmission, and the method comprises the steps that a target path mapping table from a target end is received and analyzed, and a plurality of monitoring entrances are obtained; based on the target path mapping table, establishing a plurality of connection paths corresponding to the plurality of monitoring entrances in sequence, and generating a connection pool; in response to a data read-write request generated by the host end for a target end, determining a target processor domain corresponding to the target storage unit according to the target path mapping table, and selecting a connection path associated with the target processor domain from the connection pool as a current read-write path; and monitoring and judging whether the current read-write path is available or not, and if not, reselecting. The data transmission method can be combined with NUMA architecture perception, path state monitoring and a policy-driven selection mechanism to at least solve the problems that in the prior art, path selection lacks topology perception and multiple network cards are difficult to aggregate and use.

Examples include techniques associated with mapping system memory physical addresses to isolation domains for uniform memory access (UMA) by a system. Examples include mapping separate system memory physical addresses ranges associated with memory devices communicatively coupled with at least one compute die of the system through an input / output (I / O) die of the system. The separate system memory physical addresses to be mapped to isolation domains and address decoder information is generated to indicate the mapping of the separate system memory physical address ranges to the isolation domains.

The invention discloses a task processing method and system, electronic equipment, a medium and a product, and relates to the technical field of high-performance computing. When the tasks with different priorities exist at the same time, the first type of tasks, namely the tasks with high priorities, are preferentially issued to the first type of execution queue in the scheduling domain in the node, and the processor core in the node executes the tasks according to the priority sequence of the execution queue. The first type of tasks in the first type of execution queue are ensured to be issued and executed; secondly, the task acquired by the processor core in the scheduling domain is issued by the node, and there is no need to fight for the same task by multiple cores, so that the task does not need to be locked, and the task processing efficiency and the system performance are improved; and thirdly, the tasks are issued in the non-uniform memory access architecture nodes, and the processor cores in the scheduling domains corresponding to the non-uniform memory access architecture nodes are utilized to execute the tasks, so that the performance loss of memory access across the non-uniform memory access architecture nodes is avoided.

The invention discloses a network performance optimization method and device, and is applied to a server system of a multi-non-uniform memory access node architecture, and the network performance optimization method comprises the steps: obtaining non-uniform memory access node information loaded by an operating system kernel and non-uniform memory access node information where a network card is located; if it is judged that the non-uniform memory access node loaded by the operating system kernel is the same as the non-uniform memory access node where the network card is located, checking the interrupt request binding condition of the network card; according to the interrupt request binding condition of the network card, if the interrupt request of the network card is not bound to the CPU core of the non-uniform memory access node where the network card is located, binding the interrupt request of the network card to the CPU core of the non-uniform memory access node where the network card is located.

The invention discloses a resource allocation method for non-uniform memory access and a memory access method and device, and relates to the technical field of non-uniform memory access. The resource allocation method comprises the following steps: determining a first target selected node set according to a first initial non-uniform memory access resource node of a received non-uniform memory access resource; traversing all initial non-consistent memory access resource nodes of the non-consistent memory access resources to determine all target selected node sets; determining a target selected node set meeting a target memory resource demand and a first preset condition in all target selected node sets as a target non-consistent memory access resource node set; and distributing the target non-uniform memory access resource node set to the executor with the target memory resource demand. According to the method, the target non-uniform memory access resource node set closest to the target selected node set is allocated to the executor, so that the delay of the executor at different NUMA nodes can be reduced.

The invention provides a log data processing method, device and equipment for a memory access node. The processing method comprises the following steps: acquiring a plurality of log threads which are started at present; dividing the plurality of log threads into N log thread groups according to the number N of non-uniform memory access nodes; obtaining a first preset number of target log file data to be operated by at least one log thread of the N consistent memory access nodes; distributing a global log sequence number for the first preset number of target log file data, wherein the global log sequence number is a log sequence number generated according to all log data in the N log thread groups; and according to a global log sequence number corresponding to the target log file data, writing a first preset quantity of target log file data to be operated by the at least one log thread into a local memory of the non-uniform memory access node. According to the embodiment of the invention, cross-node remote access can be avoided; and the memory access delay is obviously reduced.

Various embodiments may include a Package on Package (PoP) having a bottom package comprising a system-on-chip (SoC) and a bottom substrate, a top package comprising a top substrate, a first memory die, and a second memory die, wherein the first and second memory dies are different in at least one of: memory type, memory density, or memory capacity, an interposer electronically connecting the top package and the bottom package, and a heat sink covering at least a portion of the top package. The SoC may include a non-uniform memory access (NUMA) mechanism configured to manage data interleaving, memory write requests, memory access requests across the first and second memory dies.

Various approaches for exposing a virtual Non-Uniform Memory Access (NUMA) locality table to the guest OS of a VM running on NUMA system are provided. These approaches provide different tradeoffs between the accuracy of the virtual NUMA locality table and the ability of the system's hypervisor to migrate virtual NUMA nodes, with the general goal of enabling the guest OS to make more informed task placement / memory allocation decisions.

The application discloses a process scheduling method and device, a storage medium and a computer program product, and relates to the technical field of computers. The method comprises the following steps: counting resource demand indexes of processes; wherein the resource demand indexes comprise any one or a combination of several of the following: processor peak usage, memory growth rate, and input / output burst coefficient; performing behavior mode analysis on the processes to determine behavior mode indexes of the processes; wherein the behavior mode indexes comprise lock contention time and / or non-uniform memory access penalty value; generating dynamic priorities of the processes according to the resource demand indexes and the behavior mode indexes of the processes; and scheduling based on the dynamic priorities of the processes. The application improves the real-time performance and flexibility of process scheduling.

Memory pages can be migrated between non-uniform memory access (NUMA) nodes based on entries in a page modification log according to some examples described herein. In one example, a physical processor can detect a request from a virtual machine to access a memory page. The physical processor can then update a page modification log to include an entry indicating the request. A hypervisor supporting the virtual machine can be configured to detect the request based on the entry in the page modification log and, in response to detecting the request, migrate the memory page from a second NUMA node to a destination NUMA node.

Systems and method for automated efficient memory migration in Non-uniform Memory Access (NUMA) based virtual machines are introduced, comprising exporting one or more informative data objects, from a host machine to at least one virtual machine, wherein the informative data objects include references to pages that have been migrated from a physical source memory node (source node) on the host machine to a new source location on the host machine; inspecting, the informative data objects, by the at least one virtual machine; detecting, by the at least one virtual machine, the pages that have been migrated to the new source location; sending a request, by the at least one virtual machine, to the host machine via the hypervisor, to map the pages to a physical destination memory node (destination node) corresponding to a desired virtual destination memory node (destination vNode); and undertaking at least one efficient data migration operation.

The application relates to the storage technical field, in particular to a hard disk testing method and device, equipment and a readable storage medium. The method comprises the following steps: obtaining mapping information of hard disks and access nodes; wherein the access node is a node in a non-uniform memory access architecture; determining whether the number of hard disks allocated by the access node is balanced by using the mapping information; if not, adjusting the number of hard disks allocated by the access node, and returning to obtain the mapping information of the hard disks and the access nodes again; if yes, after the same number of processors are allocated to the hard disks in the access node, performing hard disk testing based on the non-uniform memory access architecture. After the resource balance is met, the hard disk testing is performed in the non-uniform memory access architecture, so that efficient processing of read-write operations at the processor level can be ensured, thereby avoiding the situation that the detection of individual disks does not match the actual situation, and the hard disk testing accuracy can be ensured.

A device calculates a memory oversubscription threshold for a virtual machine (VM). Based on the memory oversubscription threshold, the device determines a first memory size to be physically allocated to the VM, and a second memory size to be oversubscribed to the VM. The device configures a first virtual non-uniform memory access (NUMA) node comprising a virtual processor and a first virtual memory having the first memory size. The device allocates a first physical memory to back the first virtual memory. The device configures a second virtual NUMA node comprising a second virtual memory having the second memory size. The second virtual NUMA node is a computeless NUMA node. The device configures the VM to use the first virtual NUMA node and the second virtual NUMA node. Based on the second virtual NUMA node being computeless, the VM funnels a memory access to the first virtual memory.

Migrating containers across Non-Uniform Memory Access (NUMA) nodes of a processor device is disclosed herein. In one example, a processor device identifies one or more containers each executing on one of a plurality of NUMA nodes of the processor device. For each container of the one or more containers, the processor device determines an allocation of a processing resource to the container by a source NUMA node on which the container is executing, and identifies one or more NUMA nodes of the plurality of NUMA nodes having an availability of the processing resource sufficient to execute the container. The processor device selects a target NUMA node from among the identified one or more NUMA nodes, and migrates the container from the source NUMA node to the target NUMA node.

Migrating containers across Non-Uniform Memory Access (NUMA) nodes of a processor device is disclosed herein. In one example, a processor device identifies one or more containers each executing on one of a plurality of NUMA nodes of the processor device. For each container of the one or more containers, the processor device determines an allocation of a processing resource to the container by a source NUMA node on which the container is executing, and identifies one or more NUMA nodes of the plurality of NUMA nodes having an availability of the processing resource sufficient to execute the container. The processor device selects a target NUMA node from among the identified one or more NUMA nodes, and migrates the container from the source NUMA node to the target NUMA node.

Apparatuses, systems, and techniques to store information within one or more non-uniform memory access (NUMA) storages. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information to be stored within one or more NUMA storages or one or more graphics processor unit (GPU) physical storages based, at least in part, on one or more indicators to be indicated by one or more users of the API.

The application provides a modular integrated circuit unit, a distributed storage unit access method and system, and the modular integrated circuit unit comprises at least one memory controller, which sends a storage address access request to a storage unit; at least one storage unit, which provides uniform memory access for the storage address access request, and the storage unit comprises a local storage unit and a virtual remote storage unit; at least one computing unit, which initiates the storage address access request; and at least one on-chip interconnection network, which interweaves a storage address indicated by the storage address access request to generate an interwoven storage address distribution and determines a corresponding target storage unit. By setting the local storage unit and the virtual remote storage unit, using the address interweaving technology and the virtual storage mapping, the distributed storage units on multiple modular integrated circuit units can realize uniform address access and load balancing, the resource utilization rate is improved, and the performance and the ease of use of the distributed storage system are improved.

The present disclosure provides a virtual machine running control method and device, computer equipment and a storage medium, wherein the method comprises: obtaining non-uniform memory access (NUMA) node configuration information of a virtual machine; the NUMA node configuration information is determined according to a host NUMA topology relationship of a host running the virtual machine; the host NUMA topology relationship is used to indicate the distance between a physical central processing unit and a physical memory space in the host; using a virtual machine monitor, converting the NUMA node configuration information into target configuration information in a target format, and configuring the target configuration information as a target start parameter of a child operating system of the virtual machine; using the child operating system, creating each target virtual NUMA node corresponding to the virtual machine according to the target configuration information carried by the target start parameter. The present disclosure can accurately transfer the host NUMA topology relationship to the virtual machine without the help of ACPI.

Some embodiments provide a method for a data message processing device that includes multiple network interfaces associated with at least two different non-uniform memory access (NUMA) nodes. The method receives a data message at a first network interface associated with a particular one of the NUMA nodes. Based on processing of the data message, the method identifies multiple equivalent output options for the data message. Each of the output options is associated with a respective one of the NUMA nodes. The method selects an equivalent output option for the data message that is associated with the particular NUMA node.

The invention discloses an IO full-path memory access optimization system and method based on an NUMA architecture, and the system comprises a file system module, an IO scheduling module, a disk interaction module and a configuration and management module, and the file system module is used for receiving an IO request and obtaining storage pool instance information; transferring the IO request to an IO request processing process for processing, packaging the IO request into a scheduling request, and putting the scheduling request into a scheduling request queue corresponding to a local node; the IO scheduling module is used for an IO scheduling process to obtain a scheduling request, processing the scheduling request, packaging the processed scheduling request into a disk interaction request and putting the disk interaction request into an IO request queue; and the disk interaction module is used for obtaining the disk interaction request from the IO request queue, processing the disk interaction request to obtain an IO processing result, and returning the IO processing result to the upper-layer application program, so that full-path memory localization access from the IO request initiated by the upper-layer application to the final data interaction with the disk and rapid transplantation on different NUMA platforms are realized.

An efficient multi-core processor is provided, with processor instructions and an operating method associated with lock competition of a shared computing resource. A lock-application instruction is provided. Accordingly, the different processes executed by the different central processing unit (CPU) cores stand in a queue for right-of-access to the shared computing resources. The execution of the lock-application instruction is accompanied by the monitoring of a competition-level indicator. Based on the competition-level indicator, the lock of the shared computing resource is switched from a primitive lock mode that follows the first-in and first-out rule, to a Non-Uniform Memory Access (NUMA) lock mode.

The invention discloses a CPU (central processing unit) isolated operation method based on an isolated scheduling domain under an NUMA (non-uniform memory access) architecture, and relates to the technical field of virtualized computing. A CPU core is divided into the isolated scheduling domain and a common scheduling domain according to an NUMA topological structure and kernel configuration parameters; obtaining a trusted virtual machine label parameter in the trusted virtual machine creation instruction, transmitting the trusted virtual machine label parameter to a kernel module step by step through a virtualization management layer, and writing the trusted virtual machine label parameter into a target process through the kernel module to obtain a target label process; identifying a target label process, when the target label process is the label process in which the label parameters of the trusted virtual machine are written, scheduling the target label process to an isolation scheduling domain, otherwise, scheduling the target label process to a common scheduling domain; and running the target label process. Through the technical scheme, the adaptability of an isolation mechanism and NUMA architecture characteristics can be improved, and then the matching degree of resource allocation and memory access locality is improved.

The present application discloses a container scheduling method, device and system, which relates to the field of container scheduling technology and is used to improve overall resource utilization. The method includes: obtaining resource information of at least two working nodes and resource information of at least one application, wherein the resources of at least two working nodes include at least one of the number of CPU cores, memory capacity or hard disk capacity; wherein the resource information of at least one application is used to describe the resources required by at least one application during operation; determining a target working node based on the resource information of at least one application and the resource information of at least two working nodes, wherein the target working node is the minimum number of working nodes required to run at least one application, or the target working node is the working node with the shortest non-uniform memory access (NUMA) path required to run at least one application; when the working node running at least one application is different from the target working node, scheduling at least one application to a container on the target working node.

Some embodiments provide a novel method for dynamically processing data message flows using different non-uniform memory access (NUMA) nodes of a processing system. Each NUMA node includes a memory and processors that can access data other memories of other NUMA nodes. A load balancing application associated with a first NUMA node receives flows destined for an endpoint application. The flows are assigned to the first NUMA node to be forwarded to the endpoint application. The load balancing application monitors a central processing (CPU) usage of the first NUMA node to determine whether the CPU usage of the first NUMA node exceeds a particular threshold. When the CPU usage of the first NUMA node exceeds the particular threshold, the load balancing application reassigns at least a subset of the flows to the second NUMA node for processing.

Some embodiments provide a novel method for forwarding data messages between first and second host computers. To send, to a first machine executing on the first host computer, a flow from a second machine executing on the second host computer, the method identifies a destination network address of the flow. The method uses the identified destination network address to identify a particular tunnel endpoint group (TEPG) including a particular set of one or more tunnel endpoints (TEPs) associated with a particular non-uniform memory access (NUMA) node of a set of NUMA nodes of the first host computer. The particular NUMA node executes the first machine. The method selects, from the particular TEPG, a particular TEP as a destination TEP of the flow. The method sends the flow to the particular TEP of the particular NUMA node of the first host computer to send the flow to the first machine.

The invention provides a memory type determination method, device and equipment, and belongs to the field of data processing.The method comprises the steps that a target server and a target running program are determined, the target server adopts a non-uniform memory access architecture, the non-uniform memory access architecture comprises a plurality of nodes, and each node comprises a central processing unit (CPU) and a memory; first access performance of a target CPU executing the target running program in a first simulation scene and second access performance of the target CPU in a second simulation scene are determined, the first simulation scene indicates that the target CPU accesses memories of other nodes, the second simulation scene indicates that the target CPU accesses a memory of a local node, and the target CPU belongs to CPUs included in the multiple nodes; and determining a memory type corresponding to the target running program according to the first access performance and the second access performance, wherein the memory type comprises a small page memory or a large page memory. Therefore, the access performance of the CPU can be improved.