52 results about "Uniform memory access" patented technology

The invention relates to the technical field of computers, in particular to a method for optimizing the processing speed of a user mode program under an NUMA architecture. The method comprises the steps that in response to the optimization requirement of a user for the processing speed of an original file, first mark information representing the optimization requirement is added in the original file, a target file is generated, and the original file is a user mode program file; registering an interpreter corresponding to the target file; when a starting request corresponding to a target file is received and the starting request is scheduled to the non-uniform memory access node, calling an interpreter to process the target file to obtain a file copy; loading the file copy to a cache space of the non-uniform memory access node; according to the scheme, when the target file is executed, local access can be directly performed, so that delay and performance overhead caused by cross-node access are avoided, and the reading speed and the processing efficiency of the file copy are improved; and while the function complexity is reduced, the system stability is improved, and the system is easier to maintain and manage.

The invention discloses a data stream processing method and device, electronic equipment and a storage medium, and relates to the technical field of distributed storage. According to the data stream processing method and device, the data stream transmission mode is pre-judged to be intra-node transmission or cross-node transmission based on a hardware topology mapping table, and read-write caches are dynamically allocated according to the pre-judged data stream transmission mode; data received by the front-end network card is directly written into a controller memory buffer area of the target equipment through point-to-point direct memory access for data streams transmitted in the nodes, and is read and forwarded from the target equipment by the rear-end network card; the sending cache and the receiving cache of the data stream transmitted across the nodes are locked to the non-uniform memory access node to which the target network card belongs, and the data are sent to the target node through the remote direct memory access register memory, so that the problem that the data stream processing is not optimized in combination with hardware topology characteristics can be solved; the technical effects of reducing data replication overhead, avoiding redundant access across hardware nodes, improving data stream transmission efficiency and realizing end-to-end zero replication transmission are achieved.

The invention discloses a data transmission method, system and device and a storage medium, is applied to a host end in a non-uniform memory access architecture, and relates to the technical field of data transmission, and the method comprises the steps that a target path mapping table from a target end is received and analyzed, and a plurality of monitoring entrances are obtained; based on the target path mapping table, establishing a plurality of connection paths corresponding to the plurality of monitoring entrances in sequence, and generating a connection pool; in response to a data read-write request generated by the host end for a target end, determining a target processor domain corresponding to the target storage unit according to the target path mapping table, and selecting a connection path associated with the target processor domain from the connection pool as a current read-write path; and monitoring and judging whether the current read-write path is available or not, and if not, reselecting. The data transmission method can be combined with NUMA architecture perception, path state monitoring and a policy-driven selection mechanism to at least solve the problems that in the prior art, path selection lacks topology perception and multiple network cards are difficult to aggregate and use.

Examples include techniques associated with mapping system memory physical addresses to isolation domains for uniform memory access (UMA) by a system. Examples include mapping separate system memory physical addresses ranges associated with memory devices communicatively coupled with at least one compute die of the system through an input / output (I / O) die of the system. The separate system memory physical addresses to be mapped to isolation domains and address decoder information is generated to indicate the mapping of the separate system memory physical address ranges to the isolation domains.

Various embodiments may include a Package on Package (PoP) having a bottom package comprising a system-on-chip (SoC) and a bottom substrate, a top package comprising a top substrate, a first memory die, and a second memory die, wherein the first and second memory dies are different in at least one of: memory type, memory density, or memory capacity, an interposer electronically connecting the top package and the bottom package, and a heat sink covering at least a portion of the top package. The SoC may include a non-uniform memory access (NUMA) mechanism configured to manage data interleaving, memory write requests, memory access requests across the first and second memory dies.

The application discloses a process scheduling method and device, a storage medium and a computer program product, and relates to the technical field of computers. The method comprises the following steps: counting resource demand indexes of processes; wherein the resource demand indexes comprise any one or a combination of several of the following: processor peak usage, memory growth rate, and input / output burst coefficient; performing behavior mode analysis on the processes to determine behavior mode indexes of the processes; wherein the behavior mode indexes comprise lock contention time and / or non-uniform memory access penalty value; generating dynamic priorities of the processes according to the resource demand indexes and the behavior mode indexes of the processes; and scheduling based on the dynamic priorities of the processes. The application improves the real-time performance and flexibility of process scheduling.

Memory pages can be migrated between non-uniform memory access (NUMA) nodes based on entries in a page modification log according to some examples described herein. In one example, a physical processor can detect a request from a virtual machine to access a memory page. The physical processor can then update a page modification log to include an entry indicating the request. A hypervisor supporting the virtual machine can be configured to detect the request based on the entry in the page modification log and, in response to detecting the request, migrate the memory page from a second NUMA node to a destination NUMA node.

The application relates to the storage technical field, in particular to a hard disk testing method and device, equipment and a readable storage medium. The method comprises the following steps: obtaining mapping information of hard disks and access nodes; wherein the access node is a node in a non-uniform memory access architecture; determining whether the number of hard disks allocated by the access node is balanced by using the mapping information; if not, adjusting the number of hard disks allocated by the access node, and returning to obtain the mapping information of the hard disks and the access nodes again; if yes, after the same number of processors are allocated to the hard disks in the access node, performing hard disk testing based on the non-uniform memory access architecture. After the resource balance is met, the hard disk testing is performed in the non-uniform memory access architecture, so that efficient processing of read-write operations at the processor level can be ensured, thereby avoiding the situation that the detection of individual disks does not match the actual situation, and the hard disk testing accuracy can be ensured.

Apparatuses, systems, and techniques to store information within one or more non-uniform memory access (NUMA) storages. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information to be stored within one or more NUMA storages or one or more graphics processor unit (GPU) physical storages based, at least in part, on one or more indicators to be indicated by one or more users of the API.

The application provides a modular integrated circuit unit, a distributed storage unit access method and system, and the modular integrated circuit unit comprises at least one memory controller, which sends a storage address access request to a storage unit; at least one storage unit, which provides uniform memory access for the storage address access request, and the storage unit comprises a local storage unit and a virtual remote storage unit; at least one computing unit, which initiates the storage address access request; and at least one on-chip interconnection network, which interweaves a storage address indicated by the storage address access request to generate an interwoven storage address distribution and determines a corresponding target storage unit. By setting the local storage unit and the virtual remote storage unit, using the address interweaving technology and the virtual storage mapping, the distributed storage units on multiple modular integrated circuit units can realize uniform address access and load balancing, the resource utilization rate is improved, and the performance and the ease of use of the distributed storage system are improved.

The present disclosure provides a virtual machine running control method and device, computer equipment and a storage medium, wherein the method comprises: obtaining non-uniform memory access (NUMA) node configuration information of a virtual machine; the NUMA node configuration information is determined according to a host NUMA topology relationship of a host running the virtual machine; the host NUMA topology relationship is used to indicate the distance between a physical central processing unit and a physical memory space in the host; using a virtual machine monitor, converting the NUMA node configuration information into target configuration information in a target format, and configuring the target configuration information as a target start parameter of a child operating system of the virtual machine; using the child operating system, creating each target virtual NUMA node corresponding to the virtual machine according to the target configuration information carried by the target start parameter. The present disclosure can accurately transfer the host NUMA topology relationship to the virtual machine without the help of ACPI.

Some embodiments provide a method for a data message processing device that includes multiple network interfaces associated with at least two different non-uniform memory access (NUMA) nodes. The method receives a data message at a first network interface associated with a particular one of the NUMA nodes. Based on processing of the data message, the method identifies multiple equivalent output options for the data message. Each of the output options is associated with a respective one of the NUMA nodes. The method selects an equivalent output option for the data message that is associated with the particular NUMA node.

The invention discloses an IO full-path memory access optimization system and method based on an NUMA architecture, and the system comprises a file system module, an IO scheduling module, a disk interaction module and a configuration and management module, and the file system module is used for receiving an IO request and obtaining storage pool instance information; transferring the IO request to an IO request processing process for processing, packaging the IO request into a scheduling request, and putting the scheduling request into a scheduling request queue corresponding to a local node; the IO scheduling module is used for an IO scheduling process to obtain a scheduling request, processing the scheduling request, packaging the processed scheduling request into a disk interaction request and putting the disk interaction request into an IO request queue; and the disk interaction module is used for obtaining the disk interaction request from the IO request queue, processing the disk interaction request to obtain an IO processing result, and returning the IO processing result to the upper-layer application program, so that full-path memory localization access from the IO request initiated by the upper-layer application to the final data interaction with the disk and rapid transplantation on different NUMA platforms are realized.

An efficient multi-core processor is provided, with processor instructions and an operating method associated with lock competition of a shared computing resource. A lock-application instruction is provided. Accordingly, the different processes executed by the different central processing unit (CPU) cores stand in a queue for right-of-access to the shared computing resources. The execution of the lock-application instruction is accompanied by the monitoring of a competition-level indicator. Based on the competition-level indicator, the lock of the shared computing resource is switched from a primitive lock mode that follows the first-in and first-out rule, to a Non-Uniform Memory Access (NUMA) lock mode.

The invention discloses a CPU (central processing unit) isolated operation method based on an isolated scheduling domain under an NUMA (non-uniform memory access) architecture, and relates to the technical field of virtualized computing. A CPU core is divided into the isolated scheduling domain and a common scheduling domain according to an NUMA topological structure and kernel configuration parameters; obtaining a trusted virtual machine label parameter in the trusted virtual machine creation instruction, transmitting the trusted virtual machine label parameter to a kernel module step by step through a virtualization management layer, and writing the trusted virtual machine label parameter into a target process through the kernel module to obtain a target label process; identifying a target label process, when the target label process is the label process in which the label parameters of the trusted virtual machine are written, scheduling the target label process to an isolation scheduling domain, otherwise, scheduling the target label process to a common scheduling domain; and running the target label process. Through the technical scheme, the adaptability of an isolation mechanism and NUMA architecture characteristics can be improved, and then the matching degree of resource allocation and memory access locality is improved.

The present application discloses a container scheduling method, device and system, which relates to the field of container scheduling technology and is used to improve overall resource utilization. The method includes: obtaining resource information of at least two working nodes and resource information of at least one application, wherein the resources of at least two working nodes include at least one of the number of CPU cores, memory capacity or hard disk capacity; wherein the resource information of at least one application is used to describe the resources required by at least one application during operation; determining a target working node based on the resource information of at least one application and the resource information of at least two working nodes, wherein the target working node is the minimum number of working nodes required to run at least one application, or the target working node is the working node with the shortest non-uniform memory access (NUMA) path required to run at least one application; when the working node running at least one application is different from the target working node, scheduling at least one application to a container on the target working node.

Some embodiments provide a novel method for forwarding data messages between first and second host computers. To send, to a first machine executing on the first host computer, a flow from a second machine executing on the second host computer, the method identifies a destination network address of the flow. The method uses the identified destination network address to identify a particular tunnel endpoint group (TEPG) including a particular set of one or more tunnel endpoints (TEPs) associated with a particular non-uniform memory access (NUMA) node of a set of NUMA nodes of the first host computer. The particular NUMA node executes the first machine. The method selects, from the particular TEPG, a particular TEP as a destination TEP of the flow. The method sends the flow to the particular TEP of the particular NUMA node of the first host computer to send the flow to the first machine.

The invention provides a memory type determination method, device and equipment, and belongs to the field of data processing.The method comprises the steps that a target server and a target running program are determined, the target server adopts a non-uniform memory access architecture, the non-uniform memory access architecture comprises a plurality of nodes, and each node comprises a central processing unit (CPU) and a memory; first access performance of a target CPU executing the target running program in a first simulation scene and second access performance of the target CPU in a second simulation scene are determined, the first simulation scene indicates that the target CPU accesses memories of other nodes, the second simulation scene indicates that the target CPU accesses a memory of a local node, and the target CPU belongs to CPUs included in the multiple nodes; and determining a memory type corresponding to the target running program according to the first access performance and the second access performance, wherein the memory type comprises a small page memory or a large page memory. Therefore, the access performance of the CPU can be improved.

The description relates to dynamic memory management. One example includes an assembly that entails processing elements and memory. A dynamic UMA / NUMA configuration module is configured to facilitate managing a first region of the memory based upon a Uniform Memory Access (UMA) architecture and a second region of the memory based upon a Non-Uniform Memory Access (NUMA) architecture. The dynamic UMA / NUMA configuration module is configured to dynamically adjust ratios of the memory in the first region and the second region based upon workload changes on the processing elements.

The invention relates to the technical field of computers, in particular to a data processing method and device based on bound nodes and a storage medium, and aims to reduce performance overhead caused by cross-node access. The method applied to the virtualized process service comprises the following steps: according to resource use information of each non-uniform memory access NUMA node on a physical machine to which the virtualized process service belongs, screening out one NUMA node from each NUMA node as a target NUMA node; binding a service runtime memory of the virtualized process service to the target NUMA node; and sending the node information of the target NUMA node to the proxy service, so that the proxy service applies for a shared memory from the target NUMA node after receiving the node information of the target NUMA node, and maps the shared memory to the virtualization process service for use, and during data transmission each time, realizing data transmission between the service runtime memory and the shared memory on the target NUMA node.

The embodiment of the invention provides a server resource scheduling method, electronic equipment and a storage medium. The method comprises the following steps: creating and loading a scheduling program in a user mode, and scanning a processor topology to generate a scheduling domain based on a non-uniform memory access node; loading the program into a memory to complete initialization of a kernel scheduler, generating a scheduling callback function and associating the scheduling callback function to realize interaction between a user mode and a kernel mode; kernel load information is obtained in real time and shared to a user mode program, a scheduling decision instruction is determined by the user mode program, and scheduling domain extension and processor frequency adjustment are executed to complete scheduling. The method can improve scheduling flexibility, optimize resource utilization, effectively improve server performance, reduce energy consumption and adapt to a dynamic load scene of a cloud data center.

The application discloses a non-uniform memory access resource allocation method and device and a memory access method, and relates to the technical field of non-uniform memory access. The resource allocation method comprises the following steps: determining a first target selected node set according to a first starting non-uniform memory access resource node of a received non-uniform memory access resource; traversing all starting non-uniform memory access resource nodes of the non-uniform memory access resource to determine all target selected node sets; determining a target selected node set meeting a target memory resource demand and a first preset condition in the all target selected node sets as a target non-uniform memory access resource node set; and distributing the target non-uniform memory access resource node set to an executor existing the target memory resource demand. The target non-uniform memory access resource node set closest to the target selected node set is distributed to the executor, so that the delay of the executor in different NUMA nodes can be reduced.

This application relates to chassis repair and migration in a scale-out NUMA system. One aspect of the application can provide a system and method to replace a failed node with a spare node in a non-uniform memory access (NUMA) system. During operation, in response to determining that a node migration condition is satisfied, the system can initialize a node controller of the spare node such that access to memory local to the spare node is to be handled by the node controller, stall the failed node and the spare node to allow state information of a processor on the failed node to be migrated to a processor on the spare node, and after unstalling the failed node and the spare node, migrate data from the failed node to the spare node while maintaining cache coherency in the NUMA system and the NUMA system remains operational, thereby facilitating continued execution of processes previously executing on the failed node.

The application provides a metadata processing method, device, equipment, storage medium and product. The method comprises the following steps: in response to receiving an operation request for metadata in a distributed file system comprising a plurality of preset directory groups sent by a client device, determining a target directory group storing target metadata according to a storage path of the target metadata in the operation request; the target metadata comprises target directory access metadata and / or target file metadata under a directory thereof, and the target directory group is used for storing the target metadata and parent directory timestamp metadata thereof; for each preset directory group, the data in each preset directory group is stored in a corresponding non-uniform memory access node respectively, a plurality of non-uniform memory access nodes are located in corresponding metadata servers, and the data in each preset directory group comprises preset metadata and parent directory timestamp metadata thereof; performing an operation on the target metadata according to an operation type in the operation request, and updating the parent directory timestamp metadata of the target metadata.

Some embodiments provide a method for a data message processing device that includes multiple network interfaces associated with at least two different non-uniform memory access (NUMA) nodes. The method receives a data message at a first network interface associated with a particular one of the NUMA nodes. Based on processing of the data message, the method identifies multiple output options for the data message. Each of the output options has an equal forwarding cost and each output option is associated with a respective one of the NUMA nodes. The method selects an output option for the data message that is associated with the particular NUMA node to avoid cross-NUMA node processing of the data message.

In some embodiments, a system-on-chip, includes a central processing unit (CPU); an accelerator coupled to the CPU via a first die-to-die interconnect; and uniform memory coupled to the CPU via a second die-to-die interconnect. In some embodiments, in order to prevent use of accelerator memory for processing operations by the accelerator, the accelerator utilizes a uniform memory access tunneling system located in the accelerator to tunnel a high-level interconnect protocol associated with the second die-to-die interconnect to a die-to-die interconnect protocol associated with the first die-to-die interconnect, the uniform memory access tunneling system being configured to allow access to the uniform memory using a shared address space.

Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system. The processor-based system is configured to receive a cache allocation request to allocate a line in a share cache structure, which may further include a client identification (ID). The cache allocation request and the client ID can be compared to a sub-non-uniform memory access (NUMA) (sub-NUMA) bit mask and a client allocation bit mask to generate a cache allocation vector. The sub-NUMA bit mask may have been programmed to indicate that processing cores associated with a sub-NUMA region are available, whereas processing cores associated with other sub-NUMA regions are not available, and the client allocation bit mask may have been programmed to indicate that processing cores are available. The sub-NUMA bit mask and the client allocation bit mask can be combined to create a cache allocation vector that a cache allocation request to allocate a line serviced by one of processing cores.

Some embodiments provide a novel method for forwarding data messages between first and second host computers. To send, to a first machine of the first host, a second flow from a second machine of the second host in response to a first flow from the first machine, the method identifies from a set of tunnel endpoints (TEPs) of the first host a TEP that is a source TEP of the first flow. The method uses the identified TEP to identify one non-uniform memory access (NUMA) node of a set of NUMA nodes of the first host as the NUMA node associated with the first flow. The method selects, from a subset of TEPs of the first host that is associated with the identified NUMA node, one TEP as a destination TEP of the second flow. The method sends the second flow to the selected TEP of the first host.

Various embodiments may include a Package on Package (PoP) having a bottom package comprising a system-on-chip (SoC) and a bottom substrate, a top package comprising a top substrate, a first memory die, and a second memory die, wherein the first and second memory dies are different in at least one of: memory type, memory density, or memory capacity, an interposer electronically connecting the top package and the bottom package, and a heat sink covering at least a portion of the top package. The SoC may include a non-uniform memory access (NUMA) mechanism configured to manage data interleaving, memory write requests, memory access requests across the first and second memory dies.

The application relates to a graphics processor resource scheduling method and system, computer equipment and a storage medium. The method comprises the following steps: acquiring a plurality of preparation nodes and the node idle bandwidth of each preparation node within a preset time, and acquiring the group average idle bandwidth of each non-uniform memory access group within the preparation node within a preset time; determining a target task and a task type thereof, calculating the node score of each preparation node under different task types, and determining a target node according to the task type and the node score; and selecting a target graphics processor from the target node according to the group average idle bandwidth, so as to execute the target task through the target graphics processor, thereby improving the graphics processor resource utilization rate.