Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method

Abstract

The invention discloses an extension Cache Coherence protocol-based multi-level consistency domain simulation verification and test method. An extension Cache Coherence protocol-based multi-level consistency domain CC-NUMA (Cache Coherent Non-Uniform Memory Access) system protocol simulation model is constructed. A protocol table inquiring and state converting executing mechanism in a key node of a system ensures that a Cache Coherence protocol is maintained in a single computing domain and is simultaneous maintained among a plurality of computing domains, and accuracy and stability are ensured by intra-domain and inter-domain transmission; and a credible protocol inlet conversion coverage rate evaluating drive verification method is provided, transactions are processed by loading an optimized transaction generator promoting model, a coverage rate index is obtained after the operation is ended, and the verification efficiency is increased in comparison with a random transaction promoting mechanism. Through constructing one multi-processor multi-consistency domain verification system model and developing relevant simulation verification, the applicability and the effectiveness of the method are further confirmed.

Description

technical field [0001] The present invention relates to the invention belonging to the category of computer architecture, and in particular to Cache consistency of multiprocessor computer systems; multi-node multiprocessor computer systems; CC-NUMA (Cache Coherent Non-Uniform Memory Access——Cache Coherent Non-Uniform Memory Access Access) architecture; multi-level coherence domain and model test verification method of Cache Coherence protocol, specifically a multi-level coherence domain simulation verification and testing method based on extended Cache Coherence protocol. Background technique [0002] The current connection mode between multiprocessors has changed from bus connection to point-to-point connection, and the memory has also changed from being connected to the external bridge chip of the processor to being directly connected to the processor. Due to changes in memory mounting methods, the distribution of memory in the system also changes, resulting in non-uniform...

AI Technical Summary

Problems solved by technology

[0009] Due to the limited number of processor IDs in the domain that the processor can support, the number of node controllers required by the multi-processor system is too large, resulting in a large scale of interconnection between nodes and a complex topology.

Images