Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method

A simulation verification and testing method technology, applied in design optimization/simulation, function inspection, error detection/correction, etc., can solve problems such as complex topology, large number of node controllers, and large-scale node interconnection

Active Publication Date: 2013-06-12
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Application Information

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Problems solved by technology

[0009] Due to the limited number of processor IDs in the domain that the processor can support, the number of node controllers requ

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  • Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method
  • Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method
  • Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method

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Embodiment Construction

[0057] The method of the present invention will be described in further detail below in conjunction with the accompanying drawings.

[0058] 1) Multi-layer Cache consistency protocol model simulation test structure

[0059] This system uses the SystemC language to design and realize the whole system simulator, realizes the simulation parallel method, and the model verification is carried out by constructing a pseudo-random software simulation verification system under the SystemC environment, and its structure is as follows figure 2 shown;

[0060] The verification system mainly includes the following parts:

[0061] (1) Bus function model: It is a clock-accurate functional model, which simulates and implements the Cache, memory control, and interconnection network within and between processors in the processor; it provides transaction-level simulation support for memory access behavior ;Support custom system topology; provide external API interface for message interaction ...

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Abstract

The invention discloses an extension Cache Coherence protocol-based multi-level consistency domain simulation verification and test method. An extension Cache Coherence protocol-based multi-level consistency domain CC-NUMA (Cache Coherent Non-Uniform Memory Access) system protocol simulation model is constructed. A protocol table inquiring and state converting executing mechanism in a key node of a system ensures that a Cache Coherence protocol is maintained in a single computing domain and is simultaneous maintained among a plurality of computing domains, and accuracy and stability are ensured by intra-domain and inter-domain transmission; and a credible protocol inlet conversion coverage rate evaluating drive verification method is provided, transactions are processed by loading an optimized transaction generator promoting model, a coverage rate index is obtained after the operation is ended, and the verification efficiency is increased in comparison with a random transaction promoting mechanism. Through constructing one multi-processor multi-consistency domain verification system model and developing relevant simulation verification, the applicability and the effectiveness of the method are further confirmed.

Description

technical field [0001] The present invention relates to the invention belonging to the category of computer architecture, and in particular to Cache consistency of multiprocessor computer systems; multi-node multiprocessor computer systems; CC-NUMA (Cache Coherent Non-Uniform Memory Access——Cache Coherent Non-Uniform Memory Access Access) architecture; multi-level coherence domain and model test verification method of Cache Coherence protocol, specifically a multi-level coherence domain simulation verification and testing method based on extended Cache Coherence protocol. Background technique [0002] The current connection mode between multiprocessors has changed from bus connection to point-to-point connection, and the memory has also changed from being connected to the external bridge chip of the processor to being directly connected to the processor. Due to changes in memory mounting methods, the distribution of memory in the system also changes, resulting in non-uniform...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F11/26G06F12/0815G06F12/0837
CPCG06F12/0815G06F30/20G06F11/3608G06F11/3664G06F12/0837G06F2212/2542G06F2212/621
Inventor 王恩东胡雷钧陈继承张峰周恒钊符云越甘小伟
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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