1153results about "Functional testing" patented technology

The invention discloses a fault diagnosis method and device for a server, and relates to the technical field of electric digital data processing, and the method comprises the steps: collecting the actual operation data of a target server, obtaining the configuration information and historical fault data, and detecting whether the target server breaks down or not; when a fault occurs, inputting the configuration information, the actual operation data and the historical fault data into a pre-constructed fault path generation model so as to output a corresponding diagnosis path; and determining a diagnosis rule, a diagnosis label and a fault type when the target server is diagnosed according to the diagnosis path to generate a current fault diagnosis result, thereby solving the technical problems that the flow is solidified and single, the dynamic adjustment cannot be realized, the flexibility and pertinence are lacked, the diagnosis efficiency is low and the diagnosis precision is poor, and achieving the purposes of shortening the diagnosis time and improving the diagnosis efficiency. The server energy consumption and maintenance cost are reduced, the fault positioning accuracy is improved, the fault solving time is shortened, and the technical effect of automatic fault diagnosis is achieved.

The invention discloses a solid state disk performance fluctuation test method, device and equipment and a storage medium, and relates to the technical field of performance tests.A corresponding test action sequence is generated according to a performance test instruction, a plurality of test actions are organized into a standard test process capable of being repeatedly executed, and the performance fluctuation test efficiency is improved. The influence of the difference of manual test operation execution on the test result is eliminated, the performance fluctuation test result of the to-be-tested solid state disk is calculated based on the storage performance index of the to-be-tested solid state disk in the test action sequence execution process, and objective evaluation of the performance fluctuation of the solid state disk is realized on the basis of sufficient data support. The automation and standardization of the test are realized from the two aspects of the test process and the result evaluation, and the efficiency and accuracy of the test are improved.

Disclosed are various embodiments for identifying fault injection impact zones. A test for an application can be received from a test service. An application schema can then be created that represents the systems or services that are involved in the execution of the application. Applications with a similar application schema are then identified using a first machine-learning model. A subset of the plurality of applications that have experienced a similar test are then identified with a second machine-learning model. Log files associated with each of the subset of applications are then analyzed to identify errors that occurred during the similar test. Each of the identified errors are then provided to the test service in response to receipt of the test.

The invention discloses a test method of a storage link, electronic equipment, a storage medium and a program product, and relates to the technical field of storage networks, and the test method comprises the following steps: initializing a plurality of controller nodes in a storage server to form one or more controller groups, and networking the controller groups to a storage cluster; configuring a switch partition matched with the current state of the port virtualization function of the controller group; verifying a routing path between the host and the storage cluster according to a first mapping relationship between the physical port and the virtual port, the current state and the switch partition; the routing path comprises a second mapping relation between the host and the physical port and a third mapping relation between the host and the virtual port, namely, the storage link between the host and the storage cluster can be tested. The technical problems that virtual port management is complex and manual configuration is prone to errors are solved, and the technical effects that the test coverage rate and efficiency are improved, and the system reliability and flexibility are enhanced are achieved.

The present invention relates to the technical field of automobile curved screen detection, and in particular to a device and method for detecting the response time of an automobile curved screen, the method comprising: optimizing and affine transforming pixels on a two-dimensional plane image obtained by a 2D camera to obtain corresponding three-dimensional position information of the curved screen; determining the three-dimensional position information of a target icon on the automobile curved screen by a 3D camera, controlling a mechanical arm to accurately click the target icon on the automobile curved screen according to navigation coordinates, synchronously starting high-frame rate cameras set in different directions, obtaining continuous images and time information of changes in different areas of the curved screen when the mechanical arm operates on the automobile curved screen; inputting into a response time detection algorithm for analysis, and evaluating the response time performance of the automobile curved screen according to the output result of the response time detection algorithm. The present invention can realize accurate detection of the response time of an automobile curved screen.

Systems and methods for assessing display health in response to accidents are described. In some embodiments, an Information Handling System (IHS) may include an Embedded Controller (EC) and a memory coupled to the EC, where the memory comprises program instructions that, upon execution by the EC, cause the IHS to initiate an integrated display's Built-In-Self-Test (BIST) in response to a determination that the IHS suffered an accident.

The invention discloses a central processing unit power supply efficiency test method and device, electronic equipment and a medium, and relates to the technical field of server hardware testing, and the method comprises the steps: generating a plurality of test loads and a plurality of temperature test scenes if a data synchronous collection signal is detected, and carrying out the testing of the power supply efficiency of a central processing unit based on a preset traversal strategy; all power supply states of the central processing unit are traversed according to various test loads and various temperature test scenes, load change data, power supply data and temperature data of the central processing unit in the traversing process are collected, the data are packaged, and power supply efficiency test data can be obtained. And obtaining a central processing unit power supply efficiency test result according to the power supply efficiency test data. Therefore, by automatically adjusting the test load and the temperature test scene, the real business scene is simulated, the problem that the prior art depends on a fixed load mode and cannot reflect the dynamic frequency / voltage regulation characteristic of the CPU in the real scene is solved, and the technical effects of high test efficiency and high accuracy are achieved.

The invention discloses a computer system and a measurement method thereof and a medium, and the method comprises the steps: determining KPIs in a specific application scene, and setting a specific performance threshold value; the method comprises the following steps: performing data acquisition on a virtual machine node of a computer system by using an AI-based dynamic sampling technology; filtering and cleaning the collected data, and automatically marking abnormal data points through a K-means clustering algorithm; performing real-time performance prediction based on an LSTM neural network, identifying a performance bottleneck, and performing partial preliminary analysis at a virtual machine end by adopting an edge computing technology; according to a real-time data analysis result, KPI index parameters are dynamically adjusted, and a prediction result and an actual operation condition are fed back to the LSTM neural network model; and generating a chart and an analysis report based on natural language processing by using a data visualization tool, and displaying a measurement analysis result. According to the invention, through an intelligent feedback mechanism, monitoring index parameters are dynamically adjusted, a prediction result is compared with an actual operation condition, and a monitoring model is continuously optimized, so that system monitoring is more accurate and efficient.

The invention discloses a data recovery test method, which comprises the following steps of: performing fault injection on a storage system to enable the storage system to enter a recovery state; determining a target test scene in the recovery state, and performing a performance recovery test on the storage system in the target test scene; estimating a target duration for the storage system to enter a stable state in the performance recovery test process; after waiting for the target duration, collecting target performance data of the storage system for verification, and determining a test result of the target test scene according to a verification result; and determining a data recovery test result according to the test result of each target test scene. By applying the technical scheme provided by the invention, more efficient and accurate data recovery performance testing can be realized for the storage system. The invention also discloses a data recovery test device, electronic equipment and a computer readable storage medium, which also have the above technical effects.

Techniques pertaining to generative artificial intelligence (GAI)-based random test generation framework for processor verification are described. An apparatus generates one of more random test cases with an aid of a GAI-assisted random verification program (GRVP) framework. The apparatus also performs validation testing on a design of a processor using the one or more random test cases.

Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an integrated circuit has a logic path formed in the integrated circuit. A monitor circuit is formed in the integrated circuit near the logic path and configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to determine a condition of the integrated circuit based on the diagnostic code sequence, and to initiate a remedial action in response to the condition of the integrated circuit.

The invention discloses a verification method for a second-level cache interface protocol, which belongs to the technical field of multi-core verification, and comprises the following steps of: setting verification targets, including function correctness, performance standard, compatibility and exception handling capacity; establishing a verification environment, wherein the verification environment comprises a hardware platform and a test tool; function verification, including read-write operation verification, cache line state transition verification and consistency verification; performance verification including delay testing and bandwidth testing; the compatibility verification comprises the compatibility with a first-level cache and the compatibility with a processor core; the abnormal condition verification comprises interrupt processing verification and error injection verification; and analyzing a test result. According to the verification method for the second-level cache interface protocol, the second-level cache interface protocol can be comprehensively and deeply verified, the function correctness, the performance standard reaching performance and the compatibility with other components of the second-level cache interface protocol are ensured, and a solid guarantee is provided for stable operation of a high-performance computer system.

According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.

A system can include a memory and a processing device, operatively coupled to the memory, to perform operations including receiving, from a storage device, a data block of a blockchain, wherein the data block includes a data block payload comprising test data of an in-system test to be performed on a target device, which is external with respect to the storage device, determining whether the data block is valid by authenticating the data block, and in response to determining that the data block is valid, performing the in-system test on the target device by processing at least a portion of the test data extracted from the data block payload.

The invention discloses an NAND block health degree prediction method and system based on read interference perception. The method comprises the steps that read interference event counts of an NAND flash memory block are collected in real time; dynamically triggering multi-dimensional parameter acquisition to generate multi-dimensional parameter data with timestamps; extracting a dynamic change rate, a distribution entropy value and a growth slope feature based on the multi-dimensional parameters, and generating a compression feature matrix; inputting the compressed feature matrix into a pre-trained graph neural network-Hamiltonian Monte Carlo hybrid model, outputting a health degree score and recording a low-confidence sample; based on the health degree score and the historical health degree attenuation trajectory, generating an early warning level signal through a dynamic threshold engine; executing a corresponding block maintenance strategy according to the early warning level, and recording strategy execution effect data; and model parameters are updated through knowledge distillation by utilizing a low-confidence sample and strategy execution effect data, so that level-by-level and cross-level health risks of the NAND flash memory based on read interference perception are truly and accurately reflected.

A computer-implemented method and a processing module for identifying that a fault has occurred in a finite-state machine (FSM). It is determined whether a set of one or more transitions that have occurred between states of the FSM is allowable. In response to determining that the set of one or more transitions is not allowable, it is identified that a fault has occurred in the FSM.

According to the automatic test error-proofing detection method and detection system disclosed by the invention, after a test instruction is received, verification requests generated by bar codes of a needle bed upper mold and a needle bed lower mold are received; sending to a selected product test program to judge whether the needle bed upper die and the needle bed lower die and whether the needle bed name is matched with the current product test program or not; if not, stopping the test, otherwise, after the to-be-tested product is placed in place, receiving a serial number of the to-be-tested product generated by the bar code of the to-be-tested product, and querying and obtaining internal card binding information of the corresponding to-be-tested product; controlling the test tool to start and electrify the to-be-tested product, acquiring identity information of an internal clamping piece actually mounted in the to-be-tested product, comparing the identity information with inquired binding information of the internal clamping piece, if the identity information is consistent with the binding information of the internal clamping piece, carrying out subsequent function test, otherwise, sending error information of the internal clamping piece, and controlling the test tool to pull open an upper die and a lower die of the needle bed; therefore, automatic error-proofing detection of each module test of the industrial control system is realized.

The invention belongs to the related technical field of microelectronics, and discloses an in-memory array testing device capable of flexibly pulsing and a control method thereof, the device comprises a daughter board array, and each daughter board comprises a chip seat, a digital-to-analog conversion module, a driving module, a differential reading module, an analog-to-digital conversion module, a shift accumulation module, a first bidirectional interface, a second bidirectional interface, a third bidirectional interface and a fourth bidirectional interface; the chip seat is used for placing an in-memory array chip; the digital-to-analog conversion module converts an input vector into a voltage signal, and the driving module provides a driving current; the differential reading module comprises two anti-phase amplification circuits and an addition and subtraction circuit, the results of the chip in the memory are subjected to differential sampling and then output to the analog-to-digital conversion module for analog-to-digital conversion, and the shift accumulation module is used for performing shift accumulation on the analog-to-digital conversion results and digital signals of other daughter boards to obtain result vectors. Based on the testing device, the chip in the memory can be tested, and the flexibility is high.

The invention relates to an independent AC cycle restart test method and system for a production test server. The method comprises the following steps: determining whether a tested server is ready to be put on shelf or not; starting the test script, and reading the position information; obtaining PDU binding information to obtain a PDU address and power supply interface information thereof; carrying out a connection test on the PDU and the tested server to determine that the tested server is correctly connected with the PDU power supply interface; and executing an AC loop restart test on the tested server. According to the invention, the physical position of the production test server and the binding relation between the intelligent PDU IP of the corresponding server and the power supply interface can be positioned, the power-on and power-off of the power supply of a certain production test server can be accurately controlled, and the tested servers can be independently operated and tested.

The invention relates to the technical field of embedded system testing, in particular to a method for testing functionality and stability of a core board service component, which comprises the following steps of: initializing a core board testing environment, ensuring that software and hardware parameters are consistent in a testing process, and aiming at the service component on a core board, testing the service component on the core board; the method comprises the following steps of: analyzing and generating a dependency relationship graph among components by utilizing a dependency graph model, optimizing a key dependency relationship through a deep learning model, performing functional testing on the components according to a priority based on the optimized dependency relationship graph, and testing the stability of a core board during high-concurrency and multi-task operation through multi-thread scheduling and concurrent task simulation. Abnormal, resource competition and deadlock problems are detected; and finally, in combination with an actual application scene, carrying out component hot plug, network abnormity, power-off recovery and other scene tests, and analyzing test data to generate a comprehensive test report. According to the method, the test coverage rate and efficiency are improved, and stable operation of the system under complex conditions is ensured.

The invention discloses an automatic verification excitation generation method based on a backtracking thinking tree, and the method comprises the steps: constructing a backtracking thinking tree frame based on a self-feedback mechanism based on a thinking tree for a to-be-verified processor function; under the backtracking thinking tree framework, decoupling a to-be-verified function from top to bottom through a large language model, and recursively decomposing the whole to-be-verified function into function points capable of being independently verified layer by layer through a tree structure; according to each function point, determining a normal function and a boundary of each function point, and for each function point, generating verification excitation layer by layer in a tree structure; after the verification excitation is generated, self-verification and self-backtracking are carried out layer by layer through a tree structure, and finally, the generated verification excitation is executed on the processor design to verify the correctness of the processor function. According to the method and the system, the function verification efficiency and the verification coverage rate of the processor are remarkably improved.

The invention relates to the technical field of memory bank testing, and discloses a server mainboard memory bank plugging and unplugging test system which comprises a mechanical plugging and unplugging module, a sensor module, a pre-detection module, a test analysis module and a result display module.According to the server mainboard memory bank plugging and unplugging test system, automatic operation is achieved through the mechanical plugging and unplugging module, and accuracy and efficiency are improved; the sensor module adopts a four-wire system resistance measurement sensor, the contact resistance is accurately measured, and the contact detection precision is guaranteed; the pre-detection module can screen out memory banks with appearance scratches in advance from multi-angle image acquisition and equal-interval grid division to accurate pixel value analysis by utilizing a scientific appearance detection process; the test analysis module comprehensively evaluates the performance, the contact state judgment is clear, and the memory read-write and stability test is rigorous and scientific; a test report generated by the result display module visually shows results of scratch, contact, read-write, stability and the like, comprehensive information is provided for operators, and efficient judgment of the performance of the memory bank is assisted.

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an FPGA software and hardware cooperation testing platform based on a BFM. The test platform is formed by connecting a BFM with a Testbench, an AXI bus, an off-chip DDR and a DUT. The test process comprises the steps that the Testbench issues parameters through a transaction function interface, the BFM reads an excitation vector from the off-chip DDR / on-chip BRAM through an Avalon main interface, adaptive transmission of a system bus clock domain and a DUT clock domain is completed through double asynchronous FIFO (SNDfifo / RECfifo), and signal level interaction with the DUT is achieved through a pin protocol interface; the state machine dynamically switches long and short simulation modes according to the vector length, and drives the output vector to be written back and stored; the error monitoring unit monitors data flow faults in the whole process and outputs seven types of error reporting codes. The simulation equivalent frequency reaches a 10 megahertz level, and the method is suitable for efficient verification of the digital IC.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

The invention relates to a GPU verification system, method and device, electronic equipment, a storage medium and a program product. The system comprises a specified platform end and a reference platform end, and the specified platform end is provided with a to-be-verified GPU; the specified platform end is used for running a test case, executing a test task in the test case based on a to-be-verified GPU through the test case to obtain a test result of the test case at the specified platform end, and sending test related data of the specified platform end to the reference platform end, the test related data at least comprises information of the test case and the test result; the reference platform end is used for determining the test case according to the test related data, obtaining the test result from the test related data, running the test case to obtain a first reference result of the test case at the reference platform end, comparing the first reference result with the test result, and sending the test result to the reference platform end; and obtaining a first verification result corresponding to the to-be-verified GPU.

In a stacked integrated circuit device, there are two components, one in a first of the die and another in a second of the die. Each of the components is provided with two output connections, one leading above and one leading below the die, and two input connections, one leading above and one leading below the die, either of the two die. As a result of the redundancy, both die may be used in either position in the stacked structure. If either of the die is used as the top die, it sends data on its second output path and receives data on its second input path. On the other hand, when one of the die is used as the bottom die, it sends data on its first output path and receives data on its first input path. In this way, the same design may be used for the connections between each of the die.

Example embodiments of the present disclosure relate to a method, a device and a non-transitory computer-readable medium for distributed training. The method comprises obtaining, during a distributed training task performed across a plurality of computing nodes, at least one heartbeat message from the plurality of computing nodes, each computing node including multiple GPU workers; detecting, based on the at least one heartbeat message, an abnormal status of the distributed training task; commanding the plurality of computing nodes to run at least one self-check diagnostics test; identifying, based on results of the at least one self-check diagnostics test, at least one faulty node from the plurality of computing nodes; and replacing the at least one faulty node with an equivalent number of heathy computing nodes that have passed the at least one self-check diagnostics test.

The invention discloses an FAKRA wire harness error code testing device and method, and relates to the technical field of error code testing. The method comprises the following steps of preparation before test, basic electrical test, limit plugging test, vibration test, stability test and test result analysis. According to the method, the initial bit error rate of the to-be-tested FAKRA wire harness is tested by using the bit error tester after the test equipment is calibrated, then the connectors at the two ends and the matched connector are subjected to the limit plugging test, then the vibration test is performed, and the simulation degree of the vibration test is evaluated, so that whether vibration simulation optimization is performed or not is determined; according to the method and the device, firstly, the fluctuation condition of the bit error rate is monitored in the test period, so that whether a clock optimization measure is taken or not is determined, finally, all test data are collected, the stability of the bit error test is ensured, and the problem that the bit error test accuracy is reduced due to the fact that the vibration test simulation degree is not high enough and the simulation quality is unstable in the prior art is solved.