503results about "Functional testing" patented technology

The invention discloses an NAND block health degree prediction method and system based on read interference perception. The method comprises the steps that read interference event counts of an NAND flash memory block are collected in real time; dynamically triggering multi-dimensional parameter acquisition to generate multi-dimensional parameter data with timestamps; extracting a dynamic change rate, a distribution entropy value and a growth slope feature based on the multi-dimensional parameters, and generating a compression feature matrix; inputting the compressed feature matrix into a pre-trained graph neural network-Hamiltonian Monte Carlo hybrid model, outputting a health degree score and recording a low-confidence sample; based on the health degree score and the historical health degree attenuation trajectory, generating an early warning level signal through a dynamic threshold engine; executing a corresponding block maintenance strategy according to the early warning level, and recording strategy execution effect data; and model parameters are updated through knowledge distillation by utilizing a low-confidence sample and strategy execution effect data, so that level-by-level and cross-level health risks of the NAND flash memory based on read interference perception are truly and accurately reflected.

The invention discloses an automatic verification excitation generation method based on a backtracking thinking tree, and the method comprises the steps: constructing a backtracking thinking tree frame based on a self-feedback mechanism based on a thinking tree for a to-be-verified processor function; under the backtracking thinking tree framework, decoupling a to-be-verified function from top to bottom through a large language model, and recursively decomposing the whole to-be-verified function into function points capable of being independently verified layer by layer through a tree structure; according to each function point, determining a normal function and a boundary of each function point, and for each function point, generating verification excitation layer by layer in a tree structure; after the verification excitation is generated, self-verification and self-backtracking are carried out layer by layer through a tree structure, and finally, the generated verification excitation is executed on the processor design to verify the correctness of the processor function. According to the method and the system, the function verification efficiency and the verification coverage rate of the processor are remarkably improved.

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an FPGA software and hardware cooperation testing platform based on a BFM. The test platform is formed by connecting a BFM with a Testbench, an AXI bus, an off-chip DDR and a DUT. The test process comprises the steps that the Testbench issues parameters through a transaction function interface, the BFM reads an excitation vector from the off-chip DDR / on-chip BRAM through an Avalon main interface, adaptive transmission of a system bus clock domain and a DUT clock domain is completed through double asynchronous FIFO (SNDfifo / RECfifo), and signal level interaction with the DUT is achieved through a pin protocol interface; the state machine dynamically switches long and short simulation modes according to the vector length, and drives the output vector to be written back and stored; the error monitoring unit monitors data flow faults in the whole process and outputs seven types of error reporting codes. The simulation equivalent frequency reaches a 10 megahertz level, and the method is suitable for efficient verification of the digital IC.

Example embodiments of the present disclosure relate to a method, a device and a non-transitory computer-readable medium for distributed training. The method comprises obtaining, during a distributed training task performed across a plurality of computing nodes, at least one heartbeat message from the plurality of computing nodes, each computing node including multiple GPU workers; detecting, based on the at least one heartbeat message, an abnormal status of the distributed training task; commanding the plurality of computing nodes to run at least one self-check diagnostics test; identifying, based on results of the at least one self-check diagnostics test, at least one faulty node from the plurality of computing nodes; and replacing the at least one faulty node with an equivalent number of heathy computing nodes that have passed the at least one self-check diagnostics test.

The invention discloses an FAKRA wire harness error code testing device and method, and relates to the technical field of error code testing. The method comprises the following steps of preparation before test, basic electrical test, limit plugging test, vibration test, stability test and test result analysis. According to the method, the initial bit error rate of the to-be-tested FAKRA wire harness is tested by using the bit error tester after the test equipment is calibrated, then the connectors at the two ends and the matched connector are subjected to the limit plugging test, then the vibration test is performed, and the simulation degree of the vibration test is evaluated, so that whether vibration simulation optimization is performed or not is determined; according to the method and the device, firstly, the fluctuation condition of the bit error rate is monitored in the test period, so that whether a clock optimization measure is taken or not is determined, finally, all test data are collected, the stability of the bit error test is ensured, and the problem that the bit error test accuracy is reduced due to the fact that the vibration test simulation degree is not high enough and the simulation quality is unstable in the prior art is solved.

The invention provides a function test method and device, electronic equipment and a storage medium, and is applied to the technical field of computers, the method comprises the steps that after a test instruction for indicating a to-be-tested function of a target module is obtained, a target test case corresponding to the to-be-tested function is further obtained, and the target test case can call at least one preset test sequence; the preset test sequences comprise at least one test condition required for testing the to-be-tested function, finally calling each preset test sequence through the test case, constructing a verification scene for testing the to-be-tested function based on each test condition, and completing the test of the to-be-tested function. In addition, the test conditions included in any preset test sequence have no association relationship with other test conditions except the preset test sequence, and the preset test sequences of the to-be-tested function are mutually independent and can be called according to the test requirements in the test process, so that the function test efficiency can be effectively improved.

Techniques for assigning scenario-based tests to test assets are described. In an example, a scenario-based test operable to test a key performance indicator (KPI) of a System Under Test (SUT), a component behavior exhibited by a first component of the SUT, and a scenario characteristic are received. Based on the component behavior and the scenario characteristic, a first plurality of behavior models associated with the component behavior are identified. Based on the scenario characteristic a characteristic value is extracted from the scenario-based test. Each behavior model of the first plurality of behavior models is executed using the characteristic value to generate a first plurality of predicted behavior outcomes. Based on the first plurality of predicted behavior outcomes, a first test asset type from a plurality of test asset types is selected and the scenario-based test is transmitted to a test asset of the first test asset type.

The invention provides a memory channel detection circuit, device and method and a storage medium. The memory channel detection circuit comprises an interface, a signal acquisition module, a power supply module and a control module, the input end of the signal acquisition module is connected with the interface and the output end is connected with the control module; the power supply module is connected with the power end of the signal acquisition module and the power supply end of the control module and used for providing power voltage. Each memory channel is connected in series with a preset resistor; the interface is used for accessing a CPU or a memory bank; the signal acquisition module responds to a test instruction output by the control module, acquires partial voltage values corresponding to a plurality of memory channels, and outputs the partial voltage values to the control module; and the control module is used for determining whether the plurality of memory channels have faults or not according to the divided voltage values corresponding to the plurality of memory channels. According to the method, whether each memory channel is abnormal or not is judged by acquiring the partial voltage values corresponding to the plurality of memory channels, so that a large amount of time consumed by a traditional solution is saved.

The invention discloses a verification method and device for accelerating function coverage rate convergence, a medium and equipment, the method is applied to a verification platform, the verification platform comprises a directional excitation generator, a function coverage rate model and a to-be-tested design, and the verification platform is provided with a simulation switch. Comprising the following steps: analyzing a code file of a function coverage rate model by utilizing a preset cross use case script file to extract coverage bin information corresponding to a cross function coverage point, and configuring a simulation switch according to the coverage bin information to generate a boundary use case file; and reading switch configuration information in the boundary case file by using a directional excitation generator, generating a directional excitation flow based on the directional instruction sequence according to the switch configuration information, and sending the directional excitation flow to the design to be tested to execute verification work. By adopting the technical scheme of the invention, the boundary use case of the cross function coverage point can be automatically generated, so that the convergence time consumption of the function coverage rate is effectively reduced, and the convergence rate of the function coverage rate is improved.

The invention relates to an SPD hub chip testing method and device, equipment and a storage medium. The method comprises the steps that if it is determined that a to-be-tested SPD hub chip is placed in a replaceable limiting frame of a test seat and communication connection is established with an upper computer, target environment parameters are set, the to-be-tested SPD hub chip is initialized, the upper computer is in communication connection with the test seat, preset test data are written into an EEPROM of the SPD hub chip based on the target environment parameters, then read-back comparison is carried out, and the to-be-tested SPD hub chip is initialized; the static verification data is used for judging the static storage reliability of the to-be-tested SPD hub chip in the current environment, executing continuous read-write operation on the to-be-tested SPD hub chip to obtain a dynamic pressure test data set, and generating a test result of the to-be-tested SPD hub chip based on the static verification data and the dynamic pressure test data set.

Temperature-aware built-in self-test (BIST) control system for selectively controlling activation of BIST circuits in a processor-based system to maintain temperature limit and related methods. The temperature-aware BIST control system is configured to selectively control the number of BIST circuits in the processor-based system activated during the same time based on a temperature limit indicator related to a sensed temperature(s) in the processor-based system and whether such is within a defined temperature threshold(s) and / or temperature change rate threshold(s), which may be programmable. In this manner, the safety manager circuit can dynamically and selectively control the number of BIST circuits activated based on temperature according to the BIST control policy(ies) to reduce or avoid circuit failures due to excess temperature, while at the same time maximizing the staggering (i.e., overlapping) of BIST circuit activations to maximize testing speed.

In some examples, a system monitors for a memory fault associated with execution of software. Based at least on receiving an indication of a possible memory fault, the system scans a first area of the memory based on a data structure that indicates that the first area of the memory stores a portion of parameters of the software that affect an accuracy of the software if there is a memory fault in the first area of the memory. Based at least on the scanning indicating that there is a memory fault in the first area of the memory, the system remaps the portion of parameters of the software from the first area to a second area of the memory that is determined to be free.

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

The invention belongs to the technical field of computers, and particularly relates to a dynamically configured cockpit host video test multiplexing method. The method aims at solving the problems that a traditional testing means is poor in universality, incomplete in coverage and low in automation degree. A structural equipment description file is constructed by analyzing a host technical document, an adaptive dynamic test configuration template is automatically generated in combination with a test case library, and flexible configuration of multi-channel video stream parameters, abnormal injection modes and time sequence logic is supported. A containerized virtual signal source is deployed on a universal computing platform, and an analog video stream conforming to an input specification is generated in real time. Through the equipment description driving and virtualization signal generation technology, the multiplexing capability and coverage integrity of the testing system are improved, efficient and automatic testing of multiple types of hosts is achieved, and the hardware cost and the deployment period are remarkably reduced.

The invention discloses an STDF file offline generation method and system suitable for various ATEs. The method comprises the steps that the composition sequence of STDF files is determined; acquiring a configuration file, wherein the configuration file comprises batch information, wafer information, test site configuration information, pin configuration information, hardware Bin definition and software Bin definition; analyzing ATE native test data, and obtaining a chip test start mark, multiple types of test item results and a chip test result; checking whether the first test site information is consistent with the second test site information or not, and checking whether hardware Bin information and software Bin information in a chip test result accord with a hardware Bin definition and a software Bin definition in a configuration file or not; and when all the verification results pass, generating an STDF file according to a composition sequence based on the configuration file, the chip test start mark, the test item result and the chip test result. The test efficiency can be improved, and the supply chain cost can be reduced.

Systems and methods for assessing display health in response to accidents are described. In some embodiments, an Information Handling System (IHS) may include an Embedded Controller (EC) and a memory coupled to the EC, where the memory comprises program instructions that, upon execution by the EC, cause the IHS to initiate an integrated display's Built-In-Self-Test (BIST) in response to a determination that the IHS suffered an accident.

Methods, systems, and apparatus, including computer-readable storage media for handling component error of datacenter infrastructure by training machine learning models to handle errors when the models are deployed. Rather than predict or mitigate errors in the hardware of a datacenter or another site deploying the machine learning model, the model is trained to perform a task with comparable accuracy and efficiency even when some hardware on which the model is deployed fails. Component error can instead be simulated during training to cause the machine learning model deployed on the infrastructure to learn to correct errors caused by the component errors. The model can continue to be trained to compensate for periods in which not all parts of the model are available at inference. Updates to the model can be backpropagated to correct errors for handling instances of component error.

Systems and methods for handling communications between a host Operating System (OS) application and a display controller through an Embedded Controller (EC) are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive, by a kernel driver of a host OS, a message from a host OS application; and at least in part in response to a determination that the processor comprises a Reduced Instruction Set Computer (RISC) processor, send a request to an EC, where the request is configured to cause the EC to trigger a display's Built-In Self-Test (BIST) by a display controller.

A method for testing at least one electronic control device as a virtual control device on a simulator having at least one simulator arithmetic unit is described and shown, wherein the electronic control device has a hardware configuration comprising at least one arithmetic unit and an external interface for exchanging data and a software configuration assigned to the hardware configuration, the software configuration comprising internal functions and external interface functions, the electronic control device being mapped to the virtual control device in such a way that the internal functions of the software configuration of the electronic control device assume the internal functions of the software configuration of the virtual control device and in such a way that the external interface functions of the electronic control device are replaced by data transfer functions of a software configuration of the simulator arithmetic unit, the software configuration of the virtual control device being converted into executable code for the simulator arithmetic unit and executed on the simulator.

A method (10) is proposed for automatically checking whether an input signal (In-Bus) of a control device (21) of a vehicle is potentially related to on-board diagnostics. The method (10) comprises using (11) a signal network representing a signal flow in said control device (21) including an input signal (In-Bus) and an output signal (Out-Bus) related to on-board diagnostics. Furthermore, verifying (12) whether there is a signal coupling (22, 23) between the input signal (In-Bus) and at least one output signal (Out-Bus) related to on-board diagnostics, and indicating (13) that the input signal (In-Bus) is potentially related to on-board diagnostics when there is a signal coupling (22, 23) between the input signal (In-Bus) and at least one output signal (Out-Bus). This method may be advantageous since it is no longer necessary to precisely check all input signals, but instead only those input signals that are automatically indicated (13) as potentially related to OBD.

When values of physical operating parameters can be changed without rebooting the computing platform, latency of in-system test (IST) execution of hardware components of a field (deployed) computing platform can be reduced. Tests (e.g., patterns or vectors) are executed for changed values of physical operating parameters (e.g., supply voltage, clock speed, temperature, noise magnitude / duration, operating current, etc.) to provide the ability to detect faults in hardware components.

This invention provides an on-chip FLASH functional testing system based on an off-chip SPI master, relating to the field of integrated circuit and memory control technology. The system receives operation commands and corresponding data from an off-chip SPI master via on-chip SPI and transmits them to a controller with an independent SPI interface for the on-chip FLASH. The controller executes corresponding operations on the on-chip FLASH based on the operation commands and data, and transmits the execution results back to the off-chip SPI master via on-chip SPI. The off-chip SPI master generates functional test results for the on-chip FLASH based on the execution results fed back by the controller. The controller of this invention enables the off-chip SPI master to access and functionally test the on-chip FLASH in the same way as the off-chip FLASH. The entire testing process is transparent to the upper-layer system, requiring no additional adaptation logic, significantly improving the simplicity of the testing process and the system integration.

Example embodiments of the present disclosure relate to a method, a device and a non-transitory computer-readable medium for distributed training The method comprises obtaining, during a distributed training task performed across a plurality of computing nodes, at least one heartbeat message from the plurality of computing nodes, each computing node including multiple GPU workers; detecting, based on the at least one heartbeat message, an abnormal status of the distributed training task; commanding the plurality of computing nodes to run at least one self-check diagnostics test; identifying, based on results of the at least one self-check diagnostics test, at least one faulty node from the plurality of computing nodes; and replacing the at least one faulty node with an equivalent number of heathy computing nodes that have passed the at least one self-check diagnostics test.

The invention belongs to the technical field of vehicle control, and particularly provides a vehicle-mounted peripheral stability test method, a medium and a vehicle, and the method comprises the steps: obtaining target identification information in a vehicle-mounted system, and positioning a to-be-tested target external device based on the target identification information; starting an automatic loop test for the target external equipment, wherein the automatic loop test comprises alternately executing equipment mounting operation and equipment unloading operation; monitoring the running state of the target external equipment and the resource state of the vehicle-mounted system in real time in the automatic cycle test process; and generating a test log based on the running state and the resource state, and determining a stability evaluation result of the target external equipment according to the test log. Through the technical scheme provided by the invention, the stability testing efficiency of the vehicle-mounted peripheral can be improved.

A fault detection method and apparatus, and an intelligent driving device are disclosed. The method includes: obtaining information about a first test pattern, where the first test pattern is a to-be-run test pattern, and the first test pattern is used to detect a fault of an integrated circuit; and adjusting, to a target frequency based on the first test pattern, a running frequency of a processor configured to run the first test pattern, so that when the processor runs the first test pattern at the target frequency, a running speed of the first test pattern can be increased or power consumption required for running the first test pattern can be reduced. The technical solutions of this application may be applied to the intelligent driving device, to adjust a running frequency of a processor based on an STL test pattern, thereby achieving a balance between a fault detection speed and required power consumption.

This invention relates to a method for verifying a memory device. The method includes verifying a second memory device based on one or more first microcode instructions stored in a predetermined portion of the verification of a first memory device to detect the operating state of the second memory device. Furthermore, the method includes receiving one or more second microcode instructions after verifying the second memory device. Finally, the first memory device is verified based on the one or more second microcode instructions stored in the second memory device to detect the operating state of the first memory device.

A universal asynchronous receiver / transmitter includes a transmit register including information to be transmitted, a receive register including received information, a frame error check circuit that evaluates contents of the receive register for a frame error, and a control logic. The control logic routes contents of the transmit register to the receive register. During transmission of the contents of the transmit register to the receive register through a reprogrammable pin, the control logic modifies a bit inversion register to produce modified contents to be provided to the receive register. The modified contents cause a frame error. The control logic determines whether the frame error check circuit detects the frame error.

System testing is described. An example system testing method includes: acquiring module relationship information for a system under test, the system under test including a plurality of modules, the module relationship information indicating a logical relationship between each two of the plurality of modules; and testing at least two modules in the system under test based on the module relationship information, the at least two modules being associated with each other for the same function implemented by the system under test. By use of the technical solution of the present disclosure, both system and module perspectives can be applied to system integration testing, so as to achieve a more comprehensive system testing coverage and find problems in the system under test as soon as possible, which can help to improve the system testing coverage and system testing efficiency.

An apparatus and method for high heat functionality testing of a remote radio head unit is shown and described. The apparatus includes a chamber having a door and a plurality of walls creating an interior volume. At least two vents attached to the chamber such that air can enter and exit the chamber. A computer operably coupled to an apparatus system. A thermometer secured within the chamber which is operably coupled to the computer via the apparatus system. At least one fan secured to at least one of the vents. Each of the at least one fan is operably coupled to the computer via the apparatus system. A plurality of electrical and network connections to allow for a remote radio head unit to be operably coupled to the electrical connections and receive proper power and to be operably coupled to the computer via the apparatus system through the network connections.

The invention discloses a startup and shutdown test system and method based on a VPX calculation module, and the method comprises the steps: transmitting a power-on instruction to an intelligent switching power supply through test software, so as to control the intelligent switching power supply to power on the VPX calculation module; the test software monitors and receives a handshake signal sent by the VPX calculation module after the VPX calculation module is started; after the handshake signal is received, waiting for a preset shutdown completion time, and sending a power-off instruction to the intelligent switching power supply by the test software so as to control the intelligent switching power supply to power off the VPX calculation module; after it is confirmed that the intelligent switching power supply is powered off, waiting for a preset test interval time, and sending a power-on instruction to the intelligent switching power supply again; and on the basis of a preset number of times, cyclically executing the startup and shutdown test on the VPX calculation module. Unattended operation, accurate time sequence control and data recording of VPX module startup and shutdown testing are achieved, and testing efficiency, consistency and traceability are remarkably improved.