853results about "Functional testing" patented technology

The invention discloses a fault diagnosis method and device for a server, and relates to the technical field of electric digital data processing, and the method comprises the steps: collecting the actual operation data of a target server, obtaining the configuration information and historical fault data, and detecting whether the target server breaks down or not; when a fault occurs, inputting the configuration information, the actual operation data and the historical fault data into a pre-constructed fault path generation model so as to output a corresponding diagnosis path; and determining a diagnosis rule, a diagnosis label and a fault type when the target server is diagnosed according to the diagnosis path to generate a current fault diagnosis result, thereby solving the technical problems that the flow is solidified and single, the dynamic adjustment cannot be realized, the flexibility and pertinence are lacked, the diagnosis efficiency is low and the diagnosis precision is poor, and achieving the purposes of shortening the diagnosis time and improving the diagnosis efficiency. The server energy consumption and maintenance cost are reduced, the fault positioning accuracy is improved, the fault solving time is shortened, and the technical effect of automatic fault diagnosis is achieved.

The invention discloses a central processing unit power supply efficiency test method and device, electronic equipment and a medium, and relates to the technical field of server hardware testing, and the method comprises the steps: generating a plurality of test loads and a plurality of temperature test scenes if a data synchronous collection signal is detected, and carrying out the testing of the power supply efficiency of a central processing unit based on a preset traversal strategy; all power supply states of the central processing unit are traversed according to various test loads and various temperature test scenes, load change data, power supply data and temperature data of the central processing unit in the traversing process are collected, the data are packaged, and power supply efficiency test data can be obtained. And obtaining a central processing unit power supply efficiency test result according to the power supply efficiency test data. Therefore, by automatically adjusting the test load and the temperature test scene, the real business scene is simulated, the problem that the prior art depends on a fixed load mode and cannot reflect the dynamic frequency / voltage regulation characteristic of the CPU in the real scene is solved, and the technical effects of high test efficiency and high accuracy are achieved.

Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an integrated circuit has a logic path formed in the integrated circuit. A monitor circuit is formed in the integrated circuit near the logic path and configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to determine a condition of the integrated circuit based on the diagnostic code sequence, and to initiate a remedial action in response to the condition of the integrated circuit.

The invention discloses an NAND block health degree prediction method and system based on read interference perception. The method comprises the steps that read interference event counts of an NAND flash memory block are collected in real time; dynamically triggering multi-dimensional parameter acquisition to generate multi-dimensional parameter data with timestamps; extracting a dynamic change rate, a distribution entropy value and a growth slope feature based on the multi-dimensional parameters, and generating a compression feature matrix; inputting the compressed feature matrix into a pre-trained graph neural network-Hamiltonian Monte Carlo hybrid model, outputting a health degree score and recording a low-confidence sample; based on the health degree score and the historical health degree attenuation trajectory, generating an early warning level signal through a dynamic threshold engine; executing a corresponding block maintenance strategy according to the early warning level, and recording strategy execution effect data; and model parameters are updated through knowledge distillation by utilizing a low-confidence sample and strategy execution effect data, so that level-by-level and cross-level health risks of the NAND flash memory based on read interference perception are truly and accurately reflected.

The invention discloses an automatic verification excitation generation method based on a backtracking thinking tree, and the method comprises the steps: constructing a backtracking thinking tree frame based on a self-feedback mechanism based on a thinking tree for a to-be-verified processor function; under the backtracking thinking tree framework, decoupling a to-be-verified function from top to bottom through a large language model, and recursively decomposing the whole to-be-verified function into function points capable of being independently verified layer by layer through a tree structure; according to each function point, determining a normal function and a boundary of each function point, and for each function point, generating verification excitation layer by layer in a tree structure; after the verification excitation is generated, self-verification and self-backtracking are carried out layer by layer through a tree structure, and finally, the generated verification excitation is executed on the processor design to verify the correctness of the processor function. According to the method and the system, the function verification efficiency and the verification coverage rate of the processor are remarkably improved.

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an FPGA software and hardware cooperation testing platform based on a BFM. The test platform is formed by connecting a BFM with a Testbench, an AXI bus, an off-chip DDR and a DUT. The test process comprises the steps that the Testbench issues parameters through a transaction function interface, the BFM reads an excitation vector from the off-chip DDR / on-chip BRAM through an Avalon main interface, adaptive transmission of a system bus clock domain and a DUT clock domain is completed through double asynchronous FIFO (SNDfifo / RECfifo), and signal level interaction with the DUT is achieved through a pin protocol interface; the state machine dynamically switches long and short simulation modes according to the vector length, and drives the output vector to be written back and stored; the error monitoring unit monitors data flow faults in the whole process and outputs seven types of error reporting codes. The simulation equivalent frequency reaches a 10 megahertz level, and the method is suitable for efficient verification of the digital IC.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

In a stacked integrated circuit device, there are two components, one in a first of the die and another in a second of the die. Each of the components is provided with two output connections, one leading above and one leading below the die, and two input connections, one leading above and one leading below the die, either of the two die. As a result of the redundancy, both die may be used in either position in the stacked structure. If either of the die is used as the top die, it sends data on its second output path and receives data on its second input path. On the other hand, when one of the die is used as the bottom die, it sends data on its first output path and receives data on its first input path. In this way, the same design may be used for the connections between each of the die.

Example embodiments of the present disclosure relate to a method, a device and a non-transitory computer-readable medium for distributed training. The method comprises obtaining, during a distributed training task performed across a plurality of computing nodes, at least one heartbeat message from the plurality of computing nodes, each computing node including multiple GPU workers; detecting, based on the at least one heartbeat message, an abnormal status of the distributed training task; commanding the plurality of computing nodes to run at least one self-check diagnostics test; identifying, based on results of the at least one self-check diagnostics test, at least one faulty node from the plurality of computing nodes; and replacing the at least one faulty node with an equivalent number of heathy computing nodes that have passed the at least one self-check diagnostics test.

The invention discloses an FAKRA wire harness error code testing device and method, and relates to the technical field of error code testing. The method comprises the following steps of preparation before test, basic electrical test, limit plugging test, vibration test, stability test and test result analysis. According to the method, the initial bit error rate of the to-be-tested FAKRA wire harness is tested by using the bit error tester after the test equipment is calibrated, then the connectors at the two ends and the matched connector are subjected to the limit plugging test, then the vibration test is performed, and the simulation degree of the vibration test is evaluated, so that whether vibration simulation optimization is performed or not is determined; according to the method and the device, firstly, the fluctuation condition of the bit error rate is monitored in the test period, so that whether a clock optimization measure is taken or not is determined, finally, all test data are collected, the stability of the bit error test is ensured, and the problem that the bit error test accuracy is reduced due to the fact that the vibration test simulation degree is not high enough and the simulation quality is unstable in the prior art is solved.

The invention provides a BIOS (Basic Input / Output System) parameter configuration method and device, and relates to the technical field of computers, the key points of the technical scheme are as follows: obtaining hardware feature information, and generating a hardware feature fingerprint; retrieving a parameter dependency rule; loading a BIOS parameter configuration set; performing static conflict detection to generate a conflict detection result; dividing the BIOS parameter configuration set into a core parameter subset and a to-be-verified parameter subset; applying the core parameter subset to the target non-standard hardware; applying the to-be-verified parameter subset to target non-standard hardware to execute hardware state detection; if the hardware state detection result is abnormal, rolling back the parameter change of the last application; and if the hardware state detection result is normal, continuing to apply the next batch of parameters. The BIOS parameter configuration method and device have the advantages that hardware feature fingerprints are obtained, parameter dependency rules are retrieved, and non-standard hardware parameter constraints are recognized.

The invention belongs to the technical field of digital signal processors, and particularly relates to a non-intrusive real-time monitoring debugger for a DSP (digital signal processor). The real-time monitoring debugger comprises a bus monitoring module and a tracking buffer module, and the bus monitoring module and the tracking buffer module jointly complete debugging and obtain real-time operation information. The bus monitoring module is used for monitoring the memory access operation of the DSP, and meanwhile, the tracking buffer module is used for recording execution tracks of a program before and after an event, so that comprehensive and accurate debugging information is provided for a system, and problems occurring in the running process of the DSP can be quickly positioned and solved, and the debugging efficiency is improved; in addition, by arranging a special register, high configurability is achieved, so that monitoring and recording strategies can be flexibly adjusted according to different debugging requirements, and the debugging process is more targeted and efficient.

The invention relates to the technical field of interface detection, and discloses a DP interface connection state detection method and system and computer equipment, and the method comprises the steps: collecting a historical level signal of an HPD pin in a DP interface, and carrying out the preprocessing of the historical level signal, and obtaining a level preprocessing signal and level fluctuation characteristic data; executing time domain decomposition processing to obtain a high-low level stable region identification result and stable region duration time data; calculating a high level threshold and a low level threshold to obtain a level double-threshold detection parameter; and performing state detection on the real-time level signal of the HPD pin based on the level double-threshold detection parameter to obtain a target connection state judgment result and a state judgment reliability value, thereby improving stability and anti-interference capability of DP interface connection state detection.

The invention provides a function test method and device, electronic equipment and a storage medium, and is applied to the technical field of computers, the method comprises the steps that after a test instruction for indicating a to-be-tested function of a target module is obtained, a target test case corresponding to the to-be-tested function is further obtained, and the target test case can call at least one preset test sequence; the preset test sequences comprise at least one test condition required for testing the to-be-tested function, finally calling each preset test sequence through the test case, constructing a verification scene for testing the to-be-tested function based on each test condition, and completing the test of the to-be-tested function. In addition, the test conditions included in any preset test sequence have no association relationship with other test conditions except the preset test sequence, and the preset test sequences of the to-be-tested function are mutually independent and can be called according to the test requirements in the test process, so that the function test efficiency can be effectively improved.

A process to train a machine learning model to predict fault location in a system includes generating a data set for training the machine learning model. The generating includes injecting, at a selected location of the system, a test fault into a simulation of the system using a workload, and recording a respective error syndrome generated by the simulation. Further, the generating includes repeating the injecting, at other selected location(s) of the system, of other test fault(s) into the simulation of the system, and the recording of respective, generated error syndromes. In addition, the process includes training, using the data set, the machine learning model, and providing the trained machine learning model for use in debugging the system, where the debugging includes predicting, using the trained machine learning model, a fault location within the system based on an error syndrome generated by the system due to the fault.

Techniques for assigning scenario-based tests to test assets are described. In an example, a scenario-based test operable to test a key performance indicator (KPI) of a System Under Test (SUT), a component behavior exhibited by a first component of the SUT, and a scenario characteristic are received. Based on the component behavior and the scenario characteristic, a first plurality of behavior models associated with the component behavior are identified. Based on the scenario characteristic a characteristic value is extracted from the scenario-based test. Each behavior model of the first plurality of behavior models is executed using the characteristic value to generate a first plurality of predicted behavior outcomes. Based on the first plurality of predicted behavior outcomes, a first test asset type from a plurality of test asset types is selected and the scenario-based test is transmitted to a test asset of the first test asset type.

The invention provides a memory channel detection circuit, device and method and a storage medium. The memory channel detection circuit comprises an interface, a signal acquisition module, a power supply module and a control module, the input end of the signal acquisition module is connected with the interface and the output end is connected with the control module; the power supply module is connected with the power end of the signal acquisition module and the power supply end of the control module and used for providing power voltage. Each memory channel is connected in series with a preset resistor; the interface is used for accessing a CPU or a memory bank; the signal acquisition module responds to a test instruction output by the control module, acquires partial voltage values corresponding to a plurality of memory channels, and outputs the partial voltage values to the control module; and the control module is used for determining whether the plurality of memory channels have faults or not according to the divided voltage values corresponding to the plurality of memory channels. According to the method, whether each memory channel is abnormal or not is judged by acquiring the partial voltage values corresponding to the plurality of memory channels, so that a large amount of time consumed by a traditional solution is saved.

The invention discloses a verification method and device for accelerating function coverage rate convergence, a medium and equipment, the method is applied to a verification platform, the verification platform comprises a directional excitation generator, a function coverage rate model and a to-be-tested design, and the verification platform is provided with a simulation switch. Comprising the following steps: analyzing a code file of a function coverage rate model by utilizing a preset cross use case script file to extract coverage bin information corresponding to a cross function coverage point, and configuring a simulation switch according to the coverage bin information to generate a boundary use case file; and reading switch configuration information in the boundary case file by using a directional excitation generator, generating a directional excitation flow based on the directional instruction sequence according to the switch configuration information, and sending the directional excitation flow to the design to be tested to execute verification work. By adopting the technical scheme of the invention, the boundary use case of the cross function coverage point can be automatically generated, so that the convergence time consumption of the function coverage rate is effectively reduced, and the convergence rate of the function coverage rate is improved.

The invention discloses a test system, method, device, medium and product based on a memory extension device, and relates to the technical field of computers, a processor and a memory extension interconnection component are connected through a memory extension bus, and a simulation test of the memory extension device is added. The memory expansion interconnection assembly is connected with the memory expansion device through the serial bus, so that the processor is directly connected with the memory expansion device, and the memory expansion interconnection assembly is located at the position outside the processor. Delay caused by a local memory access path is avoided, and the transmission efficiency is improved. The technical problem that the simulation processing result obtained according to the program duration under a traditional memory access path is low in accuracy can be solved, and the technical effects that the simulation test of the memory extension device is achieved, meanwhile, the function of full-system simulation is achieved, and the simulation accuracy of memory access of the mounted CXL memory extension device is improved are achieved.

The invention relates to an SPD hub chip testing method and device, equipment and a storage medium. The method comprises the steps that if it is determined that a to-be-tested SPD hub chip is placed in a replaceable limiting frame of a test seat and communication connection is established with an upper computer, target environment parameters are set, the to-be-tested SPD hub chip is initialized, the upper computer is in communication connection with the test seat, preset test data are written into an EEPROM of the SPD hub chip based on the target environment parameters, then read-back comparison is carried out, and the to-be-tested SPD hub chip is initialized; the static verification data is used for judging the static storage reliability of the to-be-tested SPD hub chip in the current environment, executing continuous read-write operation on the to-be-tested SPD hub chip to obtain a dynamic pressure test data set, and generating a test result of the to-be-tested SPD hub chip based on the static verification data and the dynamic pressure test data set.

The disclosure relates to a method for generating test vectors to locate faulty components within an electronic circuit. The method involves: - Generating (S01) simulated faulty situations for the circuit and recording sensor data for each situation. - Encoding (S02) the recorded data into encoded triplets. - Using (S03) the encoded triplets to determine a subset of test vectors that can discriminate between different faults. - Storing t(S04) he determined discriminating input test vectors and their associated sensor signatures in a test data structure.

Temperature-aware built-in self-test (BIST) control system for selectively controlling activation of BIST circuits in a processor-based system to maintain temperature limit and related methods. The temperature-aware BIST control system is configured to selectively control the number of BIST circuits in the processor-based system activated during the same time based on a temperature limit indicator related to a sensed temperature(s) in the processor-based system and whether such is within a defined temperature threshold(s) and / or temperature change rate threshold(s), which may be programmable. In this manner, the safety manager circuit can dynamically and selectively control the number of BIST circuits activated based on temperature according to the BIST control policy(ies) to reduce or avoid circuit failures due to excess temperature, while at the same time maximizing the staggering (i.e., overlapping) of BIST circuit activations to maximize testing speed.

In some examples, a system monitors for a memory fault associated with execution of software. Based at least on receiving an indication of a possible memory fault, the system scans a first area of the memory based on a data structure that indicates that the first area of the memory stores a portion of parameters of the software that affect an accuracy of the software if there is a memory fault in the first area of the memory. Based at least on the scanning indicating that there is a memory fault in the first area of the memory, the system remaps the portion of parameters of the software from the first area to a second area of the memory that is determined to be free.

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

Provided in the embodiments of the present disclosure are a processing method, platform, and apparatus based on a chip simulator platform. The chip simulator platform is deployed with a first test end and a second test end, and the first test end and the second test end are respectively bound with different CPU resources in the chip simulator platform. The method comprises: performing received data packet redirection configuration on a local virtual network interface card of the chip simulator platform, the data packet redirection configuration being used for sending a specified data packet to a designated CPU resource; and when a soft interrupt is triggered in response to a network request issued by the first test end, according to an instruction of the received data packet redirection configuration and by means of the local virtual network interface card, sending a data packet corresponding to the soft interrupt to a CPU resource bound to the second test end for processing. According to the embodiments of the present disclosure, network environment simulation in a chip simulator environment is achieved by utilizing received data packet redirection technology.

An integrated circuit formed with interconnected electronic elements includes at least:i) functional elements which perform IC operations;ii) at least one countermeasure (CM) for detecting fault injection attacks upon the IC and outputting an alert signal when a FI attack is detected; andiii) at least one attack emulator which emulates FI attacks on the IC by applying stimuli to the plurality of functional elements in accordance with at least one control signal.The IC may include other elements such as power supply elements, oscillators, interface elements and so forth.

The invention belongs to the technical field of computers, and particularly relates to a dynamically configured cockpit host video test multiplexing method. The method aims at solving the problems that a traditional testing means is poor in universality, incomplete in coverage and low in automation degree. A structural equipment description file is constructed by analyzing a host technical document, an adaptive dynamic test configuration template is automatically generated in combination with a test case library, and flexible configuration of multi-channel video stream parameters, abnormal injection modes and time sequence logic is supported. A containerized virtual signal source is deployed on a universal computing platform, and an analog video stream conforming to an input specification is generated in real time. Through the equipment description driving and virtualization signal generation technology, the multiplexing capability and coverage integrity of the testing system are improved, efficient and automatic testing of multiple types of hosts is achieved, and the hardware cost and the deployment period are remarkably reduced.

The invention discloses an STDF file offline generation method and system suitable for various ATEs. The method comprises the steps that the composition sequence of STDF files is determined; acquiring a configuration file, wherein the configuration file comprises batch information, wafer information, test site configuration information, pin configuration information, hardware Bin definition and software Bin definition; analyzing ATE native test data, and obtaining a chip test start mark, multiple types of test item results and a chip test result; checking whether the first test site information is consistent with the second test site information or not, and checking whether hardware Bin information and software Bin information in a chip test result accord with a hardware Bin definition and a software Bin definition in a configuration file or not; and when all the verification results pass, generating an STDF file according to a composition sequence based on the configuration file, the chip test start mark, the test item result and the chip test result. The test efficiency can be improved, and the supply chain cost can be reduced.

The invention provides a hard disk prediction method and device, equipment, a medium, a product and a training method, which can be applied to the technical field of hard disks. The hard disk prediction method comprises the steps of obtaining the type, performance data and use state data of a to-be-predicted hard disk; processing the use state data to obtain a health attenuation moment of the to-be-predicted hard disk in the use process, the health attenuation moment representing a moment when the health attenuation degree of the to-be-predicted hard disk reaches a preset threshold; obtaining a health degree score of the to-be-predicted hard disk according to the type and use state data of the to-be-predicted hard disk; and according to the health attenuation moment, the health degree score and the performance data, obtaining a prediction result of the to-be-predicted hard disk, the prediction result representing a health degree attenuation trend and a performance attenuation trend of the to-be-predicted hard disk.

Systems and methods for assessing display health in response to accidents are described. In some embodiments, an Information Handling System (IHS) may include an Embedded Controller (EC) and a memory coupled to the EC, where the memory comprises program instructions that, upon execution by the EC, cause the IHS to initiate an integrated display's Built-In-Self-Test (BIST) in response to a determination that the IHS suffered an accident.