1649results about "Functional testing" patented technology

The invention discloses a fault diagnosis method and device for a server, and relates to the technical field of electric digital data processing, and the method comprises the steps: collecting the actual operation data of a target server, obtaining the configuration information and historical fault data, and detecting whether the target server breaks down or not; when a fault occurs, inputting the configuration information, the actual operation data and the historical fault data into a pre-constructed fault path generation model so as to output a corresponding diagnosis path; and determining a diagnosis rule, a diagnosis label and a fault type when the target server is diagnosed according to the diagnosis path to generate a current fault diagnosis result, thereby solving the technical problems that the flow is solidified and single, the dynamic adjustment cannot be realized, the flexibility and pertinence are lacked, the diagnosis efficiency is low and the diagnosis precision is poor, and achieving the purposes of shortening the diagnosis time and improving the diagnosis efficiency. The server energy consumption and maintenance cost are reduced, the fault positioning accuracy is improved, the fault solving time is shortened, and the technical effect of automatic fault diagnosis is achieved.

The embodiment of the invention discloses a verification platform, method and system for verifying an I2C protocol based on a UVM environment, and relates to the field of function verification. The UVM environment has comprehensive parameterization configuration capability, various test scenes are dynamically matched, and all-directional coverage and deep insight of verification are ensured. And an intelligent mode switching mechanism is adopted, and the role change of the DUT is seamlessly jointed, so that the automation and efficiency of the verification process are improved. And a randomized test strategy is introduced, so that the randomness and robustness of verification are remarkably enhanced, and potential problems are effectively revealed. As standard I2C device simulation, time sequence verification is independently executed in an environment, communication abnormity is accurately captured and analyzed, and fault positioning is accelerated. Through the fusion application of the SystemVerilog and the UVM, the verification complexity is simplified, the simulation process is optimized, and the iteration period is shortened.

Systems and methods are disclosed that relate to applications and platforms for performing in-system testing for autonomous or semi-autonomous systems and applications. In some embodiments, resources of a computing system may be grouped into one or more subsets of system elements (e.g., “a chiplet”) and may be configured to be controlled via an associated local controller, which may enable and / or disable the chiplet as targeted. In embodiments, the local controllers may receive instructions from a central controller and, via the enabling and / or disabling of the chiplets, may maintain a number of resources consumed during system testing within a threshold. As a result, the system may be configured to perform system testing without additional resources and / or without redirecting resources that may be intended for other operations.

Described herein is a generic hardware / software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.

The invention discloses a solid state disk performance fluctuation test method, device and equipment and a storage medium, and relates to the technical field of performance tests.A corresponding test action sequence is generated according to a performance test instruction, a plurality of test actions are organized into a standard test process capable of being repeatedly executed, and the performance fluctuation test efficiency is improved. The influence of the difference of manual test operation execution on the test result is eliminated, the performance fluctuation test result of the to-be-tested solid state disk is calculated based on the storage performance index of the to-be-tested solid state disk in the test action sequence execution process, and objective evaluation of the performance fluctuation of the solid state disk is realized on the basis of sufficient data support. The automation and standardization of the test are realized from the two aspects of the test process and the result evaluation, and the efficiency and accuracy of the test are improved.

Disclosed are various embodiments for identifying fault injection impact zones. A test for an application can be received from a test service. An application schema can then be created that represents the systems or services that are involved in the execution of the application. Applications with a similar application schema are then identified using a first machine-learning model. A subset of the plurality of applications that have experienced a similar test are then identified with a second machine-learning model. Log files associated with each of the subset of applications are then analyzed to identify errors that occurred during the similar test. Each of the identified errors are then provided to the test service in response to receipt of the test.

The invention discloses a superconductive processor micro-architecture construction method based on RISC-V. The superconductive processor micro-architecture construction method aims at achieving efficient operation and performance optimization of a processor in an ultralow-temperature environment. The method comprises the following steps: firstly, designing a functional module and an assembly line of a processor based on an RISC-V instruction set, and presetting initial parameters; next, micro-architecture parameters are selected and optimized through a simulation tool and a multi-objective optimization algorithm, and balance among performance, power consumption and chip area is ensured; then, a low-temperature cooling system is designed and integrated, and it is ensured that the processor stably operates in an ultralow-temperature environment of 2-4 Kelvin; the function correctness and the performance efficiency of the processor are verified through simulation and actual testing; and finally, manufacturing a key assembly by using a superconducting material, and integrally packaging the processor and the cooling system. By combining refined performance optimization and a comprehensive performance evaluation algorithm, the performance and energy efficiency of the processor in a complex environment can be remarkably improved.

The invention discloses a test method of a storage link, electronic equipment, a storage medium and a program product, and relates to the technical field of storage networks, and the test method comprises the following steps: initializing a plurality of controller nodes in a storage server to form one or more controller groups, and networking the controller groups to a storage cluster; configuring a switch partition matched with the current state of the port virtualization function of the controller group; verifying a routing path between the host and the storage cluster according to a first mapping relationship between the physical port and the virtual port, the current state and the switch partition; the routing path comprises a second mapping relation between the host and the physical port and a third mapping relation between the host and the virtual port, namely, the storage link between the host and the storage cluster can be tested. The technical problems that virtual port management is complex and manual configuration is prone to errors are solved, and the technical effects that the test coverage rate and efficiency are improved, and the system reliability and flexibility are enhanced are achieved.

The present invention relates to the technical field of automobile curved screen detection, and in particular to a device and method for detecting the response time of an automobile curved screen, the method comprising: optimizing and affine transforming pixels on a two-dimensional plane image obtained by a 2D camera to obtain corresponding three-dimensional position information of the curved screen; determining the three-dimensional position information of a target icon on the automobile curved screen by a 3D camera, controlling a mechanical arm to accurately click the target icon on the automobile curved screen according to navigation coordinates, synchronously starting high-frame rate cameras set in different directions, obtaining continuous images and time information of changes in different areas of the curved screen when the mechanical arm operates on the automobile curved screen; inputting into a response time detection algorithm for analysis, and evaluating the response time performance of the automobile curved screen according to the output result of the response time detection algorithm. The present invention can realize accurate detection of the response time of an automobile curved screen.

The invention provides an automatic test method, which is applied to a host to perform EAP simulation test on semiconductor equipment, and comprises the following steps: obtaining a test case set comprising a plurality of test cases, the test cases comprising a plurality of test steps arranged in order and preconditions and expected results respectively corresponding to the test steps; a target test case group is obtained in the test case set, test cases included in the target test case group are target test cases, and input data corresponding to preconditions and expected results in the target test cases are obtained; on the basis of the sequence of the test steps contained in the target test case, testing the current test steps in sequence to obtain a case test result of the target test case, wherein the case test result indicates that the test of the target test case is successful or failed; and obtaining a case test result of each target test case in the target test case group. According to the invention, automatic testing of the semiconductor equipment is realized.

Systems and methods for assessing display health in response to accidents are described. In some embodiments, an Information Handling System (IHS) may include an Embedded Controller (EC) and a memory coupled to the EC, where the memory comprises program instructions that, upon execution by the EC, cause the IHS to initiate an integrated display's Built-In-Self-Test (BIST) in response to a determination that the IHS suffered an accident.

The invention discloses a central processing unit power supply efficiency test method and device, electronic equipment and a medium, and relates to the technical field of server hardware testing, and the method comprises the steps: generating a plurality of test loads and a plurality of temperature test scenes if a data synchronous collection signal is detected, and carrying out the testing of the power supply efficiency of a central processing unit based on a preset traversal strategy; all power supply states of the central processing unit are traversed according to various test loads and various temperature test scenes, load change data, power supply data and temperature data of the central processing unit in the traversing process are collected, the data are packaged, and power supply efficiency test data can be obtained. And obtaining a central processing unit power supply efficiency test result according to the power supply efficiency test data. Therefore, by automatically adjusting the test load and the temperature test scene, the real business scene is simulated, the problem that the prior art depends on a fixed load mode and cannot reflect the dynamic frequency / voltage regulation characteristic of the CPU in the real scene is solved, and the technical effects of high test efficiency and high accuracy are achieved.

The invention discloses a computer system and a measurement method thereof and a medium, and the method comprises the steps: determining KPIs in a specific application scene, and setting a specific performance threshold value; the method comprises the following steps: performing data acquisition on a virtual machine node of a computer system by using an AI-based dynamic sampling technology; filtering and cleaning the collected data, and automatically marking abnormal data points through a K-means clustering algorithm; performing real-time performance prediction based on an LSTM neural network, identifying a performance bottleneck, and performing partial preliminary analysis at a virtual machine end by adopting an edge computing technology; according to a real-time data analysis result, KPI index parameters are dynamically adjusted, and a prediction result and an actual operation condition are fed back to the LSTM neural network model; and generating a chart and an analysis report based on natural language processing by using a data visualization tool, and displaying a measurement analysis result. According to the invention, through an intelligent feedback mechanism, monitoring index parameters are dynamically adjusted, a prediction result is compared with an actual operation condition, and a monitoring model is continuously optimized, so that system monitoring is more accurate and efficient.

The invention discloses a data recovery test method, which comprises the following steps of: performing fault injection on a storage system to enable the storage system to enter a recovery state; determining a target test scene in the recovery state, and performing a performance recovery test on the storage system in the target test scene; estimating a target duration for the storage system to enter a stable state in the performance recovery test process; after waiting for the target duration, collecting target performance data of the storage system for verification, and determining a test result of the target test scene according to a verification result; and determining a data recovery test result according to the test result of each target test scene. By applying the technical scheme provided by the invention, more efficient and accurate data recovery performance testing can be realized for the storage system. The invention also discloses a data recovery test device, electronic equipment and a computer readable storage medium, which also have the above technical effects.

Aspects relate to monitoring timing. In one example an apparatus includes a first sensor array formed in an integrated circuit, sensors of the first sensor array having paths through the integrated circuit and sensors of the first sensor array configured to generate one or more first level indications of a condition of the integrated circuit. A second sensor array is formed in the integrated circuit. Sensors of the second sensor array have paths through the integrated circuit and sensors of the second sensor array are configured to generate one or more second level indications of the condition of the integrated circuit. A monitor controller is coupled to the first sensor array and to the second sensor array and configured to receive the one or more first level indications and to actuate the second sensor array in response to the one or more first level indications.

Techniques pertaining to generative artificial intelligence (GAI)-based random test generation framework for processor verification are described. An apparatus generates one of more random test cases with an aid of a GAI-assisted random verification program (GRVP) framework. The apparatus also performs validation testing on a design of a processor using the one or more random test cases.

The invention relates to a fault simulation method, a test method, equipment and a system for a Flexray bus. The fault simulation method for the Flexray bus comprises the following steps of: determining bus time information of the Flexray bus, the bus time information at least comprises information used for describing a period of the Flexray bus and time slots in the period; and based on the bus time information, performing fault simulation in a specified time slot of a specified period of the Flexray bus.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an integrated circuit has a logic path formed in the integrated circuit. A monitor circuit is formed in the integrated circuit near the logic path and configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to determine a condition of the integrated circuit based on the diagnostic code sequence, and to initiate a remedial action in response to the condition of the integrated circuit.

The present disclosure relates to a computer system comprising a simulation virtual machine comprising a translator to translate simulation virtual machine instructions into instructions executable by a test platform and an instruction executor, the simulation virtual machine sending the instructions to the test platform using a shared memory; the instruction translator comprises a CPU (Central Processing Unit) simulator, the simulator, a BIOS (Basic Input Output System) and an OS (Operating System) for receiving and sending instructions, and the instruction translator further comprises a plurality of instruction grabber for grabbing corresponding instructions from the simulator; the instruction executor comprises a request filtering module which filters and distributes various instructions received from the instruction translator, and sends filtered residual instructions required by test execution of the test platform to a request control module; the request control module sends the filtered residual instruction to the transmission module, and receives a test execution result from the test platform from the transmission module; and the transmission module sends an instruction required by the test platform to the test platform by using the shared memory.

Systems and methods for service vendor onboarding and pre-production artifact validation and functional testing are provided. An example method includes receiving, in an automated test control system in connection with a cellular network, a request for deploying an artifact on the cellular network, generating an artifact profile, a configuration profile, a release note associated with the artifact, performing a validation of the artifact according to a predetermined validation rule, in response to a determination that the artifact is validated, instantiating one or more test environments for the validated artifact, performing a functional test on the artifact within the test environment, and outputting results of the validation and the functional test.

The invention discloses a verification method for a second-level cache interface protocol, which belongs to the technical field of multi-core verification, and comprises the following steps of: setting verification targets, including function correctness, performance standard, compatibility and exception handling capacity; establishing a verification environment, wherein the verification environment comprises a hardware platform and a test tool; function verification, including read-write operation verification, cache line state transition verification and consistency verification; performance verification including delay testing and bandwidth testing; the compatibility verification comprises the compatibility with a first-level cache and the compatibility with a processor core; the abnormal condition verification comprises interrupt processing verification and error injection verification; and analyzing a test result. According to the verification method for the second-level cache interface protocol, the second-level cache interface protocol can be comprehensively and deeply verified, the function correctness, the performance standard reaching performance and the compatibility with other components of the second-level cache interface protocol are ensured, and a solid guarantee is provided for stable operation of a high-performance computer system.

According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.

A system can include a memory and a processing device, operatively coupled to the memory, to perform operations including receiving, from a storage device, a data block of a blockchain, wherein the data block includes a data block payload comprising test data of an in-system test to be performed on a target device, which is external with respect to the storage device, determining whether the data block is valid by authenticating the data block, and in response to determining that the data block is valid, performing the in-system test on the target device by processing at least a portion of the test data extracted from the data block payload.

The invention discloses an NAND block health degree prediction method and system based on read interference perception. The method comprises the steps that read interference event counts of an NAND flash memory block are collected in real time; dynamically triggering multi-dimensional parameter acquisition to generate multi-dimensional parameter data with timestamps; extracting a dynamic change rate, a distribution entropy value and a growth slope feature based on the multi-dimensional parameters, and generating a compression feature matrix; inputting the compressed feature matrix into a pre-trained graph neural network-Hamiltonian Monte Carlo hybrid model, outputting a health degree score and recording a low-confidence sample; based on the health degree score and the historical health degree attenuation trajectory, generating an early warning level signal through a dynamic threshold engine; executing a corresponding block maintenance strategy according to the early warning level, and recording strategy execution effect data; and model parameters are updated through knowledge distillation by utilizing a low-confidence sample and strategy execution effect data, so that level-by-level and cross-level health risks of the NAND flash memory based on read interference perception are truly and accurately reflected.

A computer-implemented method and a processing module for identifying that a fault has occurred in a finite-state machine (FSM). It is determined whether a set of one or more transitions that have occurred between states of the FSM is allowable. In response to determining that the set of one or more transitions is not allowable, it is identified that a fault has occurred in the FSM.

According to the automatic test error-proofing detection method and detection system disclosed by the invention, after a test instruction is received, verification requests generated by bar codes of a needle bed upper mold and a needle bed lower mold are received; sending to a selected product test program to judge whether the needle bed upper die and the needle bed lower die and whether the needle bed name is matched with the current product test program or not; if not, stopping the test, otherwise, after the to-be-tested product is placed in place, receiving a serial number of the to-be-tested product generated by the bar code of the to-be-tested product, and querying and obtaining internal card binding information of the corresponding to-be-tested product; controlling the test tool to start and electrify the to-be-tested product, acquiring identity information of an internal clamping piece actually mounted in the to-be-tested product, comparing the identity information with inquired binding information of the internal clamping piece, if the identity information is consistent with the binding information of the internal clamping piece, carrying out subsequent function test, otherwise, sending error information of the internal clamping piece, and controlling the test tool to pull open an upper die and a lower die of the needle bed; therefore, automatic error-proofing detection of each module test of the industrial control system is realized.

The embodiment of the invention provides an RAID fault simulation method and device, relates to the technical field of computer system structure storage and can also be used for the financial field, and the method comprises the steps that an RAID array of a corresponding level is constructed based on the preset number of RAID array hard disks and a hard disk list forming an RAID; performing parameter control on the constructed RAID array to construct a corresponding fault model, wherein the fault type of the fault model comprises at least one of a hard disk type fault, a control and configuration type fault, a logic fault and a read-write slow fault; determining a corresponding fault injection instruction and a fault recovery instruction according to the fault model, and inputting the instructions to a tested system, so that the tested system performs fault simulation; the RAID fault simulation method and device can solve the problems that the current RAID fault simulation cost is high, and hardware dependence, professional software dependence and manual operation dependence exist.

The invention belongs to the related technical field of microelectronics, and discloses an in-memory array testing device capable of flexibly pulsing and a control method thereof, the device comprises a daughter board array, and each daughter board comprises a chip seat, a digital-to-analog conversion module, a driving module, a differential reading module, an analog-to-digital conversion module, a shift accumulation module, a first bidirectional interface, a second bidirectional interface, a third bidirectional interface and a fourth bidirectional interface; the chip seat is used for placing an in-memory array chip; the digital-to-analog conversion module converts an input vector into a voltage signal, and the driving module provides a driving current; the differential reading module comprises two anti-phase amplification circuits and an addition and subtraction circuit, the results of the chip in the memory are subjected to differential sampling and then output to the analog-to-digital conversion module for analog-to-digital conversion, and the shift accumulation module is used for performing shift accumulation on the analog-to-digital conversion results and digital signals of other daughter boards to obtain result vectors. Based on the testing device, the chip in the memory can be tested, and the flexibility is high.

The invention relates to an independent AC cycle restart test method and system for a production test server. The method comprises the following steps: determining whether a tested server is ready to be put on shelf or not; starting the test script, and reading the position information; obtaining PDU binding information to obtain a PDU address and power supply interface information thereof; carrying out a connection test on the PDU and the tested server to determine that the tested server is correctly connected with the PDU power supply interface; and executing an AC loop restart test on the tested server. According to the invention, the physical position of the production test server and the binding relation between the intelligent PDU IP of the corresponding server and the power supply interface can be positioned, the power-on and power-off of the power supply of a certain production test server can be accurately controlled, and the tested servers can be independently operated and tested.