702 results about "Low delay" patented technology

The invention discloses a video stream adaptive low-delay real-time transmission method and system based on edge calculation. The method comprises the following steps: receiving a real-time video stream from a network camera, creating a pipeline queue, adding timestamp information for each video frame, and setting a queue protection mechanism; the coded video frames are taken out from the input queue, and the frames in the video are processed through hardware acceleration decoding; the resource use condition of the system is monitored in real time; executing a self-adaptive frame skipping decision according to a performance monitoring result; timestamp generation: dynamically calculating a timestamp interval according to an actual processing frame rate; receiving the decoded original video frame and the corresponding timestamp information, accelerating decoding by using hardware, and executing a video coding operation; and packaging and transmitting the coded video data, and providing a standard protocol interface to be connected with a client for playing. According to the scheme, stable low delay and relatively low resource occupation can be kept, and meanwhile, the video quality is remarkably improved.

The invention relates to the technical field of audio control, and discloses a low-delay audio input switching method and system, a storage medium and equipment, and the method comprises the steps: carrying out the parallel pre-initialization of a plurality of pieces of audio input equipment, and building an independent parallel audio data cache for each piece of equipment; monitoring the state of each audio input device and the audio stream quality in real time, and judging whether switching is triggered or not based on a multi-factor decision model; after the switching decision is triggered, seamless audio data stream switching is executed, and format unification processing and cross fade-in and fade-out transition are included; a unified equipment operation interface is provided through the hardware abstraction layer, and system resources are optimized and managed; a delay sensing closed-loop control mechanism is constructed, processing delay of each link is monitored in real time, a caching strategy, a processing algorithm and resource allocation parameters are dynamically adjusted, self-adaptive balance of low delay and high tone quality is achieved, and through the method, quick and smooth switching of audio input equipment is achieved, delay is remarkably reduced, and real-time audio experience is improved.

A low-delay multi-protocol intelligent lighting synchronization system based on a unified abstraction layer comprises the steps that an instruction from a multi-protocol bridging module is received, and network round-trip time data of terminal equipment is acquired through an active detection mechanism; based on the network round-trip time data, adopting a Kalman filtering algorithm to construct a delay prediction model so as to predict the future network delay of the terminal equipment; inputting the instruction into a third-stage buffer area for processing, and dynamically adjusting the trigger frequency of the active detection mechanism according to the load state of the third-stage annular buffer area; calculating queue delay of the buffer area according to the received load state of the buffer area, and obtaining final sending time of the instruction in combination with future network delay of the terminal equipment; and at the final sending time, sending the instruction from the sending buffer area to the corresponding terminal equipment. According to the system, low-delay and high-stability synchronization of cross-protocol equipment in the field of intelligent illumination is realized.

The invention belongs to the technical field of computer storage, and particularly relates to a solid state disk data management and efficient storage distribution method, which comprises a data characteristic sensing and classifying unit, a data characteristic sensing and classifying unit, a data processing unit, a data storage unit and a data distribution unit, wherein the data characteristic sensing and classifying unit is configured for analyzing write-in request data flow entering a solid state disk in real time or periodically, extracting various characteristic parameters associated with data blocks and storing the data blocks; classifying the data on the basis of the characteristic parameters, and distributing one or more data classification labels for each data block to be written or stored; and the self-adaptive storage allocation strategy unit is configured to be used for dynamically selecting an optimal physical block for data writing according to the data classification label and in combination with the physical block state information of the current flash memory medium. According to the invention, the solid state disk can better adapt to various dynamic and variable workloads, and especially shows more excellent continuous write-in performance, lower delay jitter and obviously prolonged service life when processing a large amount of random write-in, small block write-in and write amplification sensitive applications.

In various examples, systems and methods are disclosed relating to coordinating and synchronizing the actions of different types of processors with low latency. Different types of processors may perform better at different types of tasks. By coordinating the processing of a one-dimensional processor such as a vector processing unit (VPU) and the processing of a two-dimensional processor such as a pixel processing engine (PPE), an overall speed of task completion can be improved.

The invention relates to the technical field of computers, discloses a heterogeneous computing low-delay communication method and system, and aims to solve the problem of high delay caused by high communication protocol overhead, lack of dynamic scheduling collaboration, memory migration redundancy and non-uniform cross-node communication abstraction in existing heterogeneous computing. The method comprises the following steps: receiving a task scheduling request and analyzing a task dependency graph; tasks are dynamically allocated based on node loads and link states; rDMA, NVLink or PCIe straight-through protocols are adaptively selected according to node types to establish communication channels; zero-copy data exchange is realized through a shared memory mapping buffer area; hardware timestamps are utilized to synchronize feedback delays with PTP to optimize scheduling. The system comprises a heterogeneous computing node cluster, a unified communication scheduling controller, a low-delay communication protocol stack, a shared memory mapping buffer area and a communication delay sensing task distributor. According to the scheme, the communication delay is remarkably reduced, and the throughput and the task execution efficiency are improved.

The invention discloses a key value storage system indexing method oriented to an NVM-NVMe SSD (Non-Volatile Memory-Non-Volatile Memory Express Solid State Disk) hybrid architecture, which comprises the following steps of: constructing a heterogeneous storage architecture taking cold and hot data perception as a core driving mechanism, coordinating and managing two types of storage media, namely a non-volatile memory NVM and a solid state disk NVMe SSD, and realizing efficient identification, layered writing and dynamic migration of cold and hot data. According to the method, the characteristics of low delay, durability and byte addressing of the NVM are utilized, the frequency and I / O overhead of Flush and Compaction operations are reduced in a data write-in path, meanwhile, the problem of mixed storage of cold and hot data is avoided, and therefore the overall performance and storage efficiency of a system are remarkably improved. In addition, by introducing an asynchronous migration module, the method can dynamically adapt to the change of data popularity along with time evolution, and effectively support high performance and high availability of the key value system in long-term operation.

Low- to ultralow-latency content delivery via real-time transport protocol (RTP) is provided. In an example, transport packets, which carry a packetized elementary stream (PES), are selectively marked based on frame size. More particularly, if a number or size of packets needed to transport a picture or PES packet exceeds a threshold, they are marked for preferential processing, such as low latency, low loss, and scalable throughput (L4S) processing. If the number or size of packets is below the threshold, they are marked for default or non-preferential processing. The marking may be applied to entire pictures, tiles, and / or slices. Related apparatuses, devices, techniques, and articles are also described.

The invention relates to a robot track synchronization control method. According to the technical scheme, efficient collection and over-distance transmission of neural signals are achieved through the quantum entanglement technology, the brain movement intention is analyzed in combination with a high-sensitivity sensor and an intelligent algorithm, an instruction is transmitted to a robot power driving system through a low-delay communication architecture, and real-time synchronization of man-machine tracks is achieved through a two-way feedback system. Meanwhile, the movement flexibility of the robot is improved by adopting a lightweight design, the problems of high delay, low precision, poor interaction experience and the like in traditional man-machine synchronous control are solved, and the method can be widely applied to the fields of exoskeleton robots, industrial collaborative robots, rehabilitation medical robots and the like. The method has the advantages of being low in delay, high in precision, capable of improving interaction experience and wide in application range.

The invention discloses a real-time data receiving and transmitting system and method based on a kernel bypass, and the method comprises the steps: processing the received data when the data receiving and transmitting system receives the data, and achieving the high-level data with complete semantics; updating a write pointer through atomic operation, and writing high-level data into a lockless annular queue in the shared memory module; the upper-layer application module reads the lock-free annular queue in the shared memory; when the data receiving and transmitting system transmits data, upper-layer data to be transmitted is transmitted to the shared memory module, and a write pointer is updated; the upper layer data in the shared memory is read in a polling or interruption mode, a read pointer is updated, the upper layer semantic data is segmented according to the format, a UDP data packet is obtained, the UDP data packet is written into a network card in the polling or interruption mode, and data sending is achieved. Through the data receiving and transmitting system disclosed by the invention, microsecond-level ultra-low delay of data certainty is realized, and efficient decoupling and stable throughput are realized.

The invention discloses an interface conversion device and circuit, electronic equipment and an interface conversion method, and relates to the technical field of computer system structures. Extracting a cache or memory transaction request from the first preset interface signal through a channel processing module, generating consistency transaction information, sending the consistency transaction information to a consistency transaction concurrent processing module, receiving response data of the consistency transaction concurrent processing module, and packaging the response data into a second preset interface signal; the consistency transaction concurrent processing module carries out processing according to the received consistency transaction information to obtain a concurrent signal; and the interface conversion module decodes and converts the concurrent signal into a first target protocol control signal, and / or converts the authorized transaction into a second target protocol control signal. Therefore, concurrent analysis, consistency transaction mapping and direct conversion are carried out on a multi-channel protocol through a configurable modular hardware architecture, and high-concurrency and low-delay protocol conversion and cache consistency maintenance between an inter-chip consistency interconnection protocol and an on-chip bus protocol are realized.

The invention discloses an edge computing node collaborative task unloading method for guaranteeing a low-delay service, and relates to the field of edge computing, each edge computing node generates a collaborative view comprising the edge computing node and a neighbor edge computing node through a local LSTM prediction model and federated learning, and the collaborative view comprises a predicted resource state and a predicted network state; according to the invention, the local LSTM prediction model and federated learning are combined to generate the collaborative view, so that accurate prediction and global information sharing of edge node resources and network states are realized, and the accuracy of decision making is improved; the tasks are analyzed into a dependency graph with key path marks, so that priority scheduling of the key tasks is ensured, and the overall task time delay is reduced; based on a weighted voting consensus mechanism of node credibility and resource adequacy, the efficiency and reliability of decision consensus among nodes are improved; the task unloading efficiency and the service quality of the low-delay service are effectively improved, and the stability and the reliability of the edge computing system are enhanced.

The invention discloses an embedded system resource allocation method and system based on hardware virtualization. The method comprises the following steps: deploying a Type-1 virtual machine monitor system on a multi-core processor hardware platform supporting virtualization extension; the Type-1 virtual machine monitor carries out virtualization, resource partitioning and security isolation on hardware resources, and creates operation system execution environment'domain 'partitions zoneG and zoneR. A universal operating system is deployed in a zoneG domain partition to take charge of a high-computing-power computing task, and a real-time operating system is deployed in a zoneR to take charge of a real-time computing task. Low-delay inter-core communication between a real-time operating system and a general operating system is realized based on an OpenAMP protocol, and data is transmitted through a shared memory and an interrupt mechanism; according to the requirements of real-time tasks and non-real-time tasks, a Type-1 virtual machine monitor dynamically adjusts a resource allocation strategy, and the priority and deadline of the real-time tasks are ensured.

The invention discloses a cloud-side-end collaborative meat intelligent detection system and a cloud-side-end collaborative meat intelligent detection method. The system realizes high precision, low delay and low resource consumption of meat detection through three-level cooperation of the mobile terminal, the edge device and the cloud server and a dynamic task scheduling strategy based on confidence, and is suitable for meat safety supervision in a large-scale and complex environment.

The invention relates to the technical field of voice interaction, in particular to a dialogue type AI low-delay response control method and system based on semantic analysis. The method comprises the following steps: firstly, generating a driving intensity correlation factor of a current time window according to the change of CAN bus data; further monitoring the output of the NLU, analyzing the acoustic intonation raising characteristics, and obtaining an interaction suppression coefficient in combination with the driving intensity correlation factor; further acquiring a time pressure coefficient based on the mute duration after the user stops sounding; further comparing the interaction suppression coefficient and the time pressure coefficient of the current time window to obtain a response judgment value; further analyzing the change trend of the interaction inhibition coefficient, and updating an environment improvement flag bit; and finally, according to the driving intensity correlation factor, the environment improvement flag bit and the response decision value of the current time window, carrying out multi-level response decision control, and carrying out selective reset of an interaction state, thereby solving the problems of wrong truncation and response delay of voice interaction under dynamic driving.

The invention provides a synchronization signal processing method and an artificial intelligence chip. The synchronization signal processing method comprises the following steps: receiving a synchronization signal reading request with a prompt sign sent by a first processing core; confirming that the synchronization signal reading request is a synchronization operation according to the prompt sign; determining that storage addresses in an effective state exist, and determining whether a target storage address matched with the target program segment identifier and the target synchronous address identifier exists in the storage addresses in the effective state; if the target storage address exists, when the synchronization value in the target storage address is the same as the target synchronization value, returning a synchronization success message to the first processing core, and adjusting readable times in the target storage address; the time spent on reading the synchronizing signal is greatly shortened, the time is saved, the delay is reduced, and the processing efficiency of the processing core is improved; moreover, the bandwidth can be saved, the bandwidth waste is avoided, and the working efficiency of the whole system is improved.

The invention provides a high-efficiency matrix engine (RVME) architecture based on RISC-V matrix extension and a calculation method, and the architecture comprises an instruction buffering and decoding module, a matrix loading / storage module, a matrix register file, a parallel outer product array and an element-by-element operation module; the matrix register file comprises a Tile register and an Acculator register; the storage modules are respectively used for storing an input matrix and an accumulation result and supporting efficient data access and parallel computing; the matrix loading / storage module significantly improves the data loading efficiency through cache line alignment and matrix transposition optimization; the instruction buffering and decoding module cooperates with a main processor through a reordering buffer area and an instruction buffer area to ensure efficient scheduling and execution of instructions. The parallel outer product array is adopted to replace a traditional systolic array, the idle period in the calculation process is eliminated through multicast data flow scheduling and a ping-pong buffer read-write mechanism, and matrix multiplication and addition operation with high calculation utilization rate and low delay is achieved.

The invention discloses an RTSP video stream AI processing method and system based on a tsn network, which realize end-to-end deterministic transmission and processing, guarantee low-delay and low-jitter transmission of a video stream from a source to an AI unit through a TSN, meet the industrial-grade real-time requirement and perform efficient edge AI processing. The problem that a traditional CPU is low in efficiency or a GPU is high in power consumption is solved, real-time analysis of the high energy efficiency ratio and high system integration are achieved, network transmission, video decoding, AI reasoning and result visualization are integrated into a single embedded platform, and hardware complexity and cost are reduced.

The invention discloses a method for ensuring hard real-time in a Linux user mode based on a multi-core CPU, and belongs to the technical field of embedded systems. According to the method, a Linux kernel is configured to be in a completely preemptable mode, user threads with the number equal to that of CPU kernels are created and bound to different kernels, a real-time scheduling kernel is selected, the thread scheduling strategy of the real-time scheduling kernel is set to be SCHEDFIFO, the priority of the real-time scheduling kernel is equal to that of the lowest-priority soft interrupt, the thread stack space is locked, the real-time kernel is isolated through kernel parameters isolcplus and nohzfull, and the cost of tick is avoided. Finally, the real-time core is exclusively used for executing the real-time task. According to the scheme, the problem that the real-time performance of the Linux user state task is poor due to the fact that a kernel cannot be preempted, scheduling delay, memory page changing, system interference and the like is effectively solved, and extremely low delay and high certainty of user state task response are ensured through multi-level collaborative optimization.

The invention provides a message sorting method and device, electronic equipment and a program product, original messages are obtained through a distribution thread pool, the messages of the same business process are distributed to the same to-be-sorted queue, a working thread of the sorting thread pool reads the messages and stores the messages in a thread local cache set, the sendability is judged based on the dependency relationship of the messages in the business process, and the message sorting efficiency is improved. The messages meeting the conditions are sent to the subscription queue, and the messages not meeting the conditions are reserved in the cache. According to the mechanism, the problem of disorder of messages of the same service caused by multiple switches and network delay of message middleware is effectively solved, and data inconsistency and service abnormity are avoided; unified sorting logic replaces repeated development of subscribers, so that the system complexity is reduced; through thread pool division, local cache storage and a cache strategy of messages which do not meet conditions, the interaction overhead is reduced, the message orderliness and low delay requirements are considered in a high-frequency transaction scene, and the processing throughput, the real-time performance and the resource utilization rate under high concurrency are improved.

The invention discloses a decentralized high-performance multicast method and system based on Gossip and RDMA, and relates to the field of computer network communication. The method has better reliability, realizes zero-loss transmission of data packets through message de-duplication, timeout retransmission, ACK / NACK convergence and a dynamic topology adaptation mechanism, ensures data consistency, and solves the problem of insufficient reliability of traditional UDP multicast; the method has the advantages that the real-time performance is high, the delay is low, the throughput is high, the zero copy and kernel bypass characteristics of the RDMA and the batch processing mechanism of the MPMC are combined, the average delay is lower than 10 microseconds, the throughput in a large data packet scene reaches 374GB / s, and the low-delay requirements of high-frequency transaction, high-performance calculation and the like are met; the method has high expansibility, is based on a decentralized architecture of an improved Gossip protocol, does not need core node maintenance topology, supports dynamic joining or quitting of nodes, can adapt to large-scale cluster expansion, and solves the expansibility bottleneck of centralized multicast.

The invention provides an NoC low-delay data transmission method based on a dynamic routing algorithm, relates to the technical field of data transmission, and aims to solve the technical problems that an existing NoC routing algorithm cannot adapt to a link dynamic load, is lack of congestion trend prejudgment, is slow in path search convergence and is insufficient in QoS differential scheduling. The method comprises the following steps: constructing a dynamic sensing module containing a double-branch LSTM time sequence prediction model, collecting states such as link bandwidth and queue length in real time, and predicting a congestion trend in 50-100ms in the future; constructing a multi-objective evaluation function taking delay as a core, and dynamically adjusting the weight according to the QoS level; solving an optimal path by adopting an improved ant colony algorithm which introduces a congestion penalty and pruning strategy; during transmission, dynamic reselection is triggered through a pre-calculation + fast matching mechanism; and iteratively optimizing the prediction model based on incremental learning. According to the method, congestion is avoided in advance, the path search efficiency and the transmission reliability are improved, the delay is remarkably reduced compared with a traditional algorithm, and the method is adaptive to delay sensitive scenes such as a high-performance processor and an AI chip.

The invention discloses an ultra-low delay live broadcast method, system and device based on edge calculation, and a medium, and relates to the technical field of real-time audio and video interaction. The method comprises the steps that a target edge computing node receives an original media stream; monitoring an uplink network link and a downlink network link of the anchor end and the target edge computing node in real time, and determining a network link quality parameter; acquiring a historical network link quality parameter, and setting a link degradation standard and a link excellent standard according to the historical network link quality parameter; determining a target compensation strategy according to the network link quality parameter, a first preset condition and a second preset condition; and the target edge computing node processes the original media stream by adopting the target compensation strategy to generate a compensated media stream, and forwards the compensated media stream to a receiving end. By adopting the scheme, the overall performance of ultra-low delay live broadcast can be improved.

The invention relates to the technical field of high-performance computing, and provides an inter-thread data sharing method, electronic equipment, a storage medium and a program product.The method comprises the steps that a plurality of threads in a thread block are divided into at least one cooperative thread group, and the threads in each cooperative thread group are from at least two different thread bundle groups; when a write operation of a first thread in any cooperative thread group is received, writing target data into a shared register resource associated with any cooperative thread group; and when a read operation of a second thread in any cooperative thread group for the target data is received, executing a synchronous operation, and reading the target data from the shared register resource after the execution is completed. According to the method, the cooperative thread group spanning different thread beam groups is constructed, and the shared register resources are utilized for data exchange, so that efficient data sharing is directly carried out among the threads spanning the thread beam groups through the register, and the method has the advantages of low delay, high bandwidth and capability of remarkably improving parallel computing performance.

The invention discloses a module and a method applied to FPGA (Field Programmable Gate Array) remote upgrade configuration data integrity verification. The module and the method are realized by FPGA logic resources. The configuration data integrity verification module comprises a message filling module, a message expansion function module, a compression iteration module, a constant parameter matrix and a top layer control module. The message filling module is used for receiving original configuration data; the message expansion function module is used for expanding the message blocks output by the message filling module; the compression iteration module is used for hash compression operation; the constant parameter matrix is used for storing constant values required by compression operation; and the top layer control module is used for completing the connection of the sub-modules. Compared with the existing technical scheme, the scheme can realize the integrity verification problem of the configuration data generated by random errors and malicious tampering; by adopting the mode of'pipeline + iteration ', the real-time performance and the low-delay characteristic are ensured, the consumption of the FPGA logic resources by the module is reduced, and the FPGA logic resources can be flexibly deployed on the small-capacity FPGA.

A high-speed matching-engine architecture is disclosed that sustains deterministic sub-microsecond latency while processing more than 10 million order messages per second per core on commodity multi-core processors. Orders reside in cache-aligned Data Holder Nodes whose occupancy and price-level boundaries are tracked with constant-time bitmask operations, eliminating pointer-chasing penalties. Per-core huge-page pools, SIMD copy kernels, and lock-free, cache-line-aligned queues further minimize TLB misses and coherence overheads. Overflow is handled by Push Back / Push Forward cascades that relocate the least- or most-prioritized orders between adjoining nodes without violating price-time priority. Node capacities vary monotonically with book depth and are re-tuned online by a lightweight machine-learning controller that maximizes cache-hit probability under changing market micro-structure. The design tightens spreads, raises match-rate revenue, and complies with stringent regulatory latency caps using standard x86-64, Arm, or other architectures.

The invention discloses a large model mixed load-oriented self-adaptive low-delay reasoning configuration generation method and device, computer equipment and a storage medium, and the method comprises the steps: determining a first token generation delay and an adjacent token delay interval which are historically configured on requests with different reasoning configurations, and obtaining tuples to form a configuration performance database, generating a delay prediction model by combining a least square method with the configuration performance database; dynamically dividing the historical request into a plurality of buckets according to the input length and the output length through a self-adaptive bucket dividing strategy; a configuration generator generates reasoning configuration for each bucket according to the input length and the output length of the historical request of each bucket; under the real mixed load, the problems of remarkable resource contention, queue head blockage, KV Cache switching overhead increase and the like are avoided in concurrent execution of long and short requests, and meanwhile, the problem of tail delay amplification is avoided, so that a reasoning system gives consideration to low delay and high throughput among different requests.

The invention discloses a phased array radar signal processing system with deterministic delay, and relates to the technical field of semiconductors, the system carries out equal-length wiring design on a link in a hardware level, a timestamp marking circuit is embedded in the link, a core processing module carries out multi-channel data alignment based on timestamp marks in a software level, and the data alignment is carried out based on the timestamp marks. The multi-channel data transmission delay deviation is solved through elastic buffer control, the most reasonable buffer depth and release phase parameters are determined through calculation, and therefore the buffer delay is minimized, the system achieves deterministic minimum delay through software and hardware collaborative design, data alignment and quick response are guaranteed, and the system is suitable for large-scale popularization and application. Low-delay and high-consistency transmission and processing of multi-channel signals are achieved, so that high-precision pointing control of radar beams and time consistency of multi-target tracking are achieved, and the high-synchronization and low-jitter requirements of phased array radar for high-speed signal processing are met.

The invention relates to the technical field of communication, in particular to a transmission layer ultra-low delay congestion control method assisted by physical layer information. The core of the method is as follows: a sending end continuously acquires physical layer channel quality information and predicts a future channel capacity change trend based on historical and current information sequences; and then, dynamically calculating and smoothly adjusting the size of a transmission layer congestion window through a predefined mapping relation according to a prediction result, actively reducing the window before predicting that the channel is deteriorated, and timely increasing the window when the channel is improved. In addition, the method also comprises a fault-tolerant mechanism, and automatically switches to a traditional congestion control mode when the prediction is misaligned by monitoring the deviation between the prediction and the reality. Through cross-layer information utilization and prospective control, the method aims to effectively reduce data transmission delay and jitter and improve the capability of a network to cope with channel dynamic changes and the overall stability.