32244 results about "Computer architecture" patented technology

A coherent, intelligent, packet-switched memory fabric enables predictive, cache-coherent access across distributed compute, accelerator, and memory resources using a Memory-Fabric Transaction Layer Protocol (MF-TLP). MF-TLP defines routable packet formats for read, write, vectorized, atomic, reduction, collective, and predictive-prefetch transactions executed by memory-centric network interface controllers (MC-NICs). Each MC-NIC performs packet parsing, address translation, coherence management, and near-memory arithmetic or tensor operations while coordinating with MF-TLP-aware switches providing hierarchical directory control, multi-path routing, and in-network aggregation. Vectorized and multimodal packets encode multiple addresses or tensor offsets to reduce scatter / gather overhead, and programmable caching and quality-of-service modules manage tiered memory and tenant fairness. MF-TLP supports extension headers for predictive prefetch, collective coordination, and tenant governance, operating across hierarchical leaf-spine topologies using Ultra-Ethernet Transport, InfiniBand, or CXL fabrics. The system delivers scalable, low-latency, memory-centric orchestration for large-language-model training, multimodal AI, and data-intensive analytics.

A computer system implements a unified framework integrating an adaptive elastic funnel (AEF) with a convergent intelligence fabric (CIF) for multi-agent AI collaboration. The system provides a universal multi-modal key-value subsystem for sharing partial computations, implements hybrid placement strategies for dynamic memory management, and incorporates quantum-resistant secure enclaves. The architecture integrates hardware acceleration through GPU-FPGA hybrid caching and neuromorphic processors, applies adaptive energy and thermal management across hardware generations, and implements autonomous flash resource orchestration with multi-dimensional wear management. The system orchestrates tensor workflows using hierarchical scheduling, enables cross-agent collaboration with privacy preservation, and supports continuous learning without catastrophic forgetting. This integration delivers unprecedented computational efficiency and security in high-dimensional decision-making environments while supporting incremental adoption through modular interfaces.

A scalable platform for orchestrating networks of collaborative AI agents utilizing modular hybrid computing architecture. The platform integrates classical, quantum, and neuromorphic computing paradigms through hardware-accelerated translation layers and cross-paradigm coordination mechanisms. A central orchestration engine manages interactions between domain-specific AI agents, dynamically distributing workloads across heterogeneous computing cores based on task complexity, computational requirements, and resource availability. The platform employs hardware-accelerated translation between paradigms, enabling efficient cross-paradigm information exchange while maintaining semantic consistency and computation integrity across different architectures. Specialized monitoring and optimization systems continuously adjust resource allocation and fine-tune performance across computing paradigms. Advanced cache management and fault tolerance mechanisms ensure reliable operation, while privacy-preservation techniques enable secure collaboration. The platform's modular architecture supports integration of different computational approaches, enabling complex multi-domain problem solving that leverages the unique advantages of each paradigm while maintaining system-wide efficiency, scalability, and coherence.

An example operation may include one or more of training a generative artificial intelligence (GenAI) model via execution of the GenAI model on descriptions and diagrams of a software architecture, receiving a plurality of different architecture views from a plurality of different domains of the software architecture, generating an architecture diagram of the plurality of domains of the software architecture in combination based on execution of the GenAI model on the plurality of different architecture views from the plurality of different domains, and displaying the architecture diagram of the plurality of domains of the software architecture via a user interface.

Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.

A system and method for adaptive image and video processing using a Persistent Cognitive Machine (PCM) architecture with visual strategy caching. The system receives degraded input media and extracts degradation fingerprints to query a PCM-based visual strategy cache containing previously successful processing strategies. When matching cached strategies are found above a relevance threshold, they are retrieved and applied directly. When no match exists, the input is processed through transform-domain networks to generate new strategies. A pattern synthesizer combines multiple strategies for complex degradation types. The system evaluates processing effectiveness using a feedback controller and stores successful strategies in the hierarchical cache. This cognitive approach enables real-time processing with continuously improving performance as the cache learns from successful patterns. The adaptive architecture eliminates redundant processing while maintaining high-quality output, making it suitable for diverse imaging and video applications requiring efficient enhancement capabilities with superior performance over traditional methods.

Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.

Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.

Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.

The invention provides a computing system and method for GPU computing power scheduling, and the method comprises the following steps: 1, obtaining computing task data, and carrying out the information collection of each task through receiving a to-be-processed computing task queue; according to the invention, through task information collection and deep analysis, and GPU resource omnibearing monitoring and workload prediction, deep understanding of tasks and GPU resources is realized, highly accurate computing power distribution can be carried out, resource waste is avoided, and the resource utilization rate is improved; advanced technologies such as a knowledge graph, mixed integer programming and deep reinforcement learning are fused through the intelligent scheduling model, the fusion mode is innovative in the GPU computing power scheduling field, the limitation of singleness of a traditional scheduling model is overcome, the method can better adapt to a complex and changeable computing environment, the task execution efficiency is optimized, and the task scheduling efficiency is improved. The adaptability and competitiveness of the whole system in a complex environment are remarkably improved, and an excellent solution is provided for the GPU computing power scheduling problem in the field of high-performance computing.

Apparatuses, systems, and methods for separate write enable signals for granular single pass metadata access operations. During an example write operation a memory may receive data bits and at least one metadata bit. A set of bit lines in a first column plane is selected and a first write enable signal is provided which enables writing data to each of that set of bit lines. A second set of bit lines in a second column plane is selected and a second write enable signal is provided which enables writing the at least one metadata bit to a selected subset of the second set of bit lines.

The invention provides a GPU computing power scheduling method based on a one-cloud multi-core heterogeneous computing power platform, and the method comprises the following steps: S1, carrying out heterogeneous resource registration and modeling, accessing hardware equipment containing multiple types of GPUs through a resource registration module, collecting the equipment model, the video memory capacity and performance index data, and carrying out heterogeneous resource modeling; constructing a resource feature database containing a topological relation, and supporting hybrid access of chips; s2, virtualized resource reconstruction: pooling a physical GPU into virtual GPU resources by adopting a hardware abstraction layer technology, realizing video memory isolation and calculation unit division through a containerization technology, and configuring each virtual GPU instance with an independent drive stack and a security sandbox; and S3, submitting a multi-modal task, receiving a CUDA / OpenCL calculation task submitted by a user, analyzing task demand parameters including a calculation core number, a video memory occupation amount and a data throughput threshold, and generating a task descriptor containing a priority label.

The invention discloses an agent architecture based on a multi-modal large model, which comprises an external support module and an internal core module, and is characterized in that the external support module comprises an input module; an output module; a large model capability module; the internal core module comprises a sensing module; a memory module; a portrait configuration module; a planning module; a tool use module; and an action module. According to the intelligent agent architecture based on the multi-modal large model, the efficient, flexible and extensible intelligent agent architecture is innovatively realized, and the problem that most of existing intelligent agents are single-function artificial intelligence systems and are difficult to meet the requirement for multi-capability combination in a complex application scene is effectively solved.

By implementing a new bitstream for a Delta-Quantization Parameter (DQP), a decoder is able to implement parallel decoding of multiple coding units within a largest coding unit. In some embodiments, the DQP is placed immediately after the mode information of the first coding unit. In some embodiments, the DQP is placed after the mode information of the first non-skipped coding unit. In some embodiments, the DQP is placed after the first non-zero coded block flag.

The invention discloses a processor and electronic equipment. The processor includes a computing unit including a tensor core configured to perform a matrix multiplication operation using a scaling factor, and a memory, the computing unit further including a scaling factor processing module configured to determine and cache a scaling factor for each tensor associated with the matrix multiplication operation, the computing unit further comprises at least one storage module arranged on a data path between the tensor core and the memory, and the at least one storage module is exclusively occupied by the tensor core when the tensor core executes tensor related operation. And the scaling factor processing module is arranged on the at least one storage module. At present, scaling factors and floating-point number quantization are completed by a vector calculation core, so that performance is reduced, and delay becomes high, and a scaling factor processing module arranged on a storage module in a calculation unit can improve the overall execution efficiency of low-precision matrix multiplication using the scaling factors.

A microprocessor includes execution units that execute macro-operations (MOPs), a decode unit that decodes architectural instructions into MOPs, an instruction fetch unit (IFU) having an instruction cache that caches architectural instructions and a macro-operation cache (MOC) that caches MOPs into which the architectural instructions are decoded. A prediction unit (PRU) predicts a series of fetch blocks (FBs) in a program instruction stream to be fetched by the IFU from the MOC if hit or from the instruction cache otherwise. A branch target buffer (BTB) caches information about previously fetched and decoded FBs. A counter of each BTB entry is incremented when the entry predicts the associated FB is present again. For each FB in the series, the PRU indicates whether the counter has exceeded a threshold for use deciding whether to allocate the MOPs into the MOC in response to an instance of decoding the instructions into the MOPs.

The invention discloses an SM4 encryption method based on an FPGA, and relates to the technical field of data encryption, and the method comprises the steps: obtaining to-be-encrypted plaintext data; a plurality of SM4 encryption cores are configured on the FPGA chip to perform parallel encryption operation on plaintext data to be encrypted; wherein each SM4 encryption core adopts a pipeline architecture, and the pipeline architecture comprises an access device, a round function arithmetic unit and a key adder; an extraction circuit based on physical noise and integrated on the FPGA chip is utilized to generate N-bit random numbers as encryption keys of each SM4 encryption core; handshake signals are collected to calculate the operation efficiency of each SM4 encryption core; adjusting FPGA resource allocation among the SM4 encryption cores by adopting a priority scheduling algorithm according to the operation efficiency; in the encryption operation process, power consumption equalization is carried out by adopting polynomial and logical operation hybrid calculation, and time sequence randomization is carried out by adopting a random waiting period. Aiming at the problem of weak anti-difference sensitivity in the prior art, the side channel attack resistance is improved.

The invention provides an EDA software implementation method and system for memory IP layout optimization, and relates to the technical field of memorizers, the method comprises the following steps: receiving a memory IP design parameter and an optimization target input by a user, and calling a matched basic unit module from a pre-established hierarchical memory IP library according to the design parameter; an initial memory IP layout scheme is generated based on the basic unit module, the initial memory IP layout scheme is rapidly evaluated by utilizing a neural network model, a plurality of optimized layout candidate schemes are generated by adopting a genetic algorithm, and each optimized layout candidate scheme comprises different basic unit arrangements, metal layer use strategies and buffer insertion positions; performing parallel simulation on the optimal layout candidate scheme, and selecting an optimal layout scheme; and performing post-simulation verification on the optimal layout scheme, wherein the post-simulation verification comprises static time sequence analysis, dynamic power consumption analysis and electromagnetic compatibility analysis.

The invention relates to the technical field of chip design, in particular to a system-on-chip design method and system and a medium. The method comprises the following steps that a chip design target and basic parameters are collected, a constraint condition set is generated through demand constraint analysis, the basic parameters of a system are subjected to parallel recombination, functional prototype data are generated, the functional prototype data are used for chip behavior design, functional unit groups are generated, a network architecture is reconstructed to form a functional module network, and the functional module network is used for chip behavior design. And carrying out clock domain mapping and competition compensation processing based on the network to obtain a function scheduling sequence, carrying out resource matrix remapping on the basic parameters according to the function scheduling sequence, generating hardware abstract data, carrying out chip layout simulation, and finally generating a simulation chip blueprint. According to the system-on-chip design method, the more efficient system-on-chip design method is achieved.

Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.

The invention discloses a real-time interactive digital human system supporting high concurrency and an implementation method thereof, and relates to the technical field of digital human interaction.The system comprises a model instance pool module used for loading the weight of a deep learning model to a shared memory area through the memory mapping technology; the multi-thread scheduling module is used for scheduling user requests by adopting a lock-free queue and a dynamic priority algorithm; the asynchronous pipeline processing module is composed of decoupled micro-services, and the modules are connected in series through asynchronous message queues; the client SDK is used for dynamically switching a rendering mode according to terminal hardware performance and network conditions; the elastic capacity expansion and contraction module is used for monitoring resource loads in real time and automatically adjusting the number of service instances; and the audio and video synchronization calibration module is used for ensuring that the synchronization error of the audio and video frames is lower than a preset threshold value through a timestamp alignment algorithm. According to the scheme, core challenges in a high-concurrency digital human interaction scene can be systematically solved, and innovative support is provided for large-scale real-time application.

The embodiment of the invention provides an instruction processing method and a processor, and the method comprises the steps: obtaining a to-be-executed instruction, and determining a conflict type of the to-be-executed instruction; distributing a physical register for the to-be-executed instruction based on the conflict type; determining a dependency conflict condition and a resource conflict condition of the to-be-executed instruction, and determining an execution sequence of the to-be-executed instruction based on the dependency conflict condition and the resource conflict condition; determining a target execution unit based on the execution sequence, and sending the instruction to be executed to the target execution unit; and controlling the target execution unit to execute the to-be-executed instruction, and writing the to-be-executed instruction into the physical register when the to-be-executed instruction is executed, so that efficient out-of-order execution is realized through refined conflict detection, resource allocation and instruction scheduling, and the performance of the RISC-V processor can be remarkably improved. And the adaptability to complex applications is enhanced.

The invention discloses a memory fault repairing method and device, equipment, a medium and a computer program product, and relates to the technical field of computers.The memory fault repairing method includes the steps that memory error information sent by a memory controller is obtained, a fault target memory page can be positioned, and a standby memory page is obtained from a standby memory pool; the memory address mapping table is updated, the physical address of the target memory page with the fault is mapped to the physical address of the standby memory page, the repairing process does not depend on triggering of a system management interrupt mechanism, memory repairing in the system running stage is achieved, the system downtime caused by memory fault repairing is shortened, and therefore the memory repairing efficiency is improved. The problem of high delay in memory fault processing can be solved, and the technical effect of improving the memory fault repairing efficiency is achieved.

The invention relates to a dynamic adjustable multi-core cooperation mechanism and power consumption optimization method and system based on an RISC-V architecture. The method comprises the following steps: 1) initializing a dynamic adjustable multi-core cooperation system; comprising the steps that a hardware module is initialized, and the hardware module comprises a high-performance core P-core, a low-power-consumption core E-core, a hardware scheduling unit HSU and a power management unit PMU; loading a task queue, and marking task characteristics; 2) core state monitoring; comprising the following steps: an HSU monitors a core state; the power management unit PMU monitors voltage and frequency; 3) dynamic task scheduling; comprising the steps that task characteristics are allocated to a high-performance core P-core or a low-power-consumption core E-core; the idle core enters a low-power-consumption mode; and 4) self-adaptive energy saving is realized, and task migration is carried out. And through a dynamic task scheduling and energy-saving optimization algorithm, the flexibility and efficiency of the RISC-V multi-core processor are remarkably improved.

An FPGA-based accelerator for bootstrappable fully homomorphic encryption (FHE) employs (1) acceleration of scalar arithmetic operations using a multi-word approach for efficient utilization of standard-width components (multipliers / adders) on custom-width operands; (2) a performant, shift-based modular reduction technique that avoids the need for expensive multipliers; (3) an improved datapath for an expensive Key Switch operation; and (4) an efficient organization of on-chip memory for storing custom-width operands and supplying them at high bandwidth to computation units.

According to the instruction processing system, method and device provided by the invention, the instructions can be efficiently and smoothly distributed and run through the at least one processing module of the processor, and different instruction distribution logics are adopted based on different types of business processing instructions through two-stage instruction distribution, so that the service processing efficiency is improved. The business processing instructions are stored in the target storage area and then scheduled to the instruction execution module, so that quick distribution and hardware support of different types of business processing instructions are realized, the instruction distribution efficiency is greatly improved, complex calculation tasks can be flexibly and efficiently processed, instruction scheduling can be performed according to the priorities of the business processing instructions, and the service processing efficiency is improved. The key business operation is ensured to be responded and processed in time, and the overall performance and the operation efficiency of the database processor are effectively improved. The technical effect of flexibly and efficiently processing the database acceleration task is achieved.

A robotic emulation device includes a processor, memory and multimedia interfaces to capture a video signal from a target device, analyze it, and transmit manipulation control signals to the target device input by emulating a peripheral input device, wherein the manipulation control signals determine manipulation or selection of a target interface control associated with a first user interface encoded and transmitted in the video signal. Furthermore, the robotic emulation device may be connected via an embedded transceiver to at least one computer or computer tenant for relaying the captured video data for analysis, and based on the analysis, applying inferred manipulation semantics.

The invention discloses a prefetch instruction conversion optimization method based on memory access mode virtualization, which comprises the following steps of: when an executable file is executed in a dynamic instruction conversion mode, acquiring an address memory access mode of a prefetch instruction of x86 architecture, and analyzing an operand and an offset calculation mode of the prefetch instruction; according to an address memory access mode, an operand and an offset calculation mode, an instruction or an instruction sequence of an ARM architecture capable of completing memory address calculation and a prefetching function is constructed, a prefetching instruction of an x86 architecture is replaced with a corresponding ARM instruction or instruction sequence to complete instruction dynamic conversion, and conversion of the prefetching instruction of a complex address mode under the x86 architecture is achieved. And the execution reliability of the executable file in the dynamic instruction conversion mode is improved.

The invention discloses an extension equipment function configuration method and device, computer equipment and a storage medium, and relates to the technical field of data processing. According to the method, a hardware and firmware collaborative dynamic configuration framework is constructed, and a receiving queue is adopted at an extension equipment end to trigger a central processing unit firmware processing mechanism; in combination with virtualization design of a shadow configuration space and a shadow register, dynamic reconstruction of configuration parameters and an address mapping strategy during operation is realized; a host end supports configuration space access, base address register remapping and memory data transmission interaction through a transaction generation and routing mechanism driven by an event type. Hardware solidification limitation of traditional extension equipment is broken through through software and hardware decoupling design, the problems that function extension capacity is insufficient, resource dynamic allocation is difficult and protocol updating and virtualization scenes cannot be adapted are solved, and the technical effects of improving configuration reconstruction efficiency and address space utilization rate and supporting virtual function creation are achieved. And the adaptability of the equipment in cloud computing and edge computing environments is enhanced.