Non-volatile memory and method with memory planes alignment

Abstract

A non-volatile memory is constituted from a set of memory planes, each having its own set of read / write circuits so that the memory planes can operate in parallel. The memory is further organized into erasable blocks, each for storing a logical group of logical units of data. In updating a logical unit, all versions of a logical unit are maintained in the same plane as the original. Preferably, all versions of a logical unit are aligned within a plane so that they are all serviced by the same set of sensing circuits. In a subsequent garbage collection operation, the latest version of the logical unit need not be retrieved from a different plane or a different set of sensing circuits, otherwise resulting in reduced performance. In one embodiment, any gaps left after alignment are padded by copying latest versions of logical units in sequential order thereto.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation-in-part of U.S. patent application Ser. No. 10 / 750,155, filed on Dec. 30, 2003.FIELD OF THE INVENTION [0002] This invention relates generally to non-volatile semiconductor memory and specifically to those having a memory block management system optimized for operating multiple memory planes in parallel, where each plane is serviced by its own set of read / write circuits. BACKGROUND OF THE INVENTION [0003] Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, and retaining its stored data even after power is turned off. Also, unlike ROM (read only memory), flash m...

AI Technical Summary

Benefits of technology

[0022] The efficient use of system resource allows multiple logical groups to be updated concurrently. This further increases efficiency and reduces overheads. Alignent for Memory Distributed over Multiple Memory Planes

[0032] In one embodiment, after two copies of a given data have been programmed in an earlier programming pass, a subsequent programming pass avoids programming the memory cells storing at least one of the two copies. In this way, at least one of the two copies will be unaffected in the event the subsequent programming pass aborts before completion and corrupts the data of the earlier pass.

Problems solved by technology

Thus, when a logical group is being updated, the distribution of logical units (and also the scatter of memory units that the updates obsolete) are limited in range.

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