2333 results about "Read-only memory" patented technology

Robotic surgical tools, systems, and methods for preparing for and performing robotic surgery include a memory mounted on the tool. The memory can perform a number of functions when the tool is loaded on the tool manipulator: first, the memory can provide a signal verifying that the tool is compatible with that particular robotic system. Secondly, the tool memory may identify the tool-type to the robotic system so that the robotic system can reconfigure its programming. Thirdly, the memory of the tool may indicate tool-specific information, including measured calibration offsets indicating misalignment of the tool drive system, tool life data, or the like. This information may be stored in a read only memory (ROM), or in a nonvolatile memory which can be written to only a single time. The invention further provides improved engagement structures for coupling robotic surgical tools with manipulator structures.

A method of making a microelectronic package includes providing a sacrificial layer having a first surface and providing an optoelectronic element having a front face including one or more contacts and a rear surface and securing the rear surface of the optoelectronic element over the first surface of the sacrificial layer. The one or more contacts are then electrically interconnected with one or more conductive pads on the sacrificial layer and a curable and at least partially transparent encapsulant is provided over the first surface of the sacrificial layer so as to encapsulate the optoelectronic element and the conductive pads. The encapsulant is then cured the sacrificial layer is at least partially removed so as to leave said one or more conductive pads on a bottom surface of the encapsulant, the bottom surface of the encapsulant defining the bottom of the package. The optoelectronic element may include a light sensitive chip such as an ultraviolet-erasable programmable read-only memory (UV EPROM) or a light emitting chip, such as a light emitting diode (LED).

A “Firmware-Based TPM” or “fTPM” ensures that secure code execution is isolated to prevent a wide variety of potential security breaches. Unlike a conventional hardware based Trusted Platform Module (TPM), isolation is achieved without the use of dedicated security processor hardware or silicon. In general, the fTPM is first instantiated in a pre-OS boot environment by reading the fTPM from system firmware or firmware accessible memory or storage and placed into read-only protected memory of the device. Once instantiated, the fTPM enables execution isolation for ensuring secure code execution. More specifically, the fTPM is placed into protected read-only memory to enable the device to use hardware such as the ARM® architecture's TrustZone™ extensions and security primitives (or similar processor architectures), and thus the devices based on such architectures, to provide secure execution isolation within a “firmware-based TPM” without requiring hardware modifications to existing devices.

A method and an apparatus for establishing an operating environment by certifying a code image received from a host over a communication link are described. The code image may be digitally signed through a central authority server. Certification of the code image may be determined by a fingerprint embedded within a secure storage area such as a ROM (read only memory) of the portable device based on a public key certification process. A certified code image may be assigned a hash signature to be stored in a storage of the portable device. An operating environment of the portable device may be established after executing the certified code.

A dynamically programmable security device. The device includes: a secure nonvolatile read only memory (NVMROM) for securely storing a unique device cipher key; a secure interface for dynamically loading authenticated application code; a cryptographic engine for encrypting, decrypting data and authenticating the application code; a secure random access memory (RAM) for storing the authenticated application code and application data; and a processor for executing the authenticated application code.

A computer system includes a dual basic input-output system (BIOS) read-only memory (ROM) system to initialize the computer. When the computer is first powered on or reset, the primary BIOS ROM is initially enabled. The computer analyzes the contents of the primary BIOS memory to detect data errors. If a data error is detected, a chip enable circuit disables the primary BIOS ROM and enables a secondary BIOS ROM containing essentially the same initialization instructions as the primary BIOS ROM. If no errors are detected in the secondary BIOS ROM, the initialization of the computer proceeds using the secondary BIOS ROM. As part of the initialization procedure, the contents of the secondary BIOS ROM are copied to a random access memory. The primary BIOS ROM can then be reprogrammed with the contents of the secondary BIOS ROM using the copy in random access memory, or from the secondary BIOS ROM itself.

The invention provides improved methods and apparatus for control using field and control devices that provide a virtual machine environment and that communicate via an IP network. By way of non-limiting example, such field device can be an “intelligent” transmitter or actuator that includes a low power processor, along with a random access memory, a read-only memory, FlashRAM, and a sensor interface. The processor can execute a real-time operating system, as well as a Java virtual machine (JVM). Java byte code executes in the JVM to configure the field device to perform typical process control functions, e.g., for proportional integral derivative (PID) control and signal conditioning. Control networks can include a plurality of such field and control devices interconnected by an IP network, such as an Ethernet.

Disclosed is a disk drive having a disk, a masked read-only memory (ROM) device, a reprogrammable nonvolatile memory device, and a microprocessor for executing program code. The disk has a magnetic data storage surface with embedded servo wedges for defining data storage tracks including reserve tracks. The masked ROM device stores program code for implementing a spindle motor controller, program code for implementing a portion of a servo controller for track following along a data storage track, and program code for implementing a portion of a disk controller for controlling writing disk data to and reading disk data from the reserve tracks. The reprogrammable nonvolatile memory device stores data parameters relating to the disk drive's configuration. The reserve tracks store program code for implementing a cache control system for controlling caching of disk data in a cache memory.

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

The present invention is directed toward providing a system for registering, locating, and identifying network servers within a data center containing many such servers. Parallel and serial port couplers with an erasable, programable read-only memory are encoded with a unique ID number, and a label with a bar code corresponding to the ID number is affixed to each coupler. A server to be installed in a data center has an encoded coupler attached to one of its communication ports, and information related to that particular server is stored in a system database. Upon encountering a problem with a network server, the system displays the logical name of the server at issue. The location and identification information for the server are retrieved from the system database and displayed to a technician responsible for the server at issue. Using the displayed location information, the technician reads the label on the coupler connected to the suspected server and verifies that the ID number on the coupler matches the ID number displayed for the server requiring service.

Systems and methods are provided for a device to engage in a zero-knowledge proof with an entity requiring authentication either of secret material or of the device itself. The device may provide protection of the secret material or its private key for device authentication using a hardware security module (HSM) of the device, which may include, for example, a read-only memory (ROM) accessible or programmable only by the device manufacturer. In the case of authenticating the device itself a zero-knowledge proof of knowledge may be used. The zero-knowledge proof or zero-knowledge proof of knowledge may be conducted via a communication channel on which an end-to-end (e.g., the device at one end and entity requiring authentication at the other end) unbroken chain of trust is established, unbroken chain of trust referring to a communication channel for which endpoints of each link in the communication channel mutually authenticate each other prior to conducting the zero-knowledge proof of knowledge and for which each link of the communication channel is protected by at least one of hardware protection and encryption.

A semiconductor memory card comprising a control IC 302, a flash memory 303, and a ROM 304. The ROM 304 holds information such as a medium ID 341 unique to the semiconductor memory card. The flash memory 303 includes an authentication memory 332 and a non-authentication memory 331. The authentication memory 332 can be accessed only by external devices which have been affirmatively authenticated. The non-authentication memory 331 can be accessed by external devices whether the external devices have been affirmatively authenticated or not. The control IC 302 includes control units 325 and 326, an authentication unit 321 and the like. The control units 325 and 326 control accesses to the authentication memory 332 and the non-authentication memory 331, respectively. The authentication unit 321 executes a mutual authentication with an external device.

A positioning and tracking system may comprise a monitoring station for receiving a location request and a user's identification code and transmitting a signal; a tracking device, which includes a signal receiver for receiving a signal from the monitoring station, including the user's identification code, a microprocessor/logic circuit for storing a first identification code, and generating a position signal; an erasable programmable read-only memory; a global positioning system logic circuit; a signal transmitter; and a plurality of transmitter/receiver stations for communicating between the tracking device and the monitoring station; wherein the tracking device compares the user's identification code to the stored identification code and upon determining that the user's identification code matches the stored identification code, the signal transmitter transmits the position signal to the monitoring station.

A method and apparatus for securely booting software components in an electronic device to establish an operating environment are described herein. According to an aspect of the invention, software components are to be executed in sequence in order to establish an operating environment of a device. For each software component, a security code is executed to authenticate and verify an executable code image associated with each software component using one or more keys embedded within a secure ROM (read-only memory) of the device and one or more hardware configuration settings of the device. The security code for each software component includes a common functionality to authenticate and verify the executable code image associated with each software component. In response to successfully authenticating and verifying the executable code image, the executable code image is then executed in a main memory of the device to launch the associated software component.

A security apparatus including a number input device (302), an address register (312) responsive to the number input device, an encryption schema memory (316) addressable by the address register to produce an output code and a relative address code, and address incrementing logic (310) responsive the relative address code and operative to increment the address register. The apparatus also preferably includes a PIN register (304) coupled to the number input device, a public code register (306) coupled to the number input device, and merging logic (308) merging outputs of the PIN register and the public code register to be input to the address register. The apparatus also preferably includes an output shift register operative to shift out the output code of the encryption schema memory. The encryption schema memory can be read only memory, writeable memory, or both.

An information display system having a housing with a location for receiving a document such as a book is provided. A location detection circuit is mounted on the housing adjacent the document and can determine any subjective selection of a location on the document. The document can have a plurality of indicia. When such indicia is selected, a control circuit can retrieve the information from a read only memory and appropriately display the information in an audible or visual manner.

A method and apparatus for booting a microprocessor system using a serial (e.g., NAND-type) flash memory array having a random-access (parallel, e.g., NOR-flash type) interface. The method includes loading a boot code loader stored in the serial (e.g., NAND-type) flash memory array into a RAM when power is turned on, according to a routine of a read-only memory (ROM) of the microprocessor; loading boot code stored in the serial flash memory into an internal or external (main) RAM of the microprocessor according to the boot code loader; loading application code stored in the serial flash memory into the main (RAM) memory according to the boot is code; and executing the application code. The system may be manufactured at a low cost compared to NOR-Flash based systems, while ensuring flexibility of a microprocessor.

A network interface configures a plurality of physical layer devices and a corresponding plurality of network interface devices to allow for the communication of network data between the physical layer devices and corresponding link partners. At least one of the network interface devices is configured as a master device that communicates management information and autonegotiation results with the physical layer devices, while the other network interface devices do not. A configuration source, such as a central processing unit (CPU) or electronic erasable programmable read only memory (EEPROM), receives the autonegotiation results from the physical layer devices, through the master device, and configures the media access controllers (MACs) of each of the network interface devices in accordance with the autonegotiation results. This forces the MACs into their respective proper configurations even though the network interface devices that are not master devices do not receive the autonegotiation results directly from their corresponding physical layer devices.

The invention is a method for creating one time-use highly secure 2D barcodes, or secure two-dimensional barcodes, by utilizing machine readable physical tokens such as read only memory (ROM) or biometric data as a precursor and then applying a public key encryption algorithm and a time-stamp to otherwise standard 2D barcode generation schemas.