66 results about "Read-only memory" patented technology

This invention provides a method for defining the encoding mode of a read-only memory (ROM) using metal wires. A substrate is provided, and a semiconductor ROM device is formed on the substrate. The top of the semiconductor device includes an interlayer dielectric layer, multiple spaced metal wires located within the interlayer dielectric layer, and a top metal layer. The continuity or disconnection of the metal wires determines the ROM's encoding mode. A photoresist layer is formed on the interlayer dielectric layer, with a thicker photoresist layer above the top metal layer and the area adjacent to the metal wires. For different products, the required encoding mode and corresponding photolithography energy are selected. Utilizing the loading effect of the photoresist layer on adjacent metals and the top metal layer, the photoresist layer on each product is opened using a photomask defining the top metal layer and the corresponding photolithography energy. The corresponding metal wires are etched according to the encoding mode of each product. This invention defines the ROM's encoding mode type by cutting the exposed metal wires, requiring only an additional metal wire etching step.

A compute expression link (CXL) memory controller includes a data conversion device that receives a fail bit map and converts the fail bit map into error correction code (ECC) predecoded information in a symbol unit, a read only memory (ROM) that stores the ECC predecoded information, and an ECC engine that performs a decoding operation based on the ECC predecoded information. The ECC predecoded information includes address information indicating an address in which an error occurs, error symbol position information indicating one or more symbols in which the error occurs from among symbols corresponding to the address, and error type information indicating an error type of the one or more symbols.

Defect tracking within a computing environment includes storing a retired page table within a read only memory (ROM) of a computing node. A hardware processor of the computing node detects one or more System-on-Chips (SoCs) within the computing node. The hardware processor reads the retired page table from the read only memory. The hardware processor compares records of the retired page table with the one or more SoCs within the computing node. For each record of the retired page table that matches the one or more SoCs within the computing node, one or more physical pages of a volatile memory of the one or more SoCs are retired based on each record.

A read-only memory (ROM) receives an instruction address from a requestor and provides a fetched instruction from the instruction address. A ROM patcher includes storage circuitry to store a bank of entries, each entry having a corresponding bank address and is configurable as either a patch address entry or a patch replacement entry. A first entry of the bank is configured as a first patch address entry storing address information indicating a first range of ROM addresses for a first patch of instructions. A plurality of entries of the bank following the first entry are configured as a plurality of patch replacement entries, each storing a replacement instruction of the first patch. Control circuitry determines if the instruction address hits in the bank, and when it does, the replacement instruction from one of the plurality of patch replacement entries is returned to the requestor in place of the fetched instruction.

The invention provides a method and a process for loading a program in an ROM (Read Only Memory) of an NVM (Non-Volatile Memory) solid-state disk, which belong to the technical field of program loading and comprise the following steps of: step 1, actively searching NOR FLASH and NAND FLASH; 2, automatic screening is carried out, an optimal convenient path is automatically screened, and an optimal loading mode is selected; the method comprises the following steps: firstly, in active search, firstly searching from NOR Flash, searching NAND FLASH when the NOR Flash cannot be searched, and selecting whether to search the NOR Flash firstly or the NAND FLASH firstly according to configuration in efuse; in the step 1, in active search, a plurality of boot points are divided into 16 segments, and each segment only contains 8 nand flash boot points. According to the method, the system program can be efficiently and stably loaded and operated by actively searching the NOR FLASH and the NAND FLASH, automatically screening the optimal convenient path and selecting the optimal loading mode; and in cooperation with a security verification mechanism, the correctness and accuracy of the data in the loading process are ensured.

A read-only memory (ROM) device comprises an active region extending along a first direction and a plurality of gates extending above and across the active region along a second direction perpendicular to the first. The plurality of gates, together with the active region, constitute a plurality of transistors. Each of the plurality of transistors is configured to store a data element. The active region extends continuously beneath and across more than four conductive gates of the plurality of gates.

A memory device includes a first portion of a memory array comprising a plurality of first read only memory (ROM) cells, each of the plurality of first ROM cells comprising a first transistor that has a first conductive type and electrically coupled to a first word line and a first bit line. The memory device includes a second portion of the memory array comprising a plurality of second ROM cells, each of the plurality of second ROM cells comprising a second transistor that has a second conductive type and electrically coupled to a second word line and a second bit line. The first word line and second word line extend along a first lateral direction, and the first bit line and second bit line extend along a second lateral direction perpendicular to the first lateral direction.

Embodiments of the present disclosure relate to read-only memories. The present description relates to a ROM comprising at least one first rewritable memory cell.

Enforcing attestation of read-only protected memory during attestation validity period. A client computer system identifies a change in a read-only protected memory protection status for a software component loaded at the client computer system. The client computer system then determines that a validity time period of an attestation report is unexpired. The attestation report comprises one or more attested properties, including one or more read-only memory protection (ROMP) attested properties for the software component. The client computer system also determines that at least one ROMP attested property for the software component is no longer valid due to the change in the read-only protected memory protection status for a software component. Based on the at least one ROMP attested property for the software component being no longer valid, the client computer system initiates a remedial action to prevent interaction of the software component with a relying party computer system.

The purpose is to enhance the enjoyment of the game. [Solution] In a gaming machine, the game control microprocessor comprises a CPU, a program executed by the CPU, a ROM storing information referenced by the program, a RAM capable of storing information updated by the program, a general-purpose register, a data register, and a flag register. The CPU writes first information to the RAM at the start of a variation performance indicating the result of a lottery. When the power to the gaming machine is cut off during the execution of the variation performance and then power is turned on to the gaming machine, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor. When the variation performance resumes after the machine has entered a waiting state for customers, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor.

Methods, systems, and devices for techniques for enhancing memory code reliability are provided. A memory device includes an array of memory cells; a page buffer; a controller; a read-only memory (ROM) configured to store read-only data for performing one or more memory operations; and a first replacement memory (REM) configured store a first replacement data. The first REM is accessible by the controller via at least one of the array of memory cells and the page buffer. The device further includes a second REM configured to store a second replacement data for replacing at least one of the read-only data stored in the ROM or the first replacement data stored in the first REM. The controller is configured to access the second REM while bypassing the page buffer and the array of memory cells.

The invention provides a chip BootLoader dual-mode configuration system, which belongs to the technical field of chip boot programs, is integrated in a chip ROM (Read Only Memory), and comprises an OTP (One Time Programmable) storage module, a dual-mode control module, a UART (Universal Asynchronous Receiver / Transmitter) communication module, a key generation module, a CRC32 verification module, a QSPI (Quantitative Serial Peripheral Interface) module and a command processing module, therefore, the multi-element scene is adapted, and the compatibility and the flexibility are greatly optimized. And a communication key and a program encryption key are generated by adopting a double-key differentiation mechanism based on the unique information of the chip, so that the security protection capability is remarkably improved, and illegal invasion and data leakage are completely eradicated. Therefore, safe, flexible and reliable chip guiding and configuration are realized, and the application requirements of the embedded chip in the fields of industrial control, automotive electronics, Internet of Things and the like are met.

The electronic device with a connector supporting a multi-connection standard includes a connector, a processor, a controller, an extended display identification read-only memory, a first multi-tasking circuit, and a second multi-tasking circuit. The first multi-tasking circuit is coupled to at least one signal pin of the connector, the processor, and the controller. The second multi-tasking circuit is coupled to the extended display identification read-only memory, the first multi-tasking circuit, the processor, and the controller. In an update state, the controller is electrically connected to the extended display identification read-only memory via the second multi-tasking circuit, and updates extended display identification data in the extended display identification read-only memory with update data.

Fixed patching protocols waste memory resources and increase boot-up latency. In contrast, example implementations include a patch controller that receives a stream of multiple patch units from a non-volatile patch memory. The patch controller parses a descriptor patch unit, which precedes a set of patch units in the stream. From the descriptor patch unit, the patch controller extracts a ROM-patch type and a count. The type indicates whether the succeeding set of patch units includes fully associative patch units, direct-mapped patch units, or a combination. The count indicates the quantity of patch units of each type following the descriptor. Based on the extracted type and count, the patch controller processes the stream by routing the patch units to a fully associative memory or a direct-mapped memory. This streaming protocol enables flexible allocation of patch resources, reduces storage overhead in non-volatile memory, and shortens boot-up time by supporting an end-of-stream marker.

An electronic device may have a plurality of defined life cycle stages and a one-time-programmable (OTP) memory comprising a plurality of life cycle bits, wherein respective bit patterns of the life cycle bits may correspond with respective life cycle stages of the defined life cycle stages. The electronic device may also have a boot code stored in read only memory and executable by a processor to receive a request to transition from a current life cycle stage to a next life cycle stage and, in response to the received request, automatically generate a bit pattern corresponding to the next life cycle stage of the plurality of defined life cycle stages and program the bit pattern corresponding to the next life cycle stage of the plurality of defined life cycle stages in the OTP memory during a time when the OTP memory is not user-accessible.

Embodiments of the present application provide a kind of rotary variable zero calibration method, device, electronic equipment and storage medium, wherein, method includes: drag motor rotor rotation and control its rotating speed;Control motor stator winding by three-phase alternating current inverter ASC enters three-phase short circuit, when the rotating speed of the motor rotor is greater than rotating speed threshold and the fluctuation state value of the rotating speed is less than fluctuation threshold, the three-phase current value of three-phase alternating current motor is acquired;According to the three-phase current value, the rotary variable zero is obtained;The rotary variable zero is written into read-only memory. Implement the above embodiment, can reduce error, so that the precision of the obtained rotary variable zero is higher.

The invention provides an AISC chip firmware starting method and device and a medium, and relates to the technical field of AISC chip firmware starting. The method comprises the steps that first firmware is loaded and operated from a read-only memory in an AISC chip; performing second firmware signature verification on the second firmware; if the signature verification of the second firmware is passed, skipping to the second firmware for execution through the first firmware; calling a hardware security module through the second firmware to perform overall signature verification on the firmware package; the firmware package is analyzed through the second firmware, and each firmware mirror image is written into a special memory area of the corresponding CPU core; releasing reset signals of other CPU cores except the first CPU core through the second firmware, so that other CPU cores obtain and execute corresponding firmware mirror images from respective special memory areas; enabling the first CPU core to start executing the firmware mirror image of the first CPU core; according to the invention, the protection capability of the system in a high-security scene is obviously improved.

The application relates to the technical field of intelligent air conditioners, and discloses a method, device and equipment for air conditioner energy consumption statistics and a storage medium. The method comprises the following steps: in the case that a first collection time corresponding to a first cycle length is reached, determining a first current energy consumption value of a set energy source of an air conditioner in a first current cycle; and storing the first current energy consumption value in a static random access memory (SRAM), wherein the set energy source comprises one or both of solar energy and municipal energy; in the case that a second collection time corresponding to a second cycle length is reached, updating the first energy consumption value stored in the SRAM in a second current cycle to an electrically erasable programmable read-only memory (EEPROM) for accumulation, so as to obtain a corresponding current cumulative energy consumption value, wherein the second cycle length is greater than the first cycle length; and determining an energy consumption value of the set energy source of the air conditioner in a unit statistical period according to the cumulative energy consumption value. In this way, the accuracy of air conditioner energy consumption data no longer depends on the real-time quality of a communication network, the stability and accuracy of air conditioner energy consumption statistics are improved, and user experience is improved.

Methods, systems, and devices for techniques for enhancing memory code reliability are provided. A memory device includes an array of memory cells; a page buffer; a controller; a read-only memory (ROM) configured to store read-only data for performing one or more memory operations; and a first replacement memory (REM) configured store a first replacement data. The first REM is accessible by the controller via at least one of the array of memory cells and the page buffer. The device further includes a second REM configured to store a second replacement data for replacing at least one of the read-only data stored in the ROM or the first replacement data stored in the first REM. The controller is configured to access the second REM while bypassing the page buffer and the array of memory cells.

An on-chip logic built-in self-test (LBIST) apparatus has a first autonomous in-system test (AIT) read only memory (ROM) storing a built-in self-test (BIST) pattern and a first set of jump instructions for reading a multiple input signature register (MISR) signature from a second AIT memory. The second AIT memory stores the MISR signature and a second set of jump instructions. The second set of jump instructions returns program execution to the first AIT ROM.

The invention relates to the technical field of industrial communication networks, in particular to a BootROM code patch loading method and system based on a CPU Cache mechanism, and the method comprises the steps: obtaining patch configuration data; a Cache controller of the CPU is initialized, an instruction Cache and a data Cache are enabled, and a write allocation strategy and a consistency monitoring mechanism are started; writing the patch code block into a target address of the address space of the BootROM, using the read-only attribute of the BootROM to enable the write-in operation to distribute a cache line in the data Cache to store the patch code block, and marking the patch code block as a modified state; and when the CPU executes to a target address, triggering the instruction Cache to be missing, obtaining patch code blocks from the data Cache through a consistency monitoring mechanism, and executing the patch code blocks, so that the BootROM codes are dynamically repaired. The system comprises a control module, a Cache management module, a bus interface module and a patch storage module. According to the method, online update of the BootROM code is realized through a Cache mechanism, and the technical problem that a read-only memory cannot be directly modified is solved.

An apparatus, method, and portable navigation device for determining a PRN code to correlate with a ranging code on a satellite-based navigation system receiver are provided. An example satellite-based navigation system receiver may include a plurality of tracking channels, wherein each tracking channel of the plurality of tracking channels is configured to generate a pseudo-random code based at least in part on a first code value from a first position in a code sequence and a second code value from a second position in the code sequence. The example satellite-based navigation system receiver may further comprise a read-only memory configured to store the code sequence. A second plurality of the plurality of tracking channels may be configured to receive the first code value and the second code value from the read-only memory.

The application discloses a data reading method and device of a flash memory device, a terminal device and a computer storage medium, and comprises the following steps: receiving a read command sent by a host, wherein the read command comprises a logical address to be read of data to be read; judging whether the read command hits a first primary mapping table in a read-only memory according to the logical address to be read and a preset block address bitmap; if the first primary mapping table is not hit, finding a second logical address of a second primary mapping table located in a flash memory according to a preset secondary mapping table, and finding the data to be read corresponding to the logical address to be read according to the second primary mapping table. The application can improve the hit rate of the read command in the flash memory device and improve the reading performance of the flash memory device.

Reduce the program size. [Solution] In a gaming machine, a predetermined circuit board used for the progress of the game includes a CPU, a ROM in which a program used by the CPU is stored, and a RAM that holds variables updated by the program, the CPU reads the program from the ROM, calls a predetermined module with an address and an input value as parameters based on the program, reads a comparison value and a candidate value based on the address in the module, updates the address, performs a comparison process that compares the input value with the comparison value, and the input value

The invention provides a code execution method and device of a read-only memory and electronic equipment. The method comprises the following steps: reading patch data from a first memory; analyzing the patch data to obtain patch code data; a first address corresponding to at least one patch function is obtained from the patch code data, the first address is used for pointing to the position of the patch function in a target code, and the target code is stored in a second memory; and executing the first patch code of the patch function corresponding to the first address, and setting the patch function in the target code in advance, so that the first memory only stores the first address corresponding to the patch function, thereby reducing the occupation of the first memory, solving the problem of small repairable data volume caused by small capacity of the first memory, and improving the repairable data volume. According to the scheme, the requirements of repairing or function extension of large-scale target codes can be met.

A method of generating an IC layout diagram includes dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two, based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the logic patterns in a storage device.

The application provides a secure power-on method and system of a system-on-chip, a chip and an electronic device. The secure power-on method specifically comprises: triggering a read-only memory in a microcontroller to configure a chip register in a case where a one-time programmable memory cannot configure the chip register; triggering an electrically erasable read-only memory to configure the chip register in a case where the microcontroller cannot normally start; and triggering the system-on-chip to perform a reset start and enter a normal working state in a case where the electrically erasable read-only memory cannot configure the chip register. Through the technical scheme provided in the application, the microcontroller, the one-time programmable memory and the electrically erasable read-only memory are simultaneously used to control the power-on process of the system-on-chip, especially the register configuration link in the power-on process, thereby guaranteeing the safety and reliability of the whole power-on process of the system-on-chip.

The invention discloses a reconfigurable digital filter based on an FPGA (Field Programmable Gate Array), which comprises an FPGA chip, and the FPGA chip comprises an ROM (Read Only Memory) module, an RAM (Random Access Memory) module, a multiplier, an accumulator, a pulse counter, a filtering control module and a reconfiguration interface, the inertial device comprises at least one gyroscope and an accelerometer, and the gyroscope and the accelerometer both output pulse signals to the FPGA chip; the pulse counter counts the pulse signals, converts count values of the N channels into floating-point numbers after the counting period is ended, and stores the floating-point numbers into the RAM module; the filtering control module controls the multiplier, the accumulator, the ROM module and the RAM module to work cooperatively, multiplexes the same group of computing resources to process signals of N channels in series, and completes filtering calculation according to an IIR filter algorithm; the reconfiguration interface can adjust the order and coefficient of the IIR filter online. The filter replaces DSP filtering, the FPGA resource utilization rate is increased, the chip cost is reduced, the execution efficiency of an inertial navigation system is improved, and online reconstruction can be carried out to adapt to different filtering requirements.