125 results about "Read-only memory" patented technology

The disclosure describes a read-only memory array and a read-only memory thereof. The read-only memory array includes common-source lines, word bit lines perpendicular to the common-source lines, and sub-memory arrays. The common-source lines include a first common-source line and a second common-source line. The word bit lines include a first word bit line and a second word bit line. Each sub-memory array includes four memory cells. Each memory cell has a control terminal coupled to the corresponding word bit line and a data terminal coupled to the corresponding common-source line and the corresponding word bit line. The read-only memory includes a field-effect transistor and a capacitor formed in a semiconductor region. The field-effect transistor and the capacitor commonly include a doped well. The doped well, overlapping the common-source line, is coupled to the common-source line.

The invention relates to the technical field of computers, and discloses a program updating method on electronic equipment, equipment, a medium and a program product, a framework program of a bootstrap program is deployed on the electronic equipment, the framework program comprises a first-level unit and a second-level unit, and the second-level unit comprises a first area and a second area. The first area comprises current program information of the bootstrap program, the second area comprises backup program information of the bootstrap program, and the method comprises the following steps: executing first-level unit implementation: judging whether a bootstrap program updating condition is met or not according to description information of the current program information in the first area and description information of the backup program information in the second area; and updating the current program information in the first area through the backup program information in the second area in response to the fact that the boot program updating condition is met. According to the method and the device, the self-upgrading of the program can be realized under the condition of not depending on read-only memory hardware, and the equipment cost is reduced.

The invention discloses a double-patch updating method, device, equipment, medium and product of a starting read-only memory, and relates to the technical field of chip updating, the starting read-only memory is located in a server management chip, and the server management chip is provided with a one-time programmable memory isolated from the starting read-only memory. The method for burning the preset shadow patch code by the one-time programmable memory comprises the following steps of: starting the read-only memory, and detecting whether the read-only memory is successfully started within a preset time period; if the starting is not successful, triggering a shadow patch process, and executing a preset shadow patch code in the one-time programmable memory; if starting succeeds, triggering an online patch updating process based on the patch updating request, and loading a target segment patch code; and loading the target segment patch code subjected to segment security verification to a random access memory of the server management chip so as to redirect the access request to a new patch code address in the random access memory. And patch updating in the read-only memory starting process is realized.

A method includes storing, by a microcontroller, cache data of the microcontroller into a dynamic random-access memory (DRAM) in response to the microcontroller receiving a power-off command. The method includes operating, by a DRAM controller, the DRAM in a standby state in response to the microcontroller storing the cache data into the DRAM. The method includes determining, by the DRAM controller and when the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof. The method includes determining, by the DRAM controller, whether a suspend to storage condition is satisfied based on the time characteristic, the charge characteristic, or the combination thereof. The method includes storing, by the DRAM controller, the cache data of the DRAM into a read-only memory (ROM) in response to the suspend to storage condition being satisfied.

The invention discloses a read-only memory program correction system and method, and relates to the technical field of computers, the read-only memory program correction system comprises a program comparison module, a program correction module and an address management module; the program comparison module is used for obtaining a standard signature value and an actual signature value and comparing the standard signature value with the actual signature value to obtain a comparison result of each program segment; the program correction module is used for controlling the system on chip to obtain a correction program corresponding to the target program segment from the external storage device and storing the correction program into the target storage unit; and the address management module is used for mapping an address field of the target program segment in the read-only memory into a target address field of the correction program in the target storage unit. When the wrong target program segment is started, the wrong target program segment is directly corrected and replaced by the correction program through the mapping relation, so that segmented correction and replacement of the wrong program segment are realized, the risk that the replaced correction program is physically attacked or tampered is reduced, and the reliability and safety of the starting program are improved.

The embodiment of the invention provides a chip system, a debugging method and electronic equipment, and is applied to the technical field of chip data security design. The chip system comprises a processor and a read-only memory. The processor includes a JTAG interface and a first data interface. The read-only memory comprises a second data interface. Wherein the processor is used for performing JTAG debugging based on the JTAG interface when a data reading path between the first data interface and the second data interface is in a closed state. And when the data reading path is in the open state, keeping the JTAG interface in the closed state. According to the embodiment of the invention, the JTAG interface and the data reading path are set to be mutually exclusive, so that the risk of reading important data in the read-only memory based on JTAG access is avoided.

Enforcing attestation of read-only protected memory during attestation validity period. A client computer system identifies a change in a read-only protected memory protection status for a software component loaded at the client computer system. The client computer system then determines that a validity time period of an attestation report is unexpired. The attestation report comprises one or more attested properties, including one or more read-only memory protection (ROMP) attested properties for the software component. The client computer system also determines that at least one ROMP attested property for the software component is no longer valid due to the change in the read-only protected memory protection status for a software component. Based on the at least one ROMP attested property for the software component being no longer valid, the client computer system initiates a remedial action to prevent interaction of the software component with a relying party computer system.

Methods, systems, and devices for information broadcast techniques for stacked memory architectures are described. A semiconductor system may include multiple instances of interface circuitry of a semiconductor die that are each operable for accessing a respective set of one or more memory arrays of one or more other semiconductor dies, as well as read-only storage for storing information that is common to the multiple instances of the interface circuitry. In some implementations, such read-only storage may include one-time programmable memory elements (e.g., fuses, antifuses) that are located in at least one of the one or more other semiconductor dies, and are accessible by each of the multiple instances of interface circuitry. The read-only storage may store information that supports common aspects of interface circuitry operations such as initialization operations, evaluation operations, configuration operations, access operations, or other operations, which may be broadcast to the multiple instances of interface circuitry.

This invention provides a method for defining the encoding mode of a read-only memory (ROM) using metal wires. A substrate is provided, and a semiconductor ROM device is formed on the substrate. The top of the semiconductor device includes an interlayer dielectric layer, multiple spaced metal wires located within the interlayer dielectric layer, and a top metal layer. The continuity or disconnection of the metal wires determines the ROM's encoding mode. A photoresist layer is formed on the interlayer dielectric layer, with a thicker photoresist layer above the top metal layer and the area adjacent to the metal wires. For different products, the required encoding mode and corresponding photolithography energy are selected. Utilizing the loading effect of the photoresist layer on adjacent metals and the top metal layer, the photoresist layer on each product is opened using a photomask defining the top metal layer and the corresponding photolithography energy. The corresponding metal wires are etched according to the encoding mode of each product. This invention defines the ROM's encoding mode type by cutting the exposed metal wires, requiring only an additional metal wire etching step.

A compute expression link (CXL) memory controller includes a data conversion device that receives a fail bit map and converts the fail bit map into error correction code (ECC) predecoded information in a symbol unit, a read only memory (ROM) that stores the ECC predecoded information, and an ECC engine that performs a decoding operation based on the ECC predecoded information. The ECC predecoded information includes address information indicating an address in which an error occurs, error symbol position information indicating one or more symbols in which the error occurs from among symbols corresponding to the address, and error type information indicating an error type of the one or more symbols.

Defect tracking within a computing environment includes storing a retired page table within a read only memory (ROM) of a computing node. A hardware processor of the computing node detects one or more System-on-Chips (SoCs) within the computing node. The hardware processor reads the retired page table from the read only memory. The hardware processor compares records of the retired page table with the one or more SoCs within the computing node. For each record of the retired page table that matches the one or more SoCs within the computing node, one or more physical pages of a volatile memory of the one or more SoCs are retired based on each record.

The invention relates to fast, low area self-testing of read only memory. A method for performing a fast read only memory (ROM) test is disclosed. In a first method, a signature is generated by performing a first set of N read operations with an extended read cycle and a subsequent second set of N read operations with a full-speed read cycle, where N is an integer greater than or equal to 2. The retrieved data is combined using a modulo addition operation and a modulo subtraction operation and stored in a signature register. In a second method, the signature is generated by performing two read operations with an extended read cycle, followed by two read operations with a full-speed read cycle. The retrieved data is combined using a rejection OR (XOR) operation and stored in a signature register. The final signature is compared to a predetermined value to determine if any error is detected. Both methods provide robust testing that can detect various ROM errors while minimizing test time and complexity.

Methods for performing a fast read-only memory (ROM) test are disclosed. In the first method, a signature is generated by performing a first set of N read operations utilizing an extended read-cycle, followed by a second set of N read operations utilizing an at-speed read-cycle, where N is an integer greater than or equal to 2. The retrieved data is combined using modulo addition and subtraction operations and stored in a signature register. In the second, a signature is generated by performing two read operations utilizing an extended read-cycle, followed by two read operations utilizing an at-speed read-cycle. The retrieved data is combined using exclusive OR (XOR) operations and stored in a signature register. The final signature is compared to a predetermined value to determine if any errors were detected. Both methods provide a robust test capable of detecting various ROM errors while minimizing test time and complexity.

The invention provides a method for generating a configuration interface. The method for generating the configuration interface comprises the following steps of: loading a UEFI Option ROM (Read Only Memory) driver of external equipment through a UEFI of main equipment, wherein the UEFI Option ROM driver is generated according to the UEFI driver and a configuration interface file; and dynamically analyzing a configuration interface file in the UEFI Option ROM driver through a file analyzer in the UEFI Option ROM driver, and creating a configuration interface option of a UEFI setting interface of the main equipment according to an analysis result. According to the configuration interface generation method provided by the invention, a user can flexibly configure and manage the configuration interface of the external equipment.

A read-only memory (ROM) receives an instruction address from a requestor and provides a fetched instruction from the instruction address. A ROM patcher includes storage circuitry to store a bank of entries, each entry having a corresponding bank address and is configurable as either a patch address entry or a patch replacement entry. A first entry of the bank is configured as a first patch address entry storing address information indicating a first range of ROM addresses for a first patch of instructions. A plurality of entries of the bank following the first entry are configured as a plurality of patch replacement entries, each storing a replacement instruction of the first patch. Control circuitry determines if the instruction address hits in the bank, and when it does, the replacement instruction from one of the plurality of patch replacement entries is returned to the requestor in place of the fetched instruction.

The invention provides a method and a process for loading a program in an ROM (Read Only Memory) of an NVM (Non-Volatile Memory) solid-state disk, which belong to the technical field of program loading and comprise the following steps of: step 1, actively searching NOR FLASH and NAND FLASH; 2, automatic screening is carried out, an optimal convenient path is automatically screened, and an optimal loading mode is selected; the method comprises the following steps: firstly, in active search, firstly searching from NOR Flash, searching NAND FLASH when the NOR Flash cannot be searched, and selecting whether to search the NOR Flash firstly or the NAND FLASH firstly according to configuration in efuse; in the step 1, in active search, a plurality of boot points are divided into 16 segments, and each segment only contains 8 nand flash boot points. According to the method, the system program can be efficiently and stably loaded and operated by actively searching the NOR FLASH and the NAND FLASH, automatically screening the optimal convenient path and selecting the optimal loading mode; and in cooperation with a security verification mechanism, the correctness and accuracy of the data in the loading process are ensured.

A method for programming an integrated circuit comprising one or more microprocessors, at least one random-access memory, at least one read-only memory and at least one non-volatile rewritable memory, at least one high-speed bus and one bus, and functional components, wherein a step of recording, in the non-volatile rewritable memory, a set of executable computer codes is carried out, the method comprising booting steps according to an execution mode or according to a programming mode comprising: ⋅an original step of recording, in a non-erasable mass memory of the integrated circuit during the manufacture of the integrated circuit: ⋅a set of static resources comprising the digital development tools forming an assisted development environment executable by a browser and the technical documentation relating to the programming of the integrated circuit; ⋅and a boot code according to a programming mode; ⋅wherein the booting step according to the programming mode consists in controlling: ⋅querying the state of the hardware and software dynamic resources of the integrated circuit and a step of recording, in a local rewritable memory, the state for each of the hardware and software resources; ⋅activating the transfer of the static resources and the dynamic resources to a connected external computer device.

A read-only memory (ROM) device comprises an active region extending along a first direction and a plurality of gates extending above and across the active region along a second direction perpendicular to the first. The plurality of gates, together with the active region, constitute a plurality of transistors. Each of the plurality of transistors is configured to store a data element. The active region extends continuously beneath and across more than four conductive gates of the plurality of gates.

A memory device includes a first portion of a memory array comprising a plurality of first read only memory (ROM) cells, each of the plurality of first ROM cells comprising a first transistor that has a first conductive type and electrically coupled to a first word line and a first bit line. The memory device includes a second portion of the memory array comprising a plurality of second ROM cells, each of the plurality of second ROM cells comprising a second transistor that has a second conductive type and electrically coupled to a second word line and a second bit line. The first word line and second word line extend along a first lateral direction, and the first bit line and second bit line extend along a second lateral direction perpendicular to the first lateral direction.

Embodiments of the present disclosure relate to read-only memories. The present description relates to a ROM comprising at least one first rewritable memory cell.

Enforcing attestation of read-only protected memory during attestation validity period. A client computer system identifies a change in a read-only protected memory protection status for a software component loaded at the client computer system. The client computer system then determines that a validity time period of an attestation report is unexpired. The attestation report comprises one or more attested properties, including one or more read-only memory protection (ROMP) attested properties for the software component. The client computer system also determines that at least one ROMP attested property for the software component is no longer valid due to the change in the read-only protected memory protection status for a software component. Based on the at least one ROMP attested property for the software component being no longer valid, the client computer system initiates a remedial action to prevent interaction of the software component with a relying party computer system.

The utility model discloses a remote IO core board supporting remote video monitoring and a plurality of communication modules, which comprises a micro-control unit, a communication pin socket, an interface board socket, a voltage regulation module, a plurality of communication modules, a read-only memory, an indicator light module and a camera module, the micro-control unit is respectively connected with corresponding pins of the interface board socket, the micro-control unit is connected with and controls the indicating lamp module, the micro-control unit is connected and interacted with the read-only memory, and the power supply is connected with the voltage regulation module through the interface board socket to respectively supply power to the communication pin header socket and the micro-control unit. A plurality of communication modules are mounted on the communication pin header socket; the camera module is connected with the micro-control unit through the interface board socket. According to the utility model, the remote video monitoring function is realized, and the operation condition of field equipment can be checked in real time.

The purpose is to enhance the enjoyment of the game. [Solution] In a gaming machine, the game control microprocessor comprises a CPU, a program executed by the CPU, a ROM storing information referenced by the program, a RAM capable of storing information updated by the program, a general-purpose register, a data register, and a flag register. The CPU writes first information to the RAM at the start of a variation performance indicating the result of a lottery. When the power to the gaming machine is cut off during the execution of the variation performance and then power is turned on to the gaming machine, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor. When the variation performance resumes after the machine has entered a waiting state for customers, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor.

Methods and systems related to mask programmable memory using shared drain and gate connections are disclosed herein. A read only memory disclosed herein includes a transistor having a read terminal and a bit terminal. The read terminal and the bit terminal are a source and a drain of the transistor. The transistor also a word line coupled to a gate of the transistor, and a plurality of bit lines programmatically coupled to the bit terminal. The plurality of bit lines can be programmatically coupled by a set of mask programmable vias that couple the bit lines to the bit terminal.

Methods, systems, and devices for techniques for enhancing memory code reliability are provided. A memory device includes an array of memory cells; a page buffer; a controller; a read-only memory (ROM) configured to store read-only data for performing one or more memory operations; and a first replacement memory (REM) configured store a first replacement data. The first REM is accessible by the controller via at least one of the array of memory cells and the page buffer. The device further includes a second REM configured to store a second replacement data for replacing at least one of the read-only data stored in the ROM or the first replacement data stored in the first REM. The controller is configured to access the second REM while bypassing the page buffer and the array of memory cells.

The invention provides a chip BootLoader dual-mode configuration system, which belongs to the technical field of chip boot programs, is integrated in a chip ROM (Read Only Memory), and comprises an OTP (One Time Programmable) storage module, a dual-mode control module, a UART (Universal Asynchronous Receiver / Transmitter) communication module, a key generation module, a CRC32 verification module, a QSPI (Quantitative Serial Peripheral Interface) module and a command processing module, therefore, the multi-element scene is adapted, and the compatibility and the flexibility are greatly optimized. And a communication key and a program encryption key are generated by adopting a double-key differentiation mechanism based on the unique information of the chip, so that the security protection capability is remarkably improved, and illegal invasion and data leakage are completely eradicated. Therefore, safe, flexible and reliable chip guiding and configuration are realized, and the application requirements of the embedded chip in the fields of industrial control, automotive electronics, Internet of Things and the like are met.

The electronic device with a connector supporting a multi-connection standard includes a connector, a processor, a controller, an extended display identification read-only memory, a first multi-tasking circuit, and a second multi-tasking circuit. The first multi-tasking circuit is coupled to at least one signal pin of the connector, the processor, and the controller. The second multi-tasking circuit is coupled to the extended display identification read-only memory, the first multi-tasking circuit, the processor, and the controller. In an update state, the controller is electrically connected to the extended display identification read-only memory via the second multi-tasking circuit, and updates extended display identification data in the extended display identification read-only memory with update data.

Methods of performing updates to a software image that is disposed in a read only memory or a one time programmable memory device are disclosed. The method includes causing an ECC error at the beginning of a function that has been modified. This ECC error causes an exception. The exception handler determines the address where the ECC error was detected was located and searches a dictionary. This dictionary contains entries that each have an original address in the ROM or OTP Memory and the patch address in a nonvolatile writable memory. The exception handler then causes the processing unit to jump to the patch address, where a modified function is located.

Fixed patching protocols waste memory resources and increase boot-up latency. In contrast, example implementations include a patch controller that receives a stream of multiple patch units from a non-volatile patch memory. The patch controller parses a descriptor patch unit, which precedes a set of patch units in the stream. From the descriptor patch unit, the patch controller extracts a ROM-patch type and a count. The type indicates whether the succeeding set of patch units includes fully associative patch units, direct-mapped patch units, or a combination. The count indicates the quantity of patch units of each type following the descriptor. Based on the extracted type and count, the patch controller processes the stream by routing the patch units to a fully associative memory or a direct-mapped memory. This streaming protocol enables flexible allocation of patch resources, reduces storage overhead in non-volatile memory, and shortens boot-up time by supporting an end-of-stream marker.