20 results about "Read-only memory" patented technology

A read-only memory (ROM) receives an instruction address from a requestor and provides a fetched instruction from the instruction address. A ROM patcher includes storage circuitry to store a bank of entries, each entry having a corresponding bank address and is configurable as either a patch address entry or a patch replacement entry. A first entry of the bank is configured as a first patch address entry storing address information indicating a first range of ROM addresses for a first patch of instructions. A plurality of entries of the bank following the first entry are configured as a plurality of patch replacement entries, each storing a replacement instruction of the first patch. Control circuitry determines if the instruction address hits in the bank, and when it does, the replacement instruction from one of the plurality of patch replacement entries is returned to the requestor in place of the fetched instruction.

A read-only memory (ROM) device comprises an active region extending along a first direction and a plurality of gates extending above and across the active region along a second direction perpendicular to the first. The plurality of gates, together with the active region, constitute a plurality of transistors. Each of the plurality of transistors is configured to store a data element. The active region extends continuously beneath and across more than four conductive gates of the plurality of gates.

The purpose is to enhance the enjoyment of the game. [Solution] In a gaming machine, the game control microprocessor comprises a CPU, a program executed by the CPU, a ROM storing information referenced by the program, a RAM capable of storing information updated by the program, a general-purpose register, a data register, and a flag register. The CPU writes first information to the RAM at the start of a variation performance indicating the result of a lottery. When the power to the gaming machine is cut off during the execution of the variation performance and then power is turned on to the gaming machine, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor. When the variation performance resumes after the machine has entered a waiting state for customers, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor.

Fixed patching protocols waste memory resources and increase boot-up latency. In contrast, example implementations include a patch controller that receives a stream of multiple patch units from a non-volatile patch memory. The patch controller parses a descriptor patch unit, which precedes a set of patch units in the stream. From the descriptor patch unit, the patch controller extracts a ROM-patch type and a count. The type indicates whether the succeeding set of patch units includes fully associative patch units, direct-mapped patch units, or a combination. The count indicates the quantity of patch units of each type following the descriptor. Based on the extracted type and count, the patch controller processes the stream by routing the patch units to a fully associative memory or a direct-mapped memory. This streaming protocol enables flexible allocation of patch resources, reduces storage overhead in non-volatile memory, and shortens boot-up time by supporting an end-of-stream marker.

The application discloses a data reading method and device of a flash memory device, a terminal device and a computer storage medium, and comprises the following steps: receiving a read command sent by a host, wherein the read command comprises a logical address to be read of data to be read; judging whether the read command hits a first primary mapping table in a read-only memory according to the logical address to be read and a preset block address bitmap; if the first primary mapping table is not hit, finding a second logical address of a second primary mapping table located in a flash memory according to a preset secondary mapping table, and finding the data to be read corresponding to the logical address to be read according to the second primary mapping table. The application can improve the hit rate of the read command in the flash memory device and improve the reading performance of the flash memory device.

This disclosure provides a high-density memory computing device, accelerator, and apparatus with dynamically expandable folded storage. The device includes multiple computing modules, an activation value masking module, a control module, and a cache module. Read-only storage devices in the computing modules store the amplitude information of quantization weights, while random access storage devices store the sign bits. The random access storage devices in the activation value masking module store shift control information. The control module schedules the computing process through control word lines and data selection control lines. The cache module is used for data temporary storage and pipeline support. The device employs a fixed-point non-uniform stride sparse-aware quantization method to achieve high-density compressed storage of weights. It supports dynamic reconfiguration at the convolution kernel level, achieving weight reconstruction and cross-model transfer by updating the sign and shift information in the random access storage devices. Through activation masking and cache collaboration, it supports multi-precision multiply-accumulate computation and pipeline scheduling. The embodiments of this disclosure improve the high-density storage of the device and increase the area efficiency of in-memory computation, thereby reducing or even eliminating the device's access to off-chip memory.

A method of generating an IC layout diagram includes generating a plurality of logic patterns, wherein each logic pattern corresponds to a number of bits N greater than two, arranging a column of NOR-type read-only memory (ROM) bit cells as a plurality of N-bit groups separated from each other by isolation features, assigning a pattern of the plurality of logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the plurality of logic patterns in a storage device.

The present application relates to the field of servers, and discloses a device management method and system, an electronic device, and a non-volatile readable storage medium, to solve the problem of long computer startup time. The method comprises: in a computer startup process, acquiring identification information corresponding to a device; on the basis of the identification information, matching with information stored in a first preset storage space, wherein the access speed of the first preset storage space is greater than or equal to the access speed of a preset physical storage device corresponding to the device; in response to a successful match, loading option read-only memory data of the device from the first preset storage space; and in response to a failed match, loading the option read-only memory data of the device from the preset physical storage device, and writing the option read-only memory data of the device into the first preset storage space. The present application can optimize the loading process of the option read-only memory data in the startup process, reduce startup time, and improve startup efficiency of a system and user experience.

The application provides an ASIC chip firmware starting method, device and medium, relates to the technical field of ASIC chip firmware starting, and the method comprises the following steps: loading and running a first firmware from a read-only memory in the ASIC chip; performing second firmware signature verification on a second firmware; if the second firmware signature verification is passed, jumping to the second firmware execution through the first firmware; calling a hardware security module through the second firmware to perform overall signature verification on the firmware package; analyzing the firmware package through the second firmware, and writing each firmware image into a special memory area of a corresponding CPU core respectively; releasing a reset signal of other CPU cores except the first CPU core through the second firmware, so that the other CPU cores acquire and execute corresponding firmware images from the respective special memory areas; and making the first CPU core start executing the firmware image thereof. The application significantly improves the protection capability of the system in a high-security scene.

This application discloses a software function configuration method, apparatus, device, and storage medium, relating to the field of function configuration technology. The disclosed software function configuration method includes: identifying software functions based on functional status signals sent by a device, obtaining software configuration data, and storing the software configuration data in a read-only memory (ROM); reading the software configuration data from the ROM when the microcontroller unit completes initialization; updating the software configuration data in the ROM based on updated functional status signals and the software configuration data; reporting the software configuration data in the ROM to the system-on-a-chip (SoC); and completing software function configuration based on the software configuration data when the SoC powers on. This solution can improve the software universality and compatibility of intelligent cockpit systems.

This utility model discloses a 4G name tag recorder device, relating to the field of name tag technology. The 4G name tag recorder device includes a rectangular housing, with a display screen and camera mounted on the front and a pin assembly on the rear. Inside, there is a recorder, a PCB circuit board, and a battery. The PCB circuit board is electrically connected to the battery, display screen, camera, and recorder, and has a main chip, SIM card slot, RAM memory, ROM read-only memory, and a WIFI module. The main chip is connected to a power switch, WIFI button, recording button, and video recording button via the PCB circuit board. The power switch, WIFI button, recording button, and video recording button are mounted on the top of the housing. This 4G name tag recorder device integrates multiple functions such as identity display, heart rate detection, audio recording, video recording, 4G real-time transmission, WIFI connection, and trajectory recording, meeting the needs of various work scenarios and providing users with comprehensive health monitoring and work assistance functions.

The application discloses a data processing method, device, equipment, medium and product. The method is applied to an electronic device, and the method comprises the following steps: when the electronic device is started, target data stored in a read-only memory (ROM) of an optical engine is acquired, wherein the target data comprises a plurality of preset injection data, and each injection data corresponds to a value; the ROM of different optical engines comprises the plurality of preset injection data; a first injection data matched with the model of the optical engine is acquired from the plurality of injection data; the configuration parameter of the optical engine is acquired according to the value of the first injection data; the type of the configuration parameter of the optical engine is analyzed, and target processing corresponding to the type is performed. According to the embodiment of the application, the problem that the same optical engine cannot be compatible with multiple electronic device products and the compatibility is poor can be solved.

A system and method are provided that enable a processor to have the immutable code and data that it uses for its boot process to be securely patched. A system may include a read only memory (ROM) storing one or more certificates and instructions, an array of one-time programmable (OTP) indicators, a bootstrap controller connected to the ROM and the array of OTP indicators, and a random access memory (RAM) connected to the bootstrap controller. The bootstrap controller is configured to verify integrity of firmware for boot based on certificates stored in ROM, check for a patch in the array of OTP indicators, and write the one or more certificates and the instructions in ROM and the patch into the RAM. The patch may be loaded into RAM by the bootstrap controller and overwrite ROM instructions or certificates in RAM.

Methods and systems related to mask programmable memory using shared drain and gate connections are disclosed herein. A read only memory disclosed herein includes a transistor having a read terminal and a bit terminal. The read terminal and the bit terminal are a source and a drain of the transistor. The transistor also a word line coupled to a gate of the transistor, and a plurality of bit lines programmatically coupled to the bit terminal. The plurality of bit lines can be programmatically coupled by a set of mask programmable vias that couple the bit lines to the bit terminal.

This application discloses a data storage method, apparatus, vehicle, and storage medium based on vehicle faults. The method includes: when a target fault code affecting the vehicle's transmission is detected while the vehicle is in motion, acquiring frozen frame data corresponding to the target fault code; after the vehicle's engine is completely shut off, storing the frozen frame data using a read-only memory (ROM) to obtain the storage status of the frozen frame data; when the storage status indicates that the frozen frame data storage is complete, accurately determining that the ROM has stored the frozen frame data, wherein the transmission is prohibited from hibernation before the frozen frame data storage is complete, enabling the ROM to promptly complete the storage of the frozen frame data corresponding to the target fault code, avoiding the loss of frozen frame data during fault code clearing operations or power-off operations, so that subsequent vehicle fault analysis can be performed based on the frozen frame data in the ROM.