169 results about "Read-only memory" patented technology

An example computing device includes a storage device, a random-access memory, a read only memory, and a processor. The processor is to determine, during a booting process, whether an operating system being booted is a primary operating system, in response to a determination that the operating system being booted is different from the primary operating system, determine whether the operating system being booted satisfies a first criteria, and, in response to a determination that the operating system being booted fails to satisfy the first criteria, disable software persistence.

The disclosure describes a read-only memory array and a read-only memory thereof. The read-only memory array includes common-source lines, word bit lines perpendicular to the common-source lines, and sub-memory arrays. The common-source lines include a first common-source line and a second common-source line. The word bit lines include a first word bit line and a second word bit line. Each sub-memory array includes four memory cells. Each memory cell has a control terminal coupled to the corresponding word bit line and a data terminal coupled to the corresponding common-source line and the corresponding word bit line. The read-only memory includes a field-effect transistor and a capacitor formed in a semiconductor region. The field-effect transistor and the capacitor commonly include a doped well. The doped well, overlapping the common-source line, is coupled to the common-source line.

The invention provides a chip power-on initialization method and device and a chip. The method is applied to the chip. The method comprises the following steps of: after a chip is powered on and POR is finished, automatically reading back a pre-stored initialization program instruction to an address field specified by a user in a register through a one-time programmable memory or a read-only memory; the initialization program instruction is set by a user according to an actual application scene; automatically triggering an initialization program to execute based on an initialization program instruction of the write-in address field, and completing power-on initialization of the chip; and the initialization program execution is used for performing serial instruction analysis processing from an initial address after a trigger signal is detected by adopting a pipeline architecture, and stopping instruction analysis processing when an end address is recognized. According to the invention, high programmability and flexibility can be provided while high efficiency, reliability and low cost are ensured, so that diversified requirements of modern integrated circuit design are met.

The invention discloses a pharmaceutical enterprise data backup system and method and a storage device. The pharmaceutical enterprise data backup system comprises a pharmaceutical enterprise data operation system, a data classification method and a data backup storage device. The data operation system comprises a first master server PSM1, a data input device, a data classification module DCM, a first conversion module TCM1, a second server SVR2, a second conversion module TCM2, a data backup management module DBMM and a data memory DM. The data classification method comprises the following steps: S1.1, defining structured data of the pharmaceutical enterprise as a first type of data, S1.2, defining semi-structured data of the pharmaceutical enterprise as a second type of data, S1.3, defining unstructured data of the pharmaceutical enterprise as a third type of data, and S1.4, defining running log type data as a fourth type of data; the memory can be a read-only memory, a magnetic disk or an optical disk. Through the technical means, the safety problem of pharmaceutical enterprise data backup can be solved.

The invention provides a trusted startup system and a startup method of the trusted startup system, and belongs to the technical field of communication, the system comprises an on-chip ROM (Read Only Memory) located in a CPU (Central Processing Unit), a one-time programmable memory located in the CPU, a password acceleration engine located in the CPU and an FPGA (Field Programmable Gate Array) chip connected with the CPU, the system comprises an FPGA (Field Programmable Gate Array) chip, a startup firmware chip, a system file chip and a system file backup chip which are connected with the FPGA chip, an on-chip boot program stored in an on-chip ROM (Read Only Memory), a trusted password module stored on a password acceleration engine, and Feiteng basic firmware, Feiteng universal firmware and a trusted system which are stored in startup firmware, and the self-developed Linux system is stored in the system file and the system file backup. According to the method, the system and the system starting process are completely credible, including security, credibility and tamper-proofing of all files in the system starting operation process, and security starting and tamper-proofing of the system are ensured in a mode of combining software design and hardware design.

The invention relates to the technical field of computers, and discloses a program updating method on electronic equipment, equipment, a medium and a program product, a framework program of a bootstrap program is deployed on the electronic equipment, the framework program comprises a first-level unit and a second-level unit, and the second-level unit comprises a first area and a second area. The first area comprises current program information of the bootstrap program, the second area comprises backup program information of the bootstrap program, and the method comprises the following steps: executing first-level unit implementation: judging whether a bootstrap program updating condition is met or not according to description information of the current program information in the first area and description information of the backup program information in the second area; and updating the current program information in the first area through the backup program information in the second area in response to the fact that the boot program updating condition is met. According to the method and the device, the self-upgrading of the program can be realized under the condition of not depending on read-only memory hardware, and the equipment cost is reduced.

A drain programmed read-only memory includes a plurality of bit lines for each drain-programmed transistor. In addition, the drain-programmed read-only memory includes a pair of ground lines for each drain-programmed transistor. A decoder decodes a plurality of bits from each drain-programmed transistor by determining which bit line (if any) and which ground line is coupled to the drain-programmed transistor.

The invention discloses a double-patch updating method, device, equipment, medium and product of a starting read-only memory, and relates to the technical field of chip updating, the starting read-only memory is located in a server management chip, and the server management chip is provided with a one-time programmable memory isolated from the starting read-only memory. The method for burning the preset shadow patch code by the one-time programmable memory comprises the following steps of: starting the read-only memory, and detecting whether the read-only memory is successfully started within a preset time period; if the starting is not successful, triggering a shadow patch process, and executing a preset shadow patch code in the one-time programmable memory; if starting succeeds, triggering an online patch updating process based on the patch updating request, and loading a target segment patch code; and loading the target segment patch code subjected to segment security verification to a random access memory of the server management chip so as to redirect the access request to a new patch code address in the random access memory. And patch updating in the read-only memory starting process is realized.

A method includes storing, by a microcontroller, cache data of the microcontroller into a dynamic random-access memory (DRAM) in response to the microcontroller receiving a power-off command. The method includes operating, by a DRAM controller, the DRAM in a standby state in response to the microcontroller storing the cache data into the DRAM. The method includes determining, by the DRAM controller and when the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof. The method includes determining, by the DRAM controller, whether a suspend to storage condition is satisfied based on the time characteristic, the charge characteristic, or the combination thereof. The method includes storing, by the DRAM controller, the cache data of the DRAM into a read-only memory (ROM) in response to the suspend to storage condition being satisfied.

A drain programmed read-only memory includes a plurality of bit lines for each drain-programmed transistor. In addition, the drain-programmed read-only memory includes a pair of ground lines for each drain-programmed transistor. A decoder decodes a plurality of bits from each drain-programmed transistor by determining which bit line (if any) and which ground line is coupled to the drain-programmed transistor.

The invention discloses a read-only memory program correction system and method, and relates to the technical field of computers, the read-only memory program correction system comprises a program comparison module, a program correction module and an address management module; the program comparison module is used for obtaining a standard signature value and an actual signature value and comparing the standard signature value with the actual signature value to obtain a comparison result of each program segment; the program correction module is used for controlling the system on chip to obtain a correction program corresponding to the target program segment from the external storage device and storing the correction program into the target storage unit; and the address management module is used for mapping an address field of the target program segment in the read-only memory into a target address field of the correction program in the target storage unit. When the wrong target program segment is started, the wrong target program segment is directly corrected and replaced by the correction program through the mapping relation, so that segmented correction and replacement of the wrong program segment are realized, the risk that the replaced correction program is physically attacked or tampered is reduced, and the reliability and safety of the starting program are improved.

The embodiment of the invention provides a chip system, a debugging method and electronic equipment, and is applied to the technical field of chip data security design. The chip system comprises a processor and a read-only memory. The processor includes a JTAG interface and a first data interface. The read-only memory comprises a second data interface. Wherein the processor is used for performing JTAG debugging based on the JTAG interface when a data reading path between the first data interface and the second data interface is in a closed state. And when the data reading path is in the open state, keeping the JTAG interface in the closed state. According to the embodiment of the invention, the JTAG interface and the data reading path are set to be mutually exclusive, so that the risk of reading important data in the read-only memory based on JTAG access is avoided.

Enforcing attestation of read-only protected memory during attestation validity period. A client computer system identifies a change in a read-only protected memory protection status for a software component loaded at the client computer system. The client computer system then determines that a validity time period of an attestation report is unexpired. The attestation report comprises one or more attested properties, including one or more read-only memory protection (ROMP) attested properties for the software component. The client computer system also determines that at least one ROMP attested property for the software component is no longer valid due to the change in the read-only protected memory protection status for a software component. Based on the at least one ROMP attested property for the software component being no longer valid, the client computer system initiates a remedial action to prevent interaction of the software component with a relying party computer system.

Methods, systems, and devices for information broadcast techniques for stacked memory architectures are described. A semiconductor system may include multiple instances of interface circuitry of a semiconductor die that are each operable for accessing a respective set of one or more memory arrays of one or more other semiconductor dies, as well as read-only storage for storing information that is common to the multiple instances of the interface circuitry. In some implementations, such read-only storage may include one-time programmable memory elements (e.g., fuses, antifuses) that are located in at least one of the one or more other semiconductor dies, and are accessible by each of the multiple instances of interface circuitry. The read-only storage may store information that supports common aspects of interface circuitry operations such as initialization operations, evaluation operations, configuration operations, access operations, or other operations, which may be broadcast to the multiple instances of interface circuitry.

This invention provides a method for defining the encoding mode of a read-only memory (ROM) using metal wires. A substrate is provided, and a semiconductor ROM device is formed on the substrate. The top of the semiconductor device includes an interlayer dielectric layer, multiple spaced metal wires located within the interlayer dielectric layer, and a top metal layer. The continuity or disconnection of the metal wires determines the ROM's encoding mode. A photoresist layer is formed on the interlayer dielectric layer, with a thicker photoresist layer above the top metal layer and the area adjacent to the metal wires. For different products, the required encoding mode and corresponding photolithography energy are selected. Utilizing the loading effect of the photoresist layer on adjacent metals and the top metal layer, the photoresist layer on each product is opened using a photomask defining the top metal layer and the corresponding photolithography energy. The corresponding metal wires are etched according to the encoding mode of each product. This invention defines the ROM's encoding mode type by cutting the exposed metal wires, requiring only an additional metal wire etching step.

The invention provides a control method, a monitoring method, a control system and a vehicle of a system-on-chip, the method is applied to the field of vehicles, a read-only memory in the system-on-chip is provided with a target interface, and the method comprises the following steps: in response to a starting instruction of the system-on-chip, controlling the read-only memory to start, when it is detected that sampling of the read-only memory is completed, the current state of the read-only memory is synchronized to the external device through the target interface. According to the method, the external equipment can obtain the state of the system-on-chip in the starting process, so that waste of interaction time between the external equipment and the system-on-chip is reduced.

The present invention provides a password setting method and device. The method includes: when obtaining the current password to be set by a password setting object this time, searching for the historical password of the password setting object in a read-only memory (ROM); when the historical password is found in the ROM, obtaining the historical password and the identification information of the historical password, and the identification information of any historical password includes characters used to describe the setting order of any historical password among all historical passwords; based on the historical password and the identification information of the historical password, when it is determined that the ROM and the current password pass the security verification, performing password setting on the password setting object based on the current password. The password setting method and device provided by the present invention can effectively avoid the invalidation of the historical password stored in the ROM with only a small amount of computing resources consumed, improve the security of storing the historical password in the ROM, and perform password setting more securely.

A compute expression link (CXL) memory controller includes a data conversion device that receives a fail bit map and converts the fail bit map into error correction code (ECC) predecoded information in a symbol unit, a read only memory (ROM) that stores the ECC predecoded information, and an ECC engine that performs a decoding operation based on the ECC predecoded information. The ECC predecoded information includes address information indicating an address in which an error occurs, error symbol position information indicating one or more symbols in which the error occurs from among symbols corresponding to the address, and error type information indicating an error type of the one or more symbols.

Defect tracking within a computing environment includes storing a retired page table within a read only memory (ROM) of a computing node. A hardware processor of the computing node detects one or more System-on-Chips (SoCs) within the computing node. The hardware processor reads the retired page table from the read only memory. The hardware processor compares records of the retired page table with the one or more SoCs within the computing node. For each record of the retired page table that matches the one or more SoCs within the computing node, one or more physical pages of a volatile memory of the one or more SoCs are retired based on each record.

The invention relates to fast, low area self-testing of read only memory. A method for performing a fast read only memory (ROM) test is disclosed. In a first method, a signature is generated by performing a first set of N read operations with an extended read cycle and a subsequent second set of N read operations with a full-speed read cycle, where N is an integer greater than or equal to 2. The retrieved data is combined using a modulo addition operation and a modulo subtraction operation and stored in a signature register. In a second method, the signature is generated by performing two read operations with an extended read cycle, followed by two read operations with a full-speed read cycle. The retrieved data is combined using a rejection OR (XOR) operation and stored in a signature register. The final signature is compared to a predetermined value to determine if any error is detected. Both methods provide robust testing that can detect various ROM errors while minimizing test time and complexity.

Methods for performing a fast read-only memory (ROM) test are disclosed. In the first method, a signature is generated by performing a first set of N read operations utilizing an extended read-cycle, followed by a second set of N read operations utilizing an at-speed read-cycle, where N is an integer greater than or equal to 2. The retrieved data is combined using modulo addition and subtraction operations and stored in a signature register. In the second, a signature is generated by performing two read operations utilizing an extended read-cycle, followed by two read operations utilizing an at-speed read-cycle. The retrieved data is combined using exclusive OR (XOR) operations and stored in a signature register. The final signature is compared to a predetermined value to determine if any errors were detected. Both methods provide a robust test capable of detecting various ROM errors while minimizing test time and complexity.

The invention provides a method for generating a configuration interface. The method for generating the configuration interface comprises the following steps of: loading a UEFI Option ROM (Read Only Memory) driver of external equipment through a UEFI of main equipment, wherein the UEFI Option ROM driver is generated according to the UEFI driver and a configuration interface file; and dynamically analyzing a configuration interface file in the UEFI Option ROM driver through a file analyzer in the UEFI Option ROM driver, and creating a configuration interface option of a UEFI setting interface of the main equipment according to an analysis result. According to the configuration interface generation method provided by the invention, a user can flexibly configure and manage the configuration interface of the external equipment.

The invention discloses an ROM storage method and system and a storage medium, and belongs to the technical field of solid state disks. The method comprises the steps that ROM firmware is loaded from an ROM assembly, and the ROM firmware issues an eFlash controller assembly read ROM patch area command; the eFlash controller component writes read-out ROM patch data into an on-chip storage designated area, ROM firmware reads the position of an ROM frame header stored on a chip, the read-out ROM frame header is all 1 at the moment, and the ROM firmware judges that no ROM patch exists; the CPU component issues a programming command to the eFlash controller component and initiates a request for writing the ROM patch into the eFlash component, and the eFlash controller component writes the ROM patch into the eFlash component; and the eFash controller component returns a programming command execution result to the CPU component, the CPU component verifies the programming command execution result, and the ROM patch update is completed if the verification is passed. According to the invention, the eFlash is adopted to store and load the ROM patch data, so that the required ROM capacity is greatly reduced, the chip area is saved, and the potential high ROM ECO cost is saved.

A read-only memory (ROM) receives an instruction address from a requestor and provides a fetched instruction from the instruction address. A ROM patcher includes storage circuitry to store a bank of entries, each entry having a corresponding bank address and is configurable as either a patch address entry or a patch replacement entry. A first entry of the bank is configured as a first patch address entry storing address information indicating a first range of ROM addresses for a first patch of instructions. A plurality of entries of the bank following the first entry are configured as a plurality of patch replacement entries, each storing a replacement instruction of the first patch. Control circuitry determines if the instruction address hits in the bank, and when it does, the replacement instruction from one of the plurality of patch replacement entries is returned to the requestor in place of the fetched instruction.

A memory device is provided. The memory device includes a plurality of read only memory (ROM) cells formed in a device layer. Each of the ROM cells includes a gate structure of a transistor coupled to a word line on a front side of the device layer, a first source / drain feature of the transistor coupled to a bit line, and a second source / drain feature of the transistor. The ROM cells include a plurality of first cells corresponding to a first logic value and a plurality of second cells corresponding to a second logic value complementary to the first logic value. In the first cell, the second source / drain feature of the transistor is coupled to a VSS line extending along the same orientation as the bit line. The device layer is formed between the bit line and the VSS line.

The invention provides a method and a process for loading a program in an ROM (Read Only Memory) of an NVM (Non-Volatile Memory) solid-state disk, which belong to the technical field of program loading and comprise the following steps of: step 1, actively searching NOR FLASH and NAND FLASH; 2, automatic screening is carried out, an optimal convenient path is automatically screened, and an optimal loading mode is selected; the method comprises the following steps: firstly, in active search, firstly searching from NOR Flash, searching NAND FLASH when the NOR Flash cannot be searched, and selecting whether to search the NOR Flash firstly or the NAND FLASH firstly according to configuration in efuse; in the step 1, in active search, a plurality of boot points are divided into 16 segments, and each segment only contains 8 nand flash boot points. According to the method, the system program can be efficiently and stably loaded and operated by actively searching the NOR FLASH and the NAND FLASH, automatically screening the optimal convenient path and selecting the optimal loading mode; and in cooperation with a security verification mechanism, the correctness and accuracy of the data in the loading process are ensured.

A method for programming an integrated circuit comprising one or more microprocessors, at least one random-access memory, at least one read-only memory and at least one non-volatile rewritable memory, at least one high-speed bus and one bus, and functional components, wherein a step of recording, in the non-volatile rewritable memory, a set of executable computer codes is carried out, the method comprising booting steps according to an execution mode or according to a programming mode comprising: ⋅an original step of recording, in a non-erasable mass memory of the integrated circuit during the manufacture of the integrated circuit: ⋅a set of static resources comprising the digital development tools forming an assisted development environment executable by a browser and the technical documentation relating to the programming of the integrated circuit; ⋅and a boot code according to a programming mode; ⋅wherein the booting step according to the programming mode consists in controlling: ⋅querying the state of the hardware and software dynamic resources of the integrated circuit and a step of recording, in a local rewritable memory, the state for each of the hardware and software resources; ⋅activating the transfer of the static resources and the dynamic resources to a connected external computer device.

A read-only memory (ROM) device comprises an active region extending along a first direction and a plurality of gates extending above and across the active region along a second direction perpendicular to the first. The plurality of gates, together with the active region, constitute a plurality of transistors. Each of the plurality of transistors is configured to store a data element. The active region extends continuously beneath and across more than four conductive gates of the plurality of gates.

A memory device includes a first portion of a memory array comprising a plurality of first read only memory (ROM) cells, each of the plurality of first ROM cells comprising a first transistor that has a first conductive type and electrically coupled to a first word line and a first bit line. The memory device includes a second portion of the memory array comprising a plurality of second ROM cells, each of the plurality of second ROM cells comprising a second transistor that has a second conductive type and electrically coupled to a second word line and a second bit line. The first word line and second word line extend along a first lateral direction, and the first bit line and second bit line extend along a second lateral direction perpendicular to the first lateral direction.