224 results about "Read-only memory" patented technology

The program updating method comprises the steps of obtaining an upgrade package of a target program; analyzing the upgrade package in the RAM to obtain a matched field, a non-matched field and a non-matched data stream; determining a source data block to which a character string associated with a matching field belongs according to the sequence of the matching field and the non-matching field in the matching sequence under the condition that the current field needing to be operated is the matching field, and reading the source data block into an RAM (Random Access Memory); reading a target character string associated with a non-matching field from the non-matching data stream under the condition that the field needing to be operated currently is the non-matching field; and generating an intermediate file of the first program file in the RAM based on the source data block and / or the target character string in the RAM, and writing the intermediate file into a read-only memory (ROM). When a target program is upgraded, new and old files are split into data blocks, only the data blocks of to-be-read and to-be-written data are loaded into an RAM (Random Access Memory), and only a limited number of data blocks are reserved in the RAM, so that the use of the RAM is kept at a small level.

The invention discloses an online upgrading method and device based on ZYNQ, relates to the technical field of ZYNQ online upgrading, and solves the problems that in the prior art, after ZYNQ firmware upgrading fails, equipment crashes, and ZYNQ firmware loading logic is unreasonable. The method comprises the steps that ZYNQ firmware is designed into three parts, all the firmware achieve different functions, and all the firmware achieve different functions; the method comprises the following steps that: a ZYNQ firmware is divided into boot firmware, application program firmware and backup program firmware which are respectively stored in an ROM (Read Only Memory), after the ZYNQ is powered on, the firmware is searched and verified from an initial address of the ROM, the ZYNQ firmware is operated after the verification is passed, the normal operation of a program is realized by loading the backup program firmware after the application program firmware fails to be loaded, and when the firmware is upgraded, the application program firmware can be updated by loading the backup program firmware. According to the method, only the running program firmware is subjected to coverage upgrading so as to ensure that the other program firmware is not damaged, and by using a multiple loading method, it can be ensured that in online upgrading, no matter whether the upgraded application firmware is damaged or not, loading can be carried out by skipping to the position of the correct firmware.

An example computing device includes a storage device, a random-access memory, a read only memory, and a processor. The processor is to determine, during a booting process, whether an operating system being booted is a primary operating system, in response to a determination that the operating system being booted is different from the primary operating system, determine whether the operating system being booted satisfies a first criteria, and, in response to a determination that the operating system being booted fails to satisfy the first criteria, disable software persistence.

The disclosure describes a read-only memory array and a read-only memory thereof. The read-only memory array includes common-source lines, word bit lines perpendicular to the common-source lines, and sub-memory arrays. The common-source lines include a first common-source line and a second common-source line. The word bit lines include a first word bit line and a second word bit line. Each sub-memory array includes four memory cells. Each memory cell has a control terminal coupled to the corresponding word bit line and a data terminal coupled to the corresponding common-source line and the corresponding word bit line. The read-only memory includes a field-effect transistor and a capacitor formed in a semiconductor region. The field-effect transistor and the capacitor commonly include a doped well. The doped well, overlapping the common-source line, is coupled to the common-source line.

The invention provides a chip power-on initialization method and device and a chip. The method is applied to the chip. The method comprises the following steps of: after a chip is powered on and POR is finished, automatically reading back a pre-stored initialization program instruction to an address field specified by a user in a register through a one-time programmable memory or a read-only memory; the initialization program instruction is set by a user according to an actual application scene; automatically triggering an initialization program to execute based on an initialization program instruction of the write-in address field, and completing power-on initialization of the chip; and the initialization program execution is used for performing serial instruction analysis processing from an initial address after a trigger signal is detected by adopting a pipeline architecture, and stopping instruction analysis processing when an end address is recognized. According to the invention, high programmability and flexibility can be provided while high efficiency, reliability and low cost are ensured, so that diversified requirements of modern integrated circuit design are met.

The invention discloses a pharmaceutical enterprise data backup system and method and a storage device. The pharmaceutical enterprise data backup system comprises a pharmaceutical enterprise data operation system, a data classification method and a data backup storage device. The data operation system comprises a first master server PSM1, a data input device, a data classification module DCM, a first conversion module TCM1, a second server SVR2, a second conversion module TCM2, a data backup management module DBMM and a data memory DM. The data classification method comprises the following steps: S1.1, defining structured data of the pharmaceutical enterprise as a first type of data, S1.2, defining semi-structured data of the pharmaceutical enterprise as a second type of data, S1.3, defining unstructured data of the pharmaceutical enterprise as a third type of data, and S1.4, defining running log type data as a fourth type of data; the memory can be a read-only memory, a magnetic disk or an optical disk. Through the technical means, the safety problem of pharmaceutical enterprise data backup can be solved.

The invention provides a trusted startup system and a startup method of the trusted startup system, and belongs to the technical field of communication, the system comprises an on-chip ROM (Read Only Memory) located in a CPU (Central Processing Unit), a one-time programmable memory located in the CPU, a password acceleration engine located in the CPU and an FPGA (Field Programmable Gate Array) chip connected with the CPU, the system comprises an FPGA (Field Programmable Gate Array) chip, a startup firmware chip, a system file chip and a system file backup chip which are connected with the FPGA chip, an on-chip boot program stored in an on-chip ROM (Read Only Memory), a trusted password module stored on a password acceleration engine, and Feiteng basic firmware, Feiteng universal firmware and a trusted system which are stored in startup firmware, and the self-developed Linux system is stored in the system file and the system file backup. According to the method, the system and the system starting process are completely credible, including security, credibility and tamper-proofing of all files in the system starting operation process, and security starting and tamper-proofing of the system are ensured in a mode of combining software design and hardware design.

The invention relates to the technical field of computers, and discloses a program updating method on electronic equipment, equipment, a medium and a program product, a framework program of a bootstrap program is deployed on the electronic equipment, the framework program comprises a first-level unit and a second-level unit, and the second-level unit comprises a first area and a second area. The first area comprises current program information of the bootstrap program, the second area comprises backup program information of the bootstrap program, and the method comprises the following steps: executing first-level unit implementation: judging whether a bootstrap program updating condition is met or not according to description information of the current program information in the first area and description information of the backup program information in the second area; and updating the current program information in the first area through the backup program information in the second area in response to the fact that the boot program updating condition is met. According to the method and the device, the self-upgrading of the program can be realized under the condition of not depending on read-only memory hardware, and the equipment cost is reduced.

The invention discloses a self-adaptive adjustment method and device of a server, a product, a medium and the server. The method and the device relate to the field of server security and are used for solving the server operation problem caused by environment difference at present. When the server is started, the environment parameters of the server are obtained and stored in the non-tampering read-only memory in the basic management controller, the type of the environment where the server is located is recognized according to the environment parameters, then the most suitable adjusting strategy is determined, and then the rotating speed of the fan and / or the deflection angle of the air blocking piece are adjusted according to the determined adjusting strategy. And adjusting a heat dissipation system of the server. It can be seen that the adjustment strategy is determined in a self-adaptive mode according to the environment parameters, the adjustment requirements of the server cooling system in different environments can be met, complex and changeable environment conditions can be responded more comprehensively and accurately, the server fault risk caused by environment differences is reduced, and the reliability and stability of the server are improved.

A drain programmed read-only memory includes a plurality of bit lines for each drain-programmed transistor. In addition, the drain-programmed read-only memory includes a pair of ground lines for each drain-programmed transistor. A decoder decodes a plurality of bits from each drain-programmed transistor by determining which bit line (if any) and which ground line is coupled to the drain-programmed transistor.

The invention provides a microprocessing system and a program execution method, the microprocessing system comprises a microprocessor, an external random access memory and a read-only memory, and the address range of the external random access memory is overlapped with the address range of the read-only memory; wherein the microprocessor, the external random access memory and the read-only memory are connected to three groups of buses, and the three groups of buses are a control bus, an address bus and a data bus; the data bus and the address bus are respectively provided with a path switching circuit, and the path switching circuits are used for switching a program in the read-only memory to the external random access memory for execution by switching a program access path of the microprocessor. According to the technical scheme, the program reading and executing speed of the microprocessor can be improved.

The invention discloses a double-patch updating method, device, equipment, medium and product of a starting read-only memory, and relates to the technical field of chip updating, the starting read-only memory is located in a server management chip, and the server management chip is provided with a one-time programmable memory isolated from the starting read-only memory. The method for burning the preset shadow patch code by the one-time programmable memory comprises the following steps of: starting the read-only memory, and detecting whether the read-only memory is successfully started within a preset time period; if the starting is not successful, triggering a shadow patch process, and executing a preset shadow patch code in the one-time programmable memory; if starting succeeds, triggering an online patch updating process based on the patch updating request, and loading a target segment patch code; and loading the target segment patch code subjected to segment security verification to a random access memory of the server management chip so as to redirect the access request to a new patch code address in the random access memory. And patch updating in the read-only memory starting process is realized.

A method includes storing, by a microcontroller, cache data of the microcontroller into a dynamic random-access memory (DRAM) in response to the microcontroller receiving a power-off command. The method includes operating, by a DRAM controller, the DRAM in a standby state in response to the microcontroller storing the cache data into the DRAM. The method includes determining, by the DRAM controller and when the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof. The method includes determining, by the DRAM controller, whether a suspend to storage condition is satisfied based on the time characteristic, the charge characteristic, or the combination thereof. The method includes storing, by the DRAM controller, the cache data of the DRAM into a read-only memory (ROM) in response to the suspend to storage condition being satisfied.

A drain programmed read-only memory includes a plurality of bit lines for each drain-programmed transistor. In addition, the drain-programmed read-only memory includes a pair of ground lines for each drain-programmed transistor. A decoder decodes a plurality of bits from each drain-programmed transistor by determining which bit line (if any) and which ground line is coupled to the drain-programmed transistor.

The invention discloses a read-only memory program correction system and method, and relates to the technical field of computers, the read-only memory program correction system comprises a program comparison module, a program correction module and an address management module; the program comparison module is used for obtaining a standard signature value and an actual signature value and comparing the standard signature value with the actual signature value to obtain a comparison result of each program segment; the program correction module is used for controlling the system on chip to obtain a correction program corresponding to the target program segment from the external storage device and storing the correction program into the target storage unit; and the address management module is used for mapping an address field of the target program segment in the read-only memory into a target address field of the correction program in the target storage unit. When the wrong target program segment is started, the wrong target program segment is directly corrected and replaced by the correction program through the mapping relation, so that segmented correction and replacement of the wrong program segment are realized, the risk that the replaced correction program is physically attacked or tampered is reduced, and the reliability and safety of the starting program are improved.

The invention provides an MCU controller. The MCU controller comprises a kernel, a read-only memory, a read-write memory, a register, a flash memory controller and a flash memory, the read-only memory and the read-write memory store different data types and different mapping addresses; the kernel is respectively connected with the read-only memory, the read-write memory and the register through a plurality of buses, and the plurality of buses are separated and parallel; the flash memory controller is connected with the read-only memory and the read-write memory, and the flash memory controller is switched between the bus master device and the bus slave device; when the flash memory controller is switched to the bus master device, the flash memory controller transmits the data to be transmitted from the flash memory to the read-write memory; when the flash memory controller is switched to a bus slave device, the kernel performs read-write operation on the register; parallel access of instructions, data and external data is achieved through separated bus interfaces, and the system efficiency is improved; the dynamic master-slave switching of the flash memory controller optimizes the starting efficiency and the flexibility during operation.

The invention provides a method for defining an encoding mode of a read-only memory by using metal wires, which comprises the following steps: providing a substrate, forming a semiconductor device of the read-only memory on the substrate, the top end of the semiconductor device comprising an interlayer dielectric layer, a plurality of metal wires distributed at intervals in the interlayer dielectric layer, and a top end metal layer, the disconnection and connection conditions of the metal wires are used for determining the coding mode of the read-only memory; forming a photoresist layer on the interlayer dielectric layer, wherein the photoresist layer above the top metal layer and the metal wire close area is thicker; selecting a required coding mode and corresponding photoetching energy for different products, and opening the photoresist layer on each product by utilizing adjacent metal, the load effect of the photoresist layer on the top metal layer, the photomask defining the top metal layer and the corresponding photoetching energy; and etching the corresponding metal wires according to the coding mode of each product. According to the method, the exposed metal wire is cut off to define the coding mode type of the read-only memory, and only one additional metal wire etching step is needed in the process.

The invention discloses a basic input and output system flashing method and device and a medium, relates to the technical field of servers, is used for realizing BIOS firmware flashing, and provides the basic input and output system flashing method aiming at the problem of low efficiency caused by adopting whole block flashing when a BIOS ROM (Read Only Memory) is flashed at present. In the compiling process of the BIOS mirror image file, corresponding module version information is added for each program module. And determining a program module with version update in the BIOS mirror image file according to the module version information to serve as a target program module needing to be flashed this time. On the basis, when the BIOS ROM is formally flashed and written, only part of program modules with version updating can be updated into the BIOS ROM. And therefore, the time required for brushing the BIOS ROM is shortened, and the brushing efficiency is greatly improved. And particularly, the method can show more obvious advantages in a scene with small BIOS firmware updating change.

The embodiment of the invention provides a chip system, a debugging method and electronic equipment, and is applied to the technical field of chip data security design. The chip system comprises a processor and a read-only memory. The processor includes a JTAG interface and a first data interface. The read-only memory comprises a second data interface. Wherein the processor is used for performing JTAG debugging based on the JTAG interface when a data reading path between the first data interface and the second data interface is in a closed state. And when the data reading path is in the open state, keeping the JTAG interface in the closed state. According to the embodiment of the invention, the JTAG interface and the data reading path are set to be mutually exclusive, so that the risk of reading important data in the read-only memory based on JTAG access is avoided.

The invention provides a high-speed read-only memory array with high write-in times, which belongs to the field of memory arrays and comprises a plurality of word lines, a plurality of selection lines, a plurality of bit lines and a plurality of sub-memory arrays. The word lines comprise a first word line, the selection lines comprise a first selection line and a second selection line, and the bit lines comprise a first bit line, a second bit line, a third bit line and a fourth bit line. Each sub-memory array comprises a first memory unit cell, a second memory unit cell, a third memory unit cell and a fourth memory unit cell. The first memory unit cell is coupled to the first word line, the first bit line and the first selection line, the second memory unit cell is coupled to the first word line, the second bit line and the first selection line, the third memory unit cell is coupled to the first word line, the third bit line and the second selection line, and the fourth memory unit cell is coupled to the first word line, the fourth bit line and the second selection line. According to the invention, the purposes of high-speed writing and high writing times can be achieved by using lower voltage.

Methods and systems which involve computer memories are disclosed herein. A disclosed multibit read only memory (ROM) includes a plurality of voltage generators for generating a plurality of voltages and a transistor having a first node and a second node. The transistor can be a field effect transistor (FET) and the first node can be a gate node and the second node can be a source or drain node. The ROM includes a connection from the first node to a first supply voltage node which is biased by one of the voltages in the plurality of voltages. The ROM includes a connection from the second node to a second supply voltage node which is biased by one of the voltages in the plurality of voltages. The value of a multibit ROM cell in the multibit ROM is stored as a resulting conductivity state of the transistor.

Enforcing attestation of read-only protected memory during attestation validity period. A client computer system identifies a change in a read-only protected memory protection status for a software component loaded at the client computer system. The client computer system then determines that a validity time period of an attestation report is unexpired. The attestation report comprises one or more attested properties, including one or more read-only memory protection (ROMP) attested properties for the software component. The client computer system also determines that at least one ROMP attested property for the software component is no longer valid due to the change in the read-only protected memory protection status for a software component. Based on the at least one ROMP attested property for the software component being no longer valid, the client computer system initiates a remedial action to prevent interaction of the software component with a relying party computer system.

Methods, systems, and devices for information broadcast techniques for stacked memory architectures are described. A semiconductor system may include multiple instances of interface circuitry of a semiconductor die that are each operable for accessing a respective set of one or more memory arrays of one or more other semiconductor dies, as well as read-only storage for storing information that is common to the multiple instances of the interface circuitry. In some implementations, such read-only storage may include one-time programmable memory elements (e.g., fuses, antifuses) that are located in at least one of the one or more other semiconductor dies, and are accessible by each of the multiple instances of interface circuitry. The read-only storage may store information that supports common aspects of interface circuitry operations such as initialization operations, evaluation operations, configuration operations, access operations, or other operations, which may be broadcast to the multiple instances of interface circuitry.

The present invention provides an accelerator chip for a large model algorithm, and relates to the technical field of artificial intelligence chips. The accelerator chip includes: a matrix-vector multiplication unit and a vector unit; the matrix-vector multiplication unit is used for matrix-vector multiplication operations, data storage and transmission of the large model algorithm; the vector unit is used for vector operations, data storage and control of the large model algorithm; wherein the matrix-vector multiplication unit includes a read-only memory and a static random access memory; the read-only memory is used to store base model parameters, and the base model parameters are used to calculate base model matrix vectors; the static random access memory is used to store fine-tuning parameters, and the fine-tuning parameters are used to calculate the fine-tuning matrix. The present invention can break the storage bandwidth limitation at a relatively low cost.

This invention provides a method for defining the encoding mode of a read-only memory (ROM) using metal wires. A substrate is provided, and a semiconductor ROM device is formed on the substrate. The top of the semiconductor device includes an interlayer dielectric layer, multiple spaced metal wires located within the interlayer dielectric layer, and a top metal layer. The continuity or disconnection of the metal wires determines the ROM's encoding mode. A photoresist layer is formed on the interlayer dielectric layer, with a thicker photoresist layer above the top metal layer and the area adjacent to the metal wires. For different products, the required encoding mode and corresponding photolithography energy are selected. Utilizing the loading effect of the photoresist layer on adjacent metals and the top metal layer, the photoresist layer on each product is opened using a photomask defining the top metal layer and the corresponding photolithography energy. The corresponding metal wires are etched according to the encoding mode of each product. This invention defines the ROM's encoding mode type by cutting the exposed metal wires, requiring only an additional metal wire etching step.

The invention provides a control method, a monitoring method, a control system and a vehicle of a system-on-chip, the method is applied to the field of vehicles, a read-only memory in the system-on-chip is provided with a target interface, and the method comprises the following steps: in response to a starting instruction of the system-on-chip, controlling the read-only memory to start, when it is detected that sampling of the read-only memory is completed, the current state of the read-only memory is synchronized to the external device through the target interface. According to the method, the external equipment can obtain the state of the system-on-chip in the starting process, so that waste of interaction time between the external equipment and the system-on-chip is reduced.

The present invention provides a password setting method and device. The method includes: when obtaining the current password to be set by a password setting object this time, searching for the historical password of the password setting object in a read-only memory (ROM); when the historical password is found in the ROM, obtaining the historical password and the identification information of the historical password, and the identification information of any historical password includes characters used to describe the setting order of any historical password among all historical passwords; based on the historical password and the identification information of the historical password, when it is determined that the ROM and the current password pass the security verification, performing password setting on the password setting object based on the current password. The password setting method and device provided by the present invention can effectively avoid the invalidation of the historical password stored in the ROM with only a small amount of computing resources consumed, improve the security of storing the historical password in the ROM, and perform password setting more securely.

A compute expression link (CXL) memory controller includes a data conversion device that receives a fail bit map and converts the fail bit map into error correction code (ECC) predecoded information in a symbol unit, a read only memory (ROM) that stores the ECC predecoded information, and an ECC engine that performs a decoding operation based on the ECC predecoded information. The ECC predecoded information includes address information indicating an address in which an error occurs, error symbol position information indicating one or more symbols in which the error occurs from among symbols corresponding to the address, and error type information indicating an error type of the one or more symbols.

Defect tracking within a computing environment includes storing a retired page table within a read only memory (ROM) of a computing node. A hardware processor of the computing node detects one or more System-on-Chips (SoCs) within the computing node. The hardware processor reads the retired page table from the read only memory. The hardware processor compares records of the retired page table with the one or more SoCs within the computing node. For each record of the retired page table that matches the one or more SoCs within the computing node, one or more physical pages of a volatile memory of the one or more SoCs are retired based on each record.