42 results about "Programmable read-only memory" patented technology

The utility model relates to the technical field of medical instruments, and provides a surgical instrument for steam ablation and a steam ablation device. The utility model provides a surgical instrument for steam ablation. The surgical instrument comprises an electrically erasable programmable read-only memory and a high-temperature-resistant protective structure, and the high-temperature-resistant protection structure covers the electrically erasable programmable read-only memory. During specific implementation, a high-temperature-resistant protection structure is specially designed for the surgical instrument and is used for protecting a key component, namely an electrically erasable programmable read-only memory, in the surgical instrument. The high-temperature-resistant protection structure can effectively solve the problem that the digital chip is easy to damage in the processing process due to the fact that the digital chip is not resistant to high temperature in the prior art.

The invention provides an erasable programmable read-only memory and a programming method. The erasable programmable read-only memory comprises a P-type well region and an N-type well region which are located in a substrate and arranged adjacently; the first gate oxide layer and the gate are located on the surface of the P-type well region; the second gate oxide layer and the floating gate are located on the surface of the N-type well region; the first N-type impurity region, the second N-type impurity region and the first P-type impurity region are located in the P-type well region and arranged at intervals, the first N-type impurity region and the second N-type impurity region are located on the two sides of the grid electrode, and the first N-type impurity region and the second N-type impurity region serve as the source end and the drain end of the NMOS respectively; the third N-type impurity region, the fourth N-type impurity region, the second P-type impurity region and the third P-type impurity region are located in the N-type well region and arranged at intervals, and the second P-type impurity region and the third P-type impurity region are located on the two sides of the floating gate and serve as the source end and the drain end of a PMOS respectively; wherein the second N-type impurity region is communicated with the second P-type impurity region.

Method and apparatus for trimming IC components. In an embodiment, a circuit includes a digital controller, a first programmable read only memory coupled to the controller, and a trimmable block having at least one trimmable component. A second programmable read only memory is coupled to the trimmable block, where the second programmable read only memory is independent of the first programmable read only memory.

An apparatus includes an N-type bit-cell bundle with a first N-type bit-cell array, a first merge circuit, and a second N-type bit-cell array coupled to the first N-type bit-cell array via the first merge circuit. The apparatus includes a P-type bit-cell bundle coupled in a horizontal direction to the N-type bit-cell bundle via a spacer area. The P-type bit-cell bundle includes a first P-type bit-cell array, a second merge circuit, and a second P-type bit-cell array. The second P-type bit-cell array is coupled to the first P-type bit-cell array via the second merge circuit.

The invention discloses a log storage method based on a vehicle machine MCU and related equipment, and relates to the technical field of data processing, and the method comprises the steps: responding to a log storage instruction, obtaining multi-source log data, based on a preset heartbeat mechanism, checking the working state of an SOC, the heartbeat mechanism is constructed based on the SOC and the MCU, and if the working state is normal, the multi-source log data is stored in the multi-source log data, and if the working state is normal, the multi-source log data is stored in the multi-source log data; sending the multi-source log data to the SOC, so that the SOC executes a data storage operation; and if the working state is abnormal, storing the multi-source log data in an EEP space of the MCU. Based on the characteristics of high capacity of the SOC and good stability of the MCU, the data is preferentially stored in the SOC, and further, by combining with a heartbeat mechanism, when the SOC works abnormally or is unstable, the storage path is dynamically adjusted, so that all log data can be completely and stably stored.

A magnetoresistive memory may include a plurality of magnetoresistive memory devices, wherein each magnetoresistive device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed between the fixed and free magnetic regions. The magnetoresistive memory may include a spin-orbit-torque (SOT) channel, wherein the SOT channel is in contact with the free magnetic regions of the plurality of magnetoresistive memory devices. The magnetoresistive memory may include a write circuit configured to apply a write current through at least one magnetoresistive memory device of the plurality of magnetoresistive memory devices and the SOT channel, wherein the write current is configured to generate a short in at least one magnetoresistive memory device as a one-time programmable read-only memory (ROM) function.

Apparatuses and techniques are described herein that provide virtual slots for firmware mirroring. An apparatus comprising: a controller configured to perform firmware mirroring; the erasable programmable read-only memory is used for storing a firmware mirror image; and a memory containing instructions that, when executed by the controller, cause the controller to: store a temporary firmware image in a firmware memory, the temporary firmware image to be used in place of a current firmware image; receiving a parameter to control the use of the temporary firmware image, the parameter defining a condition; storing the parameters in a local memory; activating the temporary firmware mirror image in the virtual firmware slot; and using the temporary firmware image until the condition is satisfied, and then resuming to the current firmware image.

According to some embodiments, a system includes a wireless test module (WTM) side hot-swap connector located between a chassis of a first WTM and a variable front end of the first WTM. The variable front end of the first WTM may mate to an aircraft connector. The WTM side hot-swap connector may mate to a front end side hot-swap connector of the variable front end of the first WTM. The WTM side hot-swap connector includes a female connector, an alignment peg configured to couple to the variable front end of the first WTM, a slip ring configured to secure the first WTM in place, and an electrically erasable programmable read-only memory (EEPROM) read / write wire integrated on a circuit board operable to read / write data of the aircraft connector.

A microwave ablation probe includes a handle configured to operably couple a supply cable to a needle and a printed circuit board assembly (PCBA) positioned in the handle. The PCBA includes an analog to digital converter and an electrically erasable programmable read-only memory (EEPROM) device.

Apparatus and techniques for providing hardware protected system measurements are described herein. A system includes a memory device accessible by a first device and a host device, where the first device is configured for use with the host device; processing circuitry coupled to the memory device; and a programmable read only memory coupled to the memory device, the programmable read only memory including instructions to: initialize the first device; verifying firmware to be executed on the first device; obtaining a measurement value of the firmware; storing the measurement value in the memory device; and initiating execution of the firmware.

A computer may store records at respective locations in the memory. The records may respectively include, for one of a plurality of variables, an identifier and a size. Responsive to a notification of a software update, the computer may retrieve from the memory a first map of the variables specifying their respective locations in the memory and respective sizes for each of the variables along with the identifiers. The computer may receive, from a remote device, a second map of the variables specifying respective second locations in the memory, and second sizes, for the respective variables along with the identifiers. The computer may store the variables to the respective second locations in memory and store the second map in place of the first map.

An electrically erasable programmable read only memory (EEPROM) cell includes a first gate, a second gate and an erasing gate. The first gate and the second gate are disposed on a substrate, wherein the first gate includes a first floating gate and a first control gate stacked from bottom to top, and the second gate includes a second floating gate and a second control gate stacked from bottom to top. The erasing gate is sandwiched by the first gate and the second gate, wherein a side part of the first floating gate and a side part of the second floating gate right below the erasing gate both have multiple tips. The present invention also provides a method of forming the electrically erasable programmable read only memory (EEPROM) cell.

One example includes an integrated circuit (100) having a sense amplifier (105) including: a first inverter (110) having a first positive power supply terminal, a first input, and a first output; and a second inverter (115) having a second positive power supply terminal, a second input connected to the first output, and a second output connected to the first input. The integrated circuit also includes a reference resistor (Rref) connected between a positive voltage rail (VDD) and the second positive power supply terminal. A fuse (120) is connected between the positive voltage rail and the first positive power supply terminal.

Hot carrier injection (HCI) may be used to provide various improvements for one-time programmable (OTP) read-only memory (ROM) or physical unclonable function (PUF) circuits. HCI may be used to write a memory bit (e.g., logical 0 or 1), which may be used in OTP ROM. HCI may be used to provide improved programmable ROM (PROM) memory devices, such as to facilitate programming or to increase sensing window. HCI may also be used to write a memory bit in a PUF circuit. HCI may provide a cross-foundry portable PUF circuit that has an associated adjustable bit error rate (BER), which may be used to secure root key generation, or may be used to provide a unique identification (ID) for fuse replacement.

Devices and techniques that provide a virtual slot for firmware images are described herein. A device includes a controller configured to execute a firmware image; erasable programmable read-only memory to store firmware images; and memory including instructions, which when executed by the controller, cause the controller to: store a temporary firmware image into a firmware memory, the temporary firmware image to be used in place of a current firmware image; receive a parameter to control the use of the temporary firmware image, the parameter defining a condition; store the parameter in the local memory; activate the temporary firmware image in the virtual firmware slot; and use the temporary firmware image until the condition is satisfied, and then revert to the current firmware image.

A mask-programmable read only memory (ROM) is provided. The mask ROM includes first and second unit cells; an isolation gate electrode that isolates the first unit cell and the second unit cell; and a bit line that crosses the first and second unit cells. The first unit cell includes: a first source contact and a first bit line contact which are disposed on a semiconductor substrate; and a first gate electrode disposed between the first source contact and the first bit line contact. The second unit cell includes: a second source contact and a second bit line contact which are disposed on the semiconductor substrate; a second gate electrode disposed between the second source contact and the second bit line contact; and a via structure electrically connected to the second bit line contact. The bit line is connected to the via structure of the second unit cell.

An electrically erasable programmable read only memory (EEPROM) includes a substrate, isolation structures, a row of erase gate and a row of floating gates. The isolation structures are defined in the substrate to extend in a first direction. The row of erase gate having a wave shape is disposed across the substrate. The row of floating gates having staggered islands is disposed parallel to the row of erase gate. A method of forming said electrically erasable programmable read only memory (EEPROM) is also provided.

The invention relates to the technical field of spaceflight electronic systems, and discloses a program guiding method and system capable of realizing on-orbit reconstruction of a running space, and the method comprises the steps: storing a guiding program in each of a PROM (programmable read-only memory) and a software-programmable nonvolatile memory of a spaceborne computer system; the method comprises the following steps of: after a system is reset, running a bootstrap function code of a bootstrap program in a programmable read-only memory (PROM), selecting a corresponding bootstrap program according to a system state register to load and run, and loading an application program by the bootstrap program to run; the states of random access memories (RAM) operated by a boot program and an application program are respectively monitored, system state register bit switching is performed through a ground instruction to realize fault isolation, program operation space redundancy and fault isolation are realized, the boot program can still be normally operated after a part of RAM devices fail, and the reliability of the boot program is improved. The on-orbit fault diagnosis and reconstruction repair functions of the system are implemented, and the reliability and safety of long-term on-orbit operation of the system are improved.

The invention provides a self-adaptive control method, medium and system for a wide-range electric energy meter, and the method comprises the steps: obtaining a current current value, and calculating a corresponding current level value based on the current current value; judging whether the current level value is consistent with an execution current level value stored in a register or not; if not, inquiring an electrically erasable programmable read-only memory according to the current current level value so as to obtain a metering parameter corresponding to the current current level value, and correcting the metering parameter stored in a register based on the metering parameter corresponding to the current current level value, and updating the execution current level value according to the current current level value, therefore, in the use process of the wide-range electric energy meter, the metering parameters are corrected according to the real-time current value, the accuracy of the electric energy meter can be ensured, the universality of the electric energy meter can be improved, and the research and development and production cost of the electric energy meter can be further reduced under the complex customer requirements.

Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, and a bank select data signal.

The invention provides a charged erasable programmable read-only memory and a preparation method thereof, and the method comprises the steps: obtaining a first semiconductor substrate which comprises a suspension gate covered with a dielectric layer; performing a lithography operation by placing a target photomask on the first semiconductor substrate, resulting in a second semiconductor substrate comprising a barrier layer formed over the floating gate by the lithography operation; ion implantation is carried out on the second semiconductor substrate to form a double-diffusion drain region, a third semiconductor substrate is obtained, and the double-diffusion drain region is limited by the barrier layer in the ion implantation process; forming a control gate in an area corresponding to the suspension gate on the third semiconductor substrate from which the barrier layer is removed to obtain a fourth semiconductor substrate; and respectively performing ion implantation on the fourth semiconductor substrate to form a drain electrode and a source electrode so as to prepare an electrified erasable programmable read-only memory unit, and constructing the electrified erasable programmable read-only memory through the electrified erasable programmable read-only memory unit.

A programmable memory device, the device comprising: at least four memory cells (201, 202, 203, 204), each cell comprising a data storage element (C) connected to a switching transistor (M), wherein the device is arranged such that each switching transistor is connected via a source of the switching transistor to a selection line and via a gate of the switching transistor to a word line for selecting at least one of the at least four memory cells, wherein at least one of the four memory cells is selectable by applying a voltage to at least one of the selection line (S1, S2) and word line (WL1, WL2), so that at least a first and a second switching transistor share the selection line and one of the first and second switching transistors shares the word line with a third switching transistor, and that each data storage element is connected to a shared data line (D) for applying a programming or reading voltage to each memory element of the at least four memory cells to allow programming or reading of the selected memory cell,where the selection line extends parallel to the split data line.,

Systems, computer program products, and methods are described herein for a secure transactional process utilizing a novel approach to data management within resource instruments. The described technology specifically addresses the need for enhanced security in electronic transactions by incorporating a system that dynamically retrieves, encrypts, stores, and subsequently erases transactional data in a secure manner. At the core of these systems is the use of electrically erasable programmable read-only memory (EEPRAM) which temporarily houses transaction details in an encrypted form. The details are securely fetched from an entity server following the verification of a transaction terminal integrity through unique cryptographic keys.

The invention discloses a chip encryption method and device with a dynamically configurable key, and relates to the technical field of chip security, the method comprises the following steps: inputting an initial key to a chip through a chip decryption instruction, activating the chip, writing a new key through an encryption instruction, storing the new key in a chip memory, and carrying out primary encryption on the chip; and the user decrypts the instruction to input a correct key to activate the chip, and enters a normal working state. And when encryption is carried out again, the user inputs a correct secret key to activate the chip through a decryption instruction, then a new secret key is written into the chip through an encryption instruction, the chip stores the new secret key, the encryption state of the chip is updated, and dynamic encryption of the chip is achieved. In order to achieve the method, the encryption device comprises a synchronous serial peripheral interface circuit, a live-line erasable programmable read-only memory and an encryption and decryption circuit, multiple times of conversion of a chip encryption key can be achieved, the problem that the key cannot be changed due to one-time injection is solved, and therefore chip dynamic authorization use can be achieved.

The present invention provides a one-time programmable read-only memory and a writing method and a reading method thereof, which relate to the technical field of integrated circuits, and include a storage unit, wherein the storage unit includes: a first electrode layer, a second electrode layer, and a single material layer between the first electrode layer and the second electrode layer; the storage unit has a first threshold transition voltage and a second threshold transition voltage, and the first threshold transition voltage is greater than the second threshold transition voltage; the storage unit also has a first writing voltage and a reading voltage, and the first writing voltage is greater than the first threshold transition voltage; the first reading voltage is greater than the second threshold transition voltage, and the first reading voltage is less than the first threshold transition voltage. The present invention not only has the function of threshold switching, but also has the advantages of storage function, low static power consumption, simple structure, low process requirements, three-dimensional integration and three-dimensional miniaturization, and is suitable for a cross array structure, especially a high-density three-dimensional one-time programmable read-only memory.

A method for providing error correction for a memory array (10), comprising: for each data word stored in a data storage section (12) of the memory array (10) that has at least one bit error, storing, in an error programmable read-only memory (PROM) (24), an error entry associated with an address of the data word in the data storage section (12) and including error data identifying a bit position of each bit error and correct bit data for each bit error, wherein storing includes programming into a programmable logic device a unique term that is a Boolean combination of the address of the data word in the data storage section (12) and a number of the bit error; monitoring memory addresses presented to the data storage section (12); when a memory address presented to the data storage section (12) is associated with a respective error entry in the error PROM (24), reading, from the error PROM (24), the bit position of each bit error and the correct bit data for each bit error and Substituting the correct bit data into each identified bit position of a memory read circuit arranged to read data from the data storage section (12).

A computer may store records at respective locations in the memory. The records may respectively include, for one of a plurality of variables, an identifier and a size. Responsive to a notification of a software update, the computer may retrieve from the memory a first map of the variables specifying their respective locations in the memory and respective sizes for each of the variables along with the identifiers. The computer may receive, from a remote device, a second map of the variables specifying respective second locations in the memory, and second sizes, for the respective variables along with the identifiers. The computer may store the variables to the respective second locations in memory and store the second map in place of the first map.

The invention discloses a PROM (Programmable Read Only Memory) programmer and a control method. The PROM programmer comprises an upper computer application program and a PROM programming board, and can realize programming of an anti-fuse PROM. Through the matching and cooperation of the upper computer application program and the power supply module, the voltage of different programming stages and other function operations can be adjusted in real time, and an error address can be reprogrammed, so that the repeated programming of the programmed address is avoided, the programming success rate of the anti-fuse PROM is greatly improved, and the programming efficiency of the anti-fuse PROM is improved. Double verification of data can be realized through a four-segment programming algorithm under different voltage conditions and through two times of full-chip backward reading in the algorithm. The PROM programmer is comprehensive in verification function and high in programming success rate, and has important significance in improving the programming success rate and accuracy of the anti-fuse PROM.

The application discloses a kind of dynamic power reconfiguration adaptive sampling power quality monitoring systems, including dynamic power management core, adaptive analog-digital conversion module, harmonic analysis accelerator, double-path interrupt processing module and data storage and communication module, dynamic power management core is divided into three power supply areas and calculates compensation coefficient;Adaptive analog-digital conversion module is used with coefficient to increase gain to offset interference;Harmonic analysis accelerator is handled to generate ultra-limit signal;Double-path interrupt processing module receives signal to trigger alarm;Data storage and communication module contain with protection storage area and the electrically erasable programmable read-only memory of associated fuse circuit.The application is combined by dynamic power management and adaptive analog-digital conversion, improves sampling anti-interference ability and precision;Harmonic analysis is handled and corrected by professional window, enhances the accuracy of abnormal harmonic identification;Data storage area with protection and fuse circuit, strengthen data security and tamper resistance ability, overall optimization power quality monitoring reliability and stability.

This disclosure relates to a real-time data storage method, storage device, and medium emulated using a flash EEPROM. The real-time data storage method emulated using a flash erasable programmable read-only memory (EEPROM) includes: defining a block header and determining the state of a block as one of the following based on the state of the block header: a candidate state, a write start state, a write end state, an active state, a full state, and an inactive state. The real-time data storage method further includes: defining a data header as at least one of a frame start, a first state, a second state, a checksum, and a verification high / low (H / L). The real-time data storage method further includes: determining the state of the data based on the state of the data header. The real-time data storage method further includes: periodically executing storage logic including data storage requests and request result retrieval to store data in real time.