1133 results about "Programmable read-only memory" patented technology

A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

A method and system for maintaining network access point equipment including installing and upgrading software. The system includes a network server, and access point equipment including one or more access point devices, with each device equipped with a CPU including a random access memory (RAM) and a programmable read only memory (PROM). The server is configured for receiving software for maintaining the programming of access point devices. Both the access point devices and the server are programmed with authentication software for identifying each other prior to transmission of maintenance data. The access point devices are further programmed to periodically do a software check with the server. If the current software version in the device is the same as that stored in the server, no action is taken. If the version in the server is different, then the server and device automatically load the current software version into the device.

Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will provide an indication of the stored data at this location in the memory array within the EEPROM or will act as the absence of a transistor at this location in the logic array within the FPLA. The memory array or the logic array includes densely packed cells, each cell having a semiconductor pillar providing shared source and drain regions for two vertical body transistors that have control gates overlaying floating gates distributed on opposing sides of the semiconductor pillar. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data or to represent a logic function, an area of only 2F<2 >is needed per respective bit of data or bit of logic, where F is the minimum lithographic feature size.

A method of making a microelectronic package includes providing a sacrificial layer having a first surface and providing an optoelectronic element having a front face including one or more contacts and a rear surface and securing the rear surface of the optoelectronic element over the first surface of the sacrificial layer. The one or more contacts are then electrically interconnected with one or more conductive pads on the sacrificial layer and a curable and at least partially transparent encapsulant is provided over the first surface of the sacrificial layer so as to encapsulate the optoelectronic element and the conductive pads. The encapsulant is then cured the sacrificial layer is at least partially removed so as to leave said one or more conductive pads on a bottom surface of the encapsulant, the bottom surface of the encapsulant defining the bottom of the package. The optoelectronic element may include a light sensitive chip such as an ultraviolet-erasable programmable read-only memory (UV EPROM) or a light emitting chip, such as a light emitting diode (LED).

The present invention discloses several improved three-dimensional mask-programmable read-only memories (3D-MPROM), including interleaved self-aligned pillar-shaped 3D-MPROM (ISP 3D-MPROM), separate self-aligned pillar-shaped 3D-MPROM (SSP 3D-MPROM), interleaved self-aligned natural-junction 3D-MPROM (ISN 3D-MPROM) and separate self-aligned natural-junction 3D-MPROM (SSN 3D-MPROM). They have larger memory capacity and lower manufacturing cost.

An inventive system and method is provided by an in-car video system that uses a type of electrically erasable programmable read-only memory known as flash memory to store video of an incident or event. In an illustrative embodiment of the invention, a digital video recorder and video camera are fixably mounted in a vehicle such as a police cruiser. An event of interest is captured by a camera and the resulting video stream is converted into a form that writable to a flash memory. The video recorder writes the video to flash memory to thereby store a record of the event on the flash memory as a storage medium.

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

The invention discloses an intelligent gas meter of the Internet of things and a control system thereof, belonging to an intelligent gas meter. The intelligent gas meter comprises a base meter, a CPU (Central Processing Unit) control module and a data transmission module. The base meter is provided with a source gas outlet and a source gas inlet. An electromechanical valve is installed close to the source gas inlet. The CPU control module is connected with the base meter and transmits a control signal to the base meter. The gas consumption standard of the base meter can be adjusted by the CPU control module. The CPU control module comprises an EEPROM (Electrically Erasable Programmable Read-Only Memory) data memory. The data transmission module is indirectly connected with the Internet of things and is also connected with a remote computer management system via the Internet of things. The data transmission module receives the control signal from the remote computer management system and feeds back the gas consumption information transmitted by the CPU control module to the computer management system. The intelligent gas meter of the Internet of things and the control system thereof are suitable for the gas use networks in areas and has the advantages of wide application range and easiness of generalization.

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

A positioning and tracking system may comprise a monitoring station for receiving a location request and a user's identification code and transmitting a signal; a tracking device, which includes a signal receiver for receiving a signal from the monitoring station, including the user's identification code, a microprocessor / logic circuit for storing a first identification code, and generating a position signal; an erasable programmable read-only memory; a global positioning system logic circuit; a signal transmitter; and a plurality of transmitter / receiver stations for communicating between the tracking device and the monitoring station; wherein the tracking device compares the user's identification code to the stored identification code and upon determining that the user's identification code matches the stored identification code, the signal transmitter transmits the position signal to the monitoring station.

A network interface configures a plurality of physical layer devices and a corresponding plurality of network interface devices to allow for the communication of network data between the physical layer devices and corresponding link partners. At least one of the network interface devices is configured as a master device that communicates management information and autonegotiation results with the physical layer devices, while the other network interface devices do not. A configuration source, such as a central processing unit (CPU) or electronic erasable programmable read only memory (EEPROM), receives the autonegotiation results from the physical layer devices, through the master device, and configures the media access controllers (MACs) of each of the network interface devices in accordance with the autonegotiation results. This forces the MACs into their respective proper configurations even though the network interface devices that are not master devices do not receive the autonegotiation results directly from their corresponding physical layer devices.

A system on chip (SOC) contains a core circuit and an input / output (I / O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+ doped drain region and a first P+ doped source region, the second PMOS transistor includes a single-poly select gate and a second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.

An error-correcting fully-buffered memory module can detect and correct some errors in data read from memory chips. An error correction code ECC controller is added to the Advanced Memory Buffer (AMB) on the memory module that fully buffers memory requests sent as serial packets. The error correction controller generates ECC bits for write data, and both the ECC bits and the write data are written to the memory chips by a DRAM controller in the AMB. During reads, an ECC checker generates a syndrome and can activate an error corrector to correct data or signal a non-correctable error. The corrected data is formed into serial packets sent back to the motherboard by the AMB. Configuration data for the ECC controller could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to error-correction configuration registers on the AMB during power-up.

A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.

A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

The invention discloses a configuration, refreshing and program upgrading integrated system for an SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array), belongs to the technical field of aerospace and aims to solve the problem of SEU (Single Event Upset) of the SRAM type FPGA in a spatial irradiation environment. The configuration, refreshing and program upgrading integrated system has a capability of performing program upgrading on the SRAM type FPGA which is in on-orbit work for a long time. The configuration, refreshing and program upgrading integrated system comprises an on-site programmable logic gate array SRAM type FPGA, a comprehensive management anti-fuse FPGA, a configuration program storage chip PROM (Programmable Read-Only Memory), an on-orbit upgrading program storage chip EEPORM (Electrically-Erasable Programmable Read-Only Memory) and an RS422 interface chip. The configuration, refreshing and program upgrading integrated system disclosed by the invention can be used for effectively solving the problem of the SEU of the SRAM type FPGA which is in on-orbit work for a long time and correcting the SEU and single event accumulation inside the SRAM type FPGA without being shut down, also has the function of on-orbit program upgrading of the SRAM type FPGA, and has the characteristics of instantaneity, reliability, flexibility, universality and low cost.

A method, apparatus, and computer instructions for backing up data in a nonvolatile random access memory. Selected data is stored in the nonvolatile random access memory in available space in at least one electrically erasable programmable read only memory in the data processing system to form stored data. The stored data is used to restore the nonvolatile random access memory if nonvolatile random access memory becomes corrupted.

An apparatus for backing up the storage data from a subscriber identity module card will comprise said followings: the subscriber identity module card connector, a central processing unit, a serial electrically erasable programmable read only memory, the displays, the power supply and the inputting device. Firstly, inserting a first subscriber identity module card into a subscriber identity module card connector of the subscriber identity module card backup system is carried out. Then, a first storage data from the subscriber identity module card is extracted and treated to a memory whereby a central processing unit. Next, backing up the first storage data into the memory whereby said central processing unit is achieved. Sequentially, the first subscriber identity module card can be removed from the subscriber identity module card connector. Next, a second subscriber identity module card is inserted into the subscriber identity module card connector. Finally, the first storage data is duplicated from the serial electrically erasable programmable read only memory into the second subscriber identity module card in order to back up the first storage data from the first subscriber identity module card to the second subscriber identity module card.

A sensor assembly used for the measurement of one or more physiologic parameters of a living subject which is capable of storing both data obtained dynamically during use as well as that programmed into the device. In one embodiment, the sensor assembly comprises a disposable combined pressure and ultrasonic transducer incorporating an electrically erasable programmable read-only memory (EEPROM), the assembly being used for the non-invasive measurement of arterial blood pressure. The sensor EEPROM has a variety of information relating to the manufacture, run time, calibration, and operation of the sensor, as well as application specific data such as patient or health care facility identification. Portions of the data are encrypted to prevent tampering. In a second embodiment, one or more additional storage devices (EEPROMs) are included within the host system to permit the storage of data relating to the system and a variety of different sensors used therewith. In a third embodiment, one or more of the individual transducer elements within the assembly are made separable and disposable, thereby allowing for the replacement of certain selected components which may degrade or become contaminated. Methods for calibrating and operating the disposable sensor assembly in conjunction with its host system are also disclosed.

A semiconductor device having an electrically erasable programmable read only memory (EEPROM) comprises a contactless array of EEPROM memory cells disposed in rows and columns and constructed over a silicon-on-insulator wafer. Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region. The semiconductor device further comprises a plurality of gate lines each connecting the gate regions of a row of EEPROM memory cells, a plurality of body lines each connecting the body regions of a column of EEPROM memory cells, a plurality of source lines each connecting the source regions of a column of EEPROM memory cells, and a plurality of drain lines each connecting the drain regions of a column of EEPROM memory cells. The source lines and the drain lines are buried lines, and the source regions and the drain regions of a column of EEPROM memory cells are insulated from the source regions and the drain regions of the adjacent columns of EEPROM memory cells.

An error-correcting fully-buffered memory module can detect and correct some errors in data read from memory chips. An error correction code ECC controller is added to the Advanced Memory Buffer (AMB) on the memory module that fully buffers memory requests sent as serial packets. The error correction controller generates ECC bits for write data, and both the ECC bits and the write data are written to the memory chips by a DRAM controller in the AMB. During reads, an ECC checker generates a syndrome and can activate an error corrector to correct data or signal a non-correctable error. The corrected data is formed into serial packets sent back to the motherboard by the AMB. Configuration data for the ECC controller could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to error-correction configuration registers on the AMB during power-up.

Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will provide an indication of the stored data at this location in the memory array within the EEPROM or will act as the absence of a transistor at this location in the logic array within the FPLA. The memory array or the logic array includes densely packed cells, each cell having a semiconductor pillar providing shared source and drain regions for two vertical body transistors that have control gates overlaying floating gates distributed on opposing sides of the semiconductor pillar. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data or to represent a logic function, an area of only 2F2 is needed per respective bit of data or bit of logic, where F is the minimum lithographic feature size.

A one time programmable read-only memory (OTPROM) device includes a plurality of memory cells, where a memory cell of the OTPROM device comprises a fuse indicating a first memory state of the memory cell if the fuse is destroyed and a second memory state of the memory cell if the fuse is not destroyed, a first transistor coupled to the fuse, and a second transistor serially coupled to the first transistor. Both the first transistor and the second transistor are turned on to select the memory cell, and at least one of the first transistor and the second transistor are turned off to unselect the memory cell. The fuse insulation layer of the fuse and the gate insulation layers of the first and second transistors share a common insulation layer formed in the same fabrication process.