48 results about "One time programmable" patented technology

Examples described herein relate to updating a cryptographic process. In some examples, circuitry is to update a cryptographic process by a write of a firmware image to a non-volatile memory; authenticate the firmware image based on a hash value stored in One Time Programmable Memory (OTPM); and permit execution of the authenticated firmware image to perform the cryptographic process.

This application discloses a one-time programmable memory cell, which includes one anti-fuse programmable transistor, one fuse, and two control transistors. One of a source end and a drain end of a first control transistor is connected to one of a source end and a drain end of the anti-fuse programmable transistor, and the other is connected to one of a source end and a drain end of a second control transistor and one end of the fuse. The other of the source end and the drain end of the second control transistor is connected to the ground. The one time programmable memory cell disclosed in this application can directly correct an error bit through reprogramming, can simplify circuit and layout design, requires a smaller layout area, and has higher reliability and safety.

An integrated circuit (IC) containing a circuit to be operable using one of multiple unequal power supplies during normal operation of the IC. The IC contains a one time programmable (OTP) memory containing a first bit and a second bit, with each of the bit having an initial value and being programmable to a programmed value. A configuration engine contained in the IC operates the circuit with a first selection with respect to using one of the unequal power supplies during normal operation of the IC if both of the first bit and the second bit have an equal value comprising one of the initial value and the programmed value. The configuration engine operates the circuit with a second selection with respect to using one of the unequal power supplies during normal operation of the IC if the first bit and the second bit have unequal values.

A memory device is provided. The memory device includes a nonvolatile memory including a memory cell array, and a controller configured to control the nonvolatile memory. The memory cell array includes: a memory cell including a first magnetic tunnel junction element, an OTP (One-Time-Programmable) cell including a second magnetic tunnel junction element, and a reference cell connected to a first reference resistor for reading data for the memory cell or a second reference resistor for reading data from the OTP cell, wherein the controller is configured to set the second reference resistance, based on a first edge resistance value detected from a resistance distribution of OTP cells comprising the OTP cell or based on the first reference resistance.

A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

A one-time programmable reset memory array and its formation method are disclosed. The method includes: providing a substrate, the substrate including a base and an active region; forming a word line gate structure on the active region, the word line gate structure including a plurality of first implantation portions, second implantation portions, and no implantation portions; forming source and drain doped layers in the active region; forming a first implantation layer in the first implantation portions, the first implantation layer containing first ions; forming a second implantation layer in the second implantation portions, the second implantation layer containing second ions, the first ions and the second ions having different electrical types. Since the first ions and the second ions have different degrees of threshold voltage regulation on the transistor structure, the regulation of the first implantation layer and the second implantation layer can represent two types of data information. Combined with the fact that the no implantation portions can also represent one type of data information, this allows a memory cell in the one-time programmable reset memory array to have three types of data information storage options, thereby effectively increasing the storage capacity of the memory array.

The invention relates to a packet-based one-time programmable memory. A one time programmable (OTP) memory may be coupled to the OTP memory controller. The OTP memory controller may be configured to store (500) OTP data within the OTP memory in a packet format. Data within the OTP packet may identify respective indices, where each of these indices may correspond to a configuration register or other volatile memory location (502, 504). The data may be written to the OTP memory during a manufacturing procedure. During boot or reset, the OTP memory controller in conjunction with a boot loader may read data from the OTP memory and cause the data to be written to a location in volatile memory according to the respective index. After the data has been written to volatile memory, the data may be used to affect fine tuning of the component, support memory repair techniques, function as a security key, etc.

Memory devices, and associated systems and methods, are disclosed herein. A representative memory device comprises a substrate, an insulative layer over the substrate, and a memory array over the insulative layer. The memory device further comprises a fuse array positioned in the insulative layer and configured as a non-volatile memory that can store trimming and / or other factors. The fuse array can comprise a plurality of transistors configured as fuses and each including a source, a drain, and a gate. The transistors in a first subset of the transistors have a first resistance across one of the source, the drain, and the gate that represents a first logic state, and the transistors in a second subset of the transistors can have a second resistance across the one of the source, the drain, and the gate that is greater than the first resistance and that represents a second logic state.

The present disclosure provides a dynamic random access memory (DRAM)-based one-time programming (OTP) memory device and a semiconductor package. The one-time programming memory device based on the dynamic random access memory comprises at least one memory bank which comprises a plurality of memory array blocks (MATs) arranged as a matrix. Each of the plural numbers MAT includes: a complex number line extending in a row direction; a plurality of bit lines extending in a column direction; and a plurality of memory cells located at corresponding intersections of the plurality of digital lines and the plurality of bit lines, each of the plurality of memory cells including a capacitor node. The capacitance nodes of the plurality of memory cells along the column direction in the memory bank are divided into a plurality of capacitance node sections, wherein at least two of the plurality of capacitance node sections are separately controllable.

The invention relates to a one-time programmable primitive and a related method. The present application relates to a one time programmable (otp) cell, the otp cell comprising: a selector device having a channel region; an otp capacitor having an otp capacitor dielectric associated with the selector device; an isolation dielectric having an isolation dielectric thickness tiso; the otp capacitor dielectric includes a first dielectric in a first region and a second dielectric in a second region, the second dielectric having a second thickness t2 less than the isolation dielectric thickness tiso, and the first dielectric having a first thickness t1 less than the second thickness t2, where the first region is embedded in the second region.

The application provides a one-time programmable device forming method, which comprises the following steps: providing a semiconductor device, which comprises a floating gate and a control gate located on an epitaxial layer and arranged at intervals, and a source end and a drain end located in the epitaxial layer and on both sides of the floating gate and the control gate, and an interlayer dielectric layer is further formed on the floating gate and the control gate; forming a via in the interlayer dielectric layer, and filling the via with tungsten by introducing WF6 gas and hydrogen, so as to form a via structure connected with the source end and / or the drain end, wherein, during the tungsten filling process, when the filling operation is interrupted and / or the hydrogen flow is insufficient, the following operations are performed: the temperature of the via filling process condition is set to 300-500 DEG C, the hydrogen flow is set to 500-700 sccm, and the hydrogen introduction time is set to 30-50 s; and the one-time programmable device is filled with tungsten by using the via filling process condition. The application reduces the occurrence of test failure of data retention.

The invention relates to the field of integrated circuits, in particular to an OTP (One Time Programmable) control circuit and application and control method thereof, and the circuit comprises a double-track power supply which comprises a programming power supply switch and a reading power supply switch, one ends of the two switches are connected with a switch network, and the other ends of the two switches are respectively connected with an OTP programming power supply and an OTP reading power supply; the switch network comprises N OTP storage units arranged in parallel and corresponding control switches, one end of each OTP storage unit is connected with the double-track power supply control circuit, and the other end of each OTP storage unit is connected with the corresponding control switch; the other ends of all the control switches are respectively connected with the double-output-bit circuit and the analog state selection circuit; the double-output-bit circuit comprises a first output switch and a second output switch and is used for controlling the turn-off of two output bits; the analog state power supply circuit comprises two switches which are respectively used for controlling a grounding end signal and a power supply end signal. According to the invention, the possibility of data writing or reading errors caused by time sequence chaos of OTP operation is solved.

The invention relates to a one-time programmable memory device in monolithic GaN technology. A one time programmable (OTP) memory device includes a semiconductor die and an OTP memory cell integrated into the die. The die includes a channel layer and a barrier layer forming a heterostructure and a plurality of metallization levels over the heterostructure. The OTP memory cell includes a fuse element having a first impedance value in a native unprogrammed state and a second impedance value in a programmed state, where the first impedance value is lower than the second impedance value; and a selector coupled in series to the fuse element and operable to flow a write current to change the fuse element from an unprogrammed state to a programmed state in an irreversible manner. A fuse element is formed in one of the metallization levels of the die. The selector includes a high electron mobility transistor (HEMT) formed at least partially in a heterostructure.

The invention provides a chip BootLoader dual-mode configuration system, which belongs to the technical field of chip boot programs, is integrated in a chip ROM (Read Only Memory), and comprises an OTP (One Time Programmable) storage module, a dual-mode control module, a UART (Universal Asynchronous Receiver / Transmitter) communication module, a key generation module, a CRC32 verification module, a QSPI (Quantitative Serial Peripheral Interface) module and a command processing module, therefore, the multi-element scene is adapted, and the compatibility and the flexibility are greatly optimized. And a communication key and a program encryption key are generated by adopting a double-key differentiation mechanism based on the unique information of the chip, so that the security protection capability is remarkably improved, and illegal invasion and data leakage are completely eradicated. Therefore, safe, flexible and reliable chip guiding and configuration are realized, and the application requirements of the embedded chip in the fields of industrial control, automotive electronics, Internet of Things and the like are met.

A memory device comprises multiple memory cells, a word line, multiple bit lines, and multiple source lines. Each memory cell includes a once-programmable element (OTP element) and multiple selection transistors. The word line is connected to the gate terminals of the selection transistors of a memory cell. The bit lines are connected in parallel between a first node and a first OTP element terminal of the OTP element of the memory cell. The source lines are connected in parallel and connect second source / drain terminals of the selection transistors of the memory cell to a second node. A method for fabricating the memory device is also disclosed.

Methods of performing updates to a software image that is disposed in a read only memory or a one time programmable memory device are disclosed. The method includes causing an ECC error at the beginning of a function that has been modified. This ECC error causes an exception. The exception handler determines the address where the ECC error was detected was located and searches a dictionary. This dictionary contains entries that each have an original address in the ROM or OTP Memory and the patch address in a nonvolatile writable memory. The exception handler then causes the processing unit to jump to the patch address, where a modified function is located.

A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.

An antifuse-type one time programmable memory cell includes a first select transistor, a second select transistor and a first antifuse transistor. A first terminal of the first select transistor is connected with a first bit line. A gate terminal of the first select transistor is connected with a first word line. A first terminal of the second select transistor is connected with a second terminal of the first select transistor. A gate terminal of the second select transistor is connected with a second word line. A first terminal of the first antifuse transistor is connected with a second terminal of the second select transistor. A gate terminal of the first antifuse transistor is connected with a first antifuse line. When a program action is performed, both of the first select transistor and the second select transistor are turned on.

A memory device may include a memory cell array, a write driver, and a sensing circuit. The memory cell array may include a normal cell connected to a bit line and a one time programmable (OTP) cell connected to the bit line. A program state of the normal cell may be determined by a first reference resistance and a program state of the OTP cell may be determined by a second reference resistance smaller than the first reference resistance. The write driver may perform a first OTP write operation on the OTP cell, and a sensing circuit may determine whether the first OTP write operation on the OTP cell is passed. The write driver may perform a second OTP write operation on the OTP cell experiencing a failure of the first OTP write operation.

The present disclosure provides a programming method of a one-time programming (OTP) memory device based on a dynamic random access memory (DRAM). A selected word line of a selected page is turned on. A sensing circuit is turned on to sense a first data set of the selected page to the sensing circuit. An electrode plate voltage (VPLT) is set to a high voltage and the selected page is programmed. The electrode plate voltage (VPLT) is reduced and the word line of the selected page is turned off.

A memory device includes a first memory array including a plurality of first memory bits. Each of the plurality of first memory bits is configured as a one-time-programmable (OTP) memory bit. A second memory array includes a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit. A lock bit circuit operatively coupled to the first memory array and not the second memory array. The lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.

The application provides a one-time programmable memory cell and a memory array, and relates to the technical field of integrated circuit design. The one-time programmable memory cell comprises a memory structure and a conductive structure arranged below the memory structure; the conductive structure has a first end and a second end arranged oppositely; a write voltage is applied to a write path between any one end of the conductive structure and the top of the memory structure, so that a target region of the conductive structure is disconnected, and data writing of the one-time programmable memory cell is realized; after the target region is disconnected, a read voltage is applied to the one-time programmable memory cell, and the current values of the first end and the second end are compared, so that the read of the written data is realized. The one-time programmable memory cell can compare the current values of the first end and the second end of the conductive structure to read data, does not need to set an additional reference unit to realize the read of data, and can improve the storage density and the write stability of a memory chip in which the one-time programmable memory cell is arranged.

A method for fabricating a memory device is disclosed. The method includes forming a first transistor, and forming a first capacitor electrically coupled to the first transistor. The first transistor and the first capacitor form a first one-time-programmable (OTP) memory cell. The first capacitor is formed to have a first bottom metal terminal, a first top metal terminal, and a first insulation layer interposed therebetween. The first insulation layer is formed to include a first portion, a second portion separated from the first portion, and a third portion vertically extending therebetween. The first bottom metal terminal is formed directly below and in contact with the first portion of the first insulation layer.

A one time programmable memory device includes a field effect transistor and an antifuse structure. A first node of the antifuse structure includes, or is electrically connected to, the drain region of the field effect transistor. The antifuse structure includes an antifuse dielectric layer and a second node on, or over, the antifuse dielectric layer. One of the first node and the second node includes the drain region or a metal via structure formed within a via cavity extending through an interlayer dielectric material layer that overlies the field effect transistor.

A semiconductor device includes an active region on a frontside of the semiconductor. The active region includes an anti-fuse control cell including a plurality of first transistors. The semiconductor device includes a frontside metallization layer coupled with the plurality of first transistors. The semiconductor device includes a one-time-programmable circuit on a backside of the semiconductor device. The one-time-programmable circuit includes a second transistor coupled with a programing wordline (WLP) line of the anti-fuse control cell. The one-time-programmable circuit includes a third transistor coupled with a read wordline (WLR) line of the anti-fuse control cell. The semiconductor device includes a backside metallization layer coupled with the second and third transistor.

A one time programmable memory device includes a field effect transistor and an antifuse structure. A first node of the antifuse structure includes, or is electrically connected to, the drain region of the field effect transistor. The antifuse structure includes an antifuse dielectric layer and a second node on, or over, the antifuse dielectric layer. One of the first node and the second node includes the drain region or a metal via structure formed within a via cavity extending through an interlayer dielectric material layer that overlies the field effect transistor.

Techniques for semiconductor structures are disclosed. In one aspect, a semiconductor structure includes a conductive element on an isolation structure; a dielectric film; a first contact structure, wherein at least a portion of the dielectric film is disposed between the conductive element and the first contact structure; and a second contact structure disposed on and electrically coupled to the conductive element. After a dielectric breakdown has occurred within the portion of the dielectric film, the dielectric film is configured as a resistive element, where the first contact structure and the second contact structure are terminals of the resistive element. Moreover, in the absence of dielectric breakdown within the portion of the dielectric film, the dielectric film is configured as an insulator of a capacitive element, where the first contact structure and the second contact structure are terminals of the capacitive element.

A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bit-line.

The invention relates to a control method and device of an OTP (One Time Programmable) memory, and a control circuit responds to a first programming command and sequentially writes a plurality of data sets into memory cells in the OTP memory. Secondly, when at least one second programming command appears, the control circuit writes the data set indicated in the second programming command into the standby unit according to the sequence of the standby unit. The core of the technical scheme is to reserve a standby unit for the OTP memory so as to realize subsequent reprogramming. According to the method, the requirements of customers during product reprogramming are effectively met, and higher flexibility and sustainability are provided for parameter adjustment of the motor control IC. According to the technical innovation, a user can reprogram new parameters or numerical values for the product under the condition that the existing OTP data is not changed, so that the requirement of a customer on personalized setting of the product is met.