13 results about "One time programmable" patented technology

An integrated circuit (IC) containing a circuit to be operable using one of multiple unequal power supplies during normal operation of the IC. The IC contains a one time programmable (OTP) memory containing a first bit and a second bit, with each of the bit having an initial value and being programmable to a programmed value. A configuration engine contained in the IC operates the circuit with a first selection with respect to using one of the unequal power supplies during normal operation of the IC if both of the first bit and the second bit have an equal value comprising one of the initial value and the programmed value. The configuration engine operates the circuit with a second selection with respect to using one of the unequal power supplies during normal operation of the IC if the first bit and the second bit have unequal values.

A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

The present disclosure provides a dynamic random access memory (DRAM)-based one-time programming (OTP) memory device and a semiconductor package. The one-time programming memory device based on the dynamic random access memory comprises at least one memory bank which comprises a plurality of memory array blocks (MATs) arranged as a matrix. Each of the plural numbers MAT includes: a complex number line extending in a row direction; a plurality of bit lines extending in a column direction; and a plurality of memory cells located at corresponding intersections of the plurality of digital lines and the plurality of bit lines, each of the plurality of memory cells including a capacitor node. The capacitance nodes of the plurality of memory cells along the column direction in the memory bank are divided into a plurality of capacitance node sections, wherein at least two of the plurality of capacitance node sections are separately controllable.

The application provides a one-time programmable device forming method, which comprises the following steps: providing a semiconductor device, which comprises a floating gate and a control gate located on an epitaxial layer and arranged at intervals, and a source end and a drain end located in the epitaxial layer and on both sides of the floating gate and the control gate, and an interlayer dielectric layer is further formed on the floating gate and the control gate; forming a via in the interlayer dielectric layer, and filling the via with tungsten by introducing WF6 gas and hydrogen, so as to form a via structure connected with the source end and / or the drain end, wherein, during the tungsten filling process, when the filling operation is interrupted and / or the hydrogen flow is insufficient, the following operations are performed: the temperature of the via filling process condition is set to 300-500 DEG C, the hydrogen flow is set to 500-700 sccm, and the hydrogen introduction time is set to 30-50 s; and the one-time programmable device is filled with tungsten by using the via filling process condition. The application reduces the occurrence of test failure of data retention.

The invention provides a chip BootLoader dual-mode configuration system, which belongs to the technical field of chip boot programs, is integrated in a chip ROM (Read Only Memory), and comprises an OTP (One Time Programmable) storage module, a dual-mode control module, a UART (Universal Asynchronous Receiver / Transmitter) communication module, a key generation module, a CRC32 verification module, a QSPI (Quantitative Serial Peripheral Interface) module and a command processing module, therefore, the multi-element scene is adapted, and the compatibility and the flexibility are greatly optimized. And a communication key and a program encryption key are generated by adopting a double-key differentiation mechanism based on the unique information of the chip, so that the security protection capability is remarkably improved, and illegal invasion and data leakage are completely eradicated. Therefore, safe, flexible and reliable chip guiding and configuration are realized, and the application requirements of the embedded chip in the fields of industrial control, automotive electronics, Internet of Things and the like are met.

A memory device comprises multiple memory cells, a word line, multiple bit lines, and multiple source lines. Each memory cell includes a once-programmable element (OTP element) and multiple selection transistors. The word line is connected to the gate terminals of the selection transistors of a memory cell. The bit lines are connected in parallel between a first node and a first OTP element terminal of the OTP element of the memory cell. The source lines are connected in parallel and connect second source / drain terminals of the selection transistors of the memory cell to a second node. A method for fabricating the memory device is also disclosed.

The present disclosure provides a programming method of a one-time programming (OTP) memory device based on a dynamic random access memory (DRAM). A selected word line of a selected page is turned on. A sensing circuit is turned on to sense a first data set of the selected page to the sensing circuit. An electrode plate voltage (VPLT) is set to a high voltage and the selected page is programmed. The electrode plate voltage (VPLT) is reduced and the word line of the selected page is turned off.

A method for fabricating a memory device is disclosed. The method includes forming a first transistor, and forming a first capacitor electrically coupled to the first transistor. The first transistor and the first capacitor form a first one-time-programmable (OTP) memory cell. The first capacitor is formed to have a first bottom metal terminal, a first top metal terminal, and a first insulation layer interposed therebetween. The first insulation layer is formed to include a first portion, a second portion separated from the first portion, and a third portion vertically extending therebetween. The first bottom metal terminal is formed directly below and in contact with the first portion of the first insulation layer.

A semiconductor device includes an active region on a frontside of the semiconductor. The active region includes an anti-fuse control cell including a plurality of first transistors. The semiconductor device includes a frontside metallization layer coupled with the plurality of first transistors. The semiconductor device includes a one-time-programmable circuit on a backside of the semiconductor device. The one-time-programmable circuit includes a second transistor coupled with a programing wordline (WLP) line of the anti-fuse control cell. The one-time-programmable circuit includes a third transistor coupled with a read wordline (WLR) line of the anti-fuse control cell. The semiconductor device includes a backside metallization layer coupled with the second and third transistor.

A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.

Because OTP (One Time Programmable) memory, which consists of an antifuse element or a fuse element, lacks a write control function, there is a risk of writing incorrect information due to accidental operation or ESD. [Solution] A memory device having first and second semiconductor memory circuits, each containing a memory element that can be written to only once, characterized in that information stored in the second semiconductor memory circuit is written to the memory element of the first semiconductor memory circuit.

This application provides a memory chip, comprising: a one-time programmable region including a first SOT unit, a switching unit, and a data read unit, wherein a first terminal of the first SOT unit is electrically connected to a bit line, a second terminal of the first SOT unit is electrically connected to a first terminal of the switching unit, a second terminal of the switching unit is electrically connected to a source line, and a third terminal of the switching unit is electrically connected to a word line; the first SOT unit includes a first MTJ and a first spin-orbit matrix layer disposed by contacts; and a data storage region including a second SOT unit, a read unit, and a write unit, wherein a first terminal of the read unit and a first terminal of the write unit are respectively electrically connected to a source line, a second terminal of the read unit is electrically connected to a first terminal of the second SOT unit, a second terminal of the write unit is electrically connected to a second terminal of the second SOT unit, and a third terminal of the second SOT unit is electrically connected to a bit line; the second SOT unit includes at least one second MTJ and a second spin-orbit matrix layer disposed by contacts.

This invention discloses a one-time programmable read-only memory, its control method, and a storage unit, belonging to the field of data storage. When performing a write operation, the invention breaks down the gate oxide layer of the first field-effect transistor specified by the write operation instruction, enabling it to have gate leakage current during operation. When performing a read operation, based on applying a working voltage to the gate of the second field-effect transistor specified by the read operation instruction, the binary value represented by the second field-effect transistor is determined by detecting whether the second field-effect transistor has a sufficient gate leakage current. Since a floating gate structure is no longer used to store charge, a thick floating gate dielectric layer is not required for the field-effect transistor, thereby reducing the process complexity and cost of the field-effect transistor.