103 results about "One time programmable" patented technology

Examples described herein relate to updating a cryptographic process. In some examples, circuitry is to update a cryptographic process by a write of a firmware image to a non-volatile memory; authenticate the firmware image based on a hash value stored in One Time Programmable Memory (OTPM); and permit execution of the authenticated firmware image to perform the cryptographic process.

This application discloses a one-time programmable memory cell, which includes one anti-fuse programmable transistor, one fuse, and two control transistors. One of a source end and a drain end of a first control transistor is connected to one of a source end and a drain end of the anti-fuse programmable transistor, and the other is connected to one of a source end and a drain end of a second control transistor and one end of the fuse. The other of the source end and the drain end of the second control transistor is connected to the ground. The one time programmable memory cell disclosed in this application can directly correct an error bit through reprogramming, can simplify circuit and layout design, requires a smaller layout area, and has higher reliability and safety.

A semiconductor device includes a substrate having a medium-voltage (MV) region and an one time programmable (OTP) capacitor region, a MV device on the MV region, and an OTP capacitor on the OTP capacitor region. Preferably, the MV device includes a first gate dielectric layer on the substrate, a first gate electrode on the first gate dielectric layer, and a shallow trench isolation (STI) adjacent to two sides of the first gate electrode. The OTP capacitor includes a fin-shaped structure on the substrate, a doped region in the fin-shaped structure, a second gate dielectric layer on the doped region, and a second gate electrode on the second gate dielectric layer.

Methods of performing updates to a software image that is disposed in a one time programmable (OTP) memory device are disclosed. The method includes writing an invalid opcode at the beginning of a function that has been modified. This invalid opcode causes an exception. The exception handler determines the address where the invalid opcode was located and searches a random access memory (RAM) dictionary. This RAM dictionary contains entries that each have an original address in the OTP Memory and the patch address in a volatile memory. The exception handler then causes the processing unit to jump to the patch address, where a modified function is located.

An integrated circuit (IC) containing a circuit to be operable using one of multiple unequal power supplies during normal operation of the IC. The IC contains a one time programmable (OTP) memory containing a first bit and a second bit, with each of the bit having an initial value and being programmable to a programmed value. A configuration engine contained in the IC operates the circuit with a first selection with respect to using one of the unequal power supplies during normal operation of the IC if both of the first bit and the second bit have an equal value comprising one of the initial value and the programmed value. The configuration engine operates the circuit with a second selection with respect to using one of the unequal power supplies during normal operation of the IC if the first bit and the second bit have unequal values.

A memory device is provided. The memory device includes a nonvolatile memory including a memory cell array, and a controller configured to control the nonvolatile memory. The memory cell array includes: a memory cell including a first magnetic tunnel junction element, an OTP (One-Time-Programmable) cell including a second magnetic tunnel junction element, and a reference cell connected to a first reference resistor for reading data for the memory cell or a second reference resistor for reading data from the OTP cell, wherein the controller is configured to set the second reference resistance, based on a first edge resistance value detected from a resistance distribution of OTP cells comprising the OTP cell or based on the first reference resistance.

A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

A one-time programmable reset memory array and its formation method are disclosed. The method includes: providing a substrate, the substrate including a base and an active region; forming a word line gate structure on the active region, the word line gate structure including a plurality of first implantation portions, second implantation portions, and no implantation portions; forming source and drain doped layers in the active region; forming a first implantation layer in the first implantation portions, the first implantation layer containing first ions; forming a second implantation layer in the second implantation portions, the second implantation layer containing second ions, the first ions and the second ions having different electrical types. Since the first ions and the second ions have different degrees of threshold voltage regulation on the transistor structure, the regulation of the first implantation layer and the second implantation layer can represent two types of data information. Combined with the fact that the no implantation portions can also represent one type of data information, this allows a memory cell in the one-time programmable reset memory array to have three types of data information storage options, thereby effectively increasing the storage capacity of the memory array.

The invention relates to a packet-based one-time programmable memory. A one time programmable (OTP) memory may be coupled to the OTP memory controller. The OTP memory controller may be configured to store (500) OTP data within the OTP memory in a packet format. Data within the OTP packet may identify respective indices, where each of these indices may correspond to a configuration register or other volatile memory location (502, 504). The data may be written to the OTP memory during a manufacturing procedure. During boot or reset, the OTP memory controller in conjunction with a boot loader may read data from the OTP memory and cause the data to be written to a location in volatile memory according to the respective index. After the data has been written to volatile memory, the data may be used to affect fine tuning of the component, support memory repair techniques, function as a security key, etc.

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a transistor region and an one time programmable (OTP) capacitor region, forming a first fin-shaped structure on the transistor region and a second fin-shaped structure on the OTP capacitor region, and then performing an oxidation process to form a gate oxide layer on the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure have different shapes under a cross-section perspective.

An adaptive control system configurable with a strong PUF source (CSPS), the CSPS being configured to communicate a self-registration state (SES), a key (K) and a key reconstruction state (KRS), the system comprising: an adaptive PUF control unit (ACU) configured to: receive information of an entropy of at least one key, a reliability of the at least one key and a PUF index representative of one of the at least one key; -challenging and configuring a strong PUF source (CSPS); and-receiving a quantized non-binary response in the feedback of a strong PUF source (CSPS); -a PUF control logic finite state machine (CFSM) configured to drive an adaptive control unit (ACU), the CFSM configured to: receive PUF mode operation to first perform self-registration (SE) and then perform key reconstruction (KR); -accessing data representative of a one-time programmable policy (POTP); writing and reading data of the data RAM (DRAM); and-writing and reading one time programmable data (DOTP).

Memory devices, and associated systems and methods, are disclosed herein. A representative memory device comprises a substrate, an insulative layer over the substrate, and a memory array over the insulative layer. The memory device further comprises a fuse array positioned in the insulative layer and configured as a non-volatile memory that can store trimming and / or other factors. The fuse array can comprise a plurality of transistors configured as fuses and each including a source, a drain, and a gate. The transistors in a first subset of the transistors have a first resistance across one of the source, the drain, and the gate that represents a first logic state, and the transistors in a second subset of the transistors can have a second resistance across the one of the source, the drain, and the gate that is greater than the first resistance and that represents a second logic state.

A field of memory technologies and a reading circuit for a differential one time programmable (OTP) memory including a first and second memory cells in a differentially symmetrical structure, the reading circuit connects between the first and second memory cells and includes: a detector having a first and second connected to respective first and second memory cells, configured to detect one of a resistance value of a first or second fuse of respective first and second memory cells, and a resistance difference between the first and second fuse after a burn-in operation of the first or second memory is completed; and a latch connected to the detector, provides a readout data according to one of the resistance value of the first or second fuse, and the resistance difference. The reading circuit may both read out data normally and detect a resistance value of the fuse.

The present disclosure provides a dynamic random access memory (DRAM)-based one-time programming (OTP) memory device and a semiconductor package. The one-time programming memory device based on the dynamic random access memory comprises at least one memory bank which comprises a plurality of memory array blocks (MATs) arranged as a matrix. Each of the plural numbers MAT includes: a complex number line extending in a row direction; a plurality of bit lines extending in a column direction; and a plurality of memory cells located at corresponding intersections of the plurality of digital lines and the plurality of bit lines, each of the plurality of memory cells including a capacitor node. The capacitance nodes of the plurality of memory cells along the column direction in the memory bank are divided into a plurality of capacitance node sections, wherein at least two of the plurality of capacitance node sections are separately controllable.

The invention relates to a one-time programmable primitive and a related method. The present application relates to a one time programmable (otp) cell, the otp cell comprising: a selector device having a channel region; an otp capacitor having an otp capacitor dielectric associated with the selector device; an isolation dielectric having an isolation dielectric thickness tiso; the otp capacitor dielectric includes a first dielectric in a first region and a second dielectric in a second region, the second dielectric having a second thickness t2 less than the isolation dielectric thickness tiso, and the first dielectric having a first thickness t1 less than the second thickness t2, where the first region is embedded in the second region.

The application provides a one-time programmable device forming method, which comprises the following steps: providing a semiconductor device, which comprises a floating gate and a control gate located on an epitaxial layer and arranged at intervals, and a source end and a drain end located in the epitaxial layer and on both sides of the floating gate and the control gate, and an interlayer dielectric layer is further formed on the floating gate and the control gate; forming a via in the interlayer dielectric layer, and filling the via with tungsten by introducing WF6 gas and hydrogen, so as to form a via structure connected with the source end and / or the drain end, wherein, during the tungsten filling process, when the filling operation is interrupted and / or the hydrogen flow is insufficient, the following operations are performed: the temperature of the via filling process condition is set to 300-500 DEG C, the hydrogen flow is set to 500-700 sccm, and the hydrogen introduction time is set to 30-50 s; and the one-time programmable device is filled with tungsten by using the via filling process condition. The application reduces the occurrence of test failure of data retention.

The invention relates to the field of integrated circuits, in particular to an OTP (One Time Programmable) control circuit and application and control method thereof, and the circuit comprises a double-track power supply which comprises a programming power supply switch and a reading power supply switch, one ends of the two switches are connected with a switch network, and the other ends of the two switches are respectively connected with an OTP programming power supply and an OTP reading power supply; the switch network comprises N OTP storage units arranged in parallel and corresponding control switches, one end of each OTP storage unit is connected with the double-track power supply control circuit, and the other end of each OTP storage unit is connected with the corresponding control switch; the other ends of all the control switches are respectively connected with the double-output-bit circuit and the analog state selection circuit; the double-output-bit circuit comprises a first output switch and a second output switch and is used for controlling the turn-off of two output bits; the analog state power supply circuit comprises two switches which are respectively used for controlling a grounding end signal and a power supply end signal. According to the invention, the possibility of data writing or reading errors caused by time sequence chaos of OTP operation is solved.

Disclosed herein is related to physical unclonable function (PUF) with enhanced security based on one time programmable (OTP) memory device. In one aspect, indirection process, hashing or a combination of them can be employed to hide a key for allowing access to an integrated circuit. Each indirection process may include identifying a subsequent address of the OTP memory device based on content stored by the OTP memory device at an address, and obtaining subsequent content stored by the OTP memory device at the subsequent address. Through a number of indirection processes, hidden content stored by the OTP memory device can be obtained. In one approach, hashing can be applied to input bits to obtain an address of the OTP memory device to apply. In one approach, hashing can be applied to the hidden content stored by the OTP memory device to generate the key.

In an embodiment, a method includes receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associated with a respective transistor-based memory cell; providing a program pulse to a first word line coupled to the first transistor-based memory cell to write the first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell; reading redundant bit values from the transistor-based memory cells associated with the plurality of redundant bit addresses; determining a majority bit value based on the first bit value and the redundancy bit value when one of the first bit value and the redundancy bit value does not match the first write value; and asserting the flag signal when the majority bit value does not match the first write value.

The invention relates to a one-time programmable memory device in monolithic GaN technology. A one time programmable (OTP) memory device includes a semiconductor die and an OTP memory cell integrated into the die. The die includes a channel layer and a barrier layer forming a heterostructure and a plurality of metallization levels over the heterostructure. The OTP memory cell includes a fuse element having a first impedance value in a native unprogrammed state and a second impedance value in a programmed state, where the first impedance value is lower than the second impedance value; and a selector coupled in series to the fuse element and operable to flow a write current to change the fuse element from an unprogrammed state to a programmed state in an irreversible manner. A fuse element is formed in one of the metallization levels of the die. The selector includes a high electron mobility transistor (HEMT) formed at least partially in a heterostructure.

The invention provides a chip BootLoader dual-mode configuration system, which belongs to the technical field of chip boot programs, is integrated in a chip ROM (Read Only Memory), and comprises an OTP (One Time Programmable) storage module, a dual-mode control module, a UART (Universal Asynchronous Receiver / Transmitter) communication module, a key generation module, a CRC32 verification module, a QSPI (Quantitative Serial Peripheral Interface) module and a command processing module, therefore, the multi-element scene is adapted, and the compatibility and the flexibility are greatly optimized. And a communication key and a program encryption key are generated by adopting a double-key differentiation mechanism based on the unique information of the chip, so that the security protection capability is remarkably improved, and illegal invasion and data leakage are completely eradicated. Therefore, safe, flexible and reliable chip guiding and configuration are realized, and the application requirements of the embedded chip in the fields of industrial control, automotive electronics, Internet of Things and the like are met.

A memory device includes a plurality of magnetoresistive random-access memory (MRAM) cells including a first one-time programmable (OTP) MRAM cell. A first OTP select transistor is connected to the first OTP MRAM cell. The first OTP select transistor configured to selectively apply a breakdown current to the first OTP MRAM cell to write the first OTP MRAM cell to a breakdown state.

A memory device comprises multiple memory cells, a word line, multiple bit lines, and multiple source lines. Each memory cell includes a once-programmable element (OTP element) and multiple selection transistors. The word line is connected to the gate terminals of the selection transistors of a memory cell. The bit lines are connected in parallel between a first node and a first OTP element terminal of the OTP element of the memory cell. The source lines are connected in parallel and connect second source / drain terminals of the selection transistors of the memory cell to a second node. A method for fabricating the memory device is also disclosed.

The invention discloses a use control method of an OTP ROM (one time programmable read only memory) based on an MCU (microprogrammed control unit) system, which comprises the following steps: a, the MCU detects the current state of the MCU and configures a dormancy signal to a dormancy register according to the current state; b, the monitoring module receives the dormancy signal of the dormancy register and controls the MCU and the OTP ROM to enter a standby mode according to the dormancy signal; c, the monitoring module detects and judges whether a wake-up signal exists in the system or not; and d, when the monitoring module detects that a wake-up signal exists in the system, controlling the MCU and the OTP ROM to enter a working mode. According to the scheme of the invention, the MCU and the OTP ROM can perform dynamic dormancy, the design cost is reduced, the design flexibility is improved, and the power consumption of the system is greatly reduced.

Methods of performing updates to a software image that is disposed in a read only memory or a one time programmable memory device are disclosed. The method includes causing an ECC error at the beginning of a function that has been modified. This ECC error causes an exception. The exception handler determines the address where the ECC error was detected was located and searches a dictionary. This dictionary contains entries that each have an original address in the ROM or OTP Memory and the patch address in a nonvolatile writable memory. The exception handler then causes the processing unit to jump to the patch address, where a modified function is located.

The invention provides a one-time programmable memory cell and a memory array, and relates to the technical field of integrated circuit design. Comprising a storage structure and a conductive structure arranged below the storage structure; the conductive structure is provided with a first end and a second end which are oppositely arranged, and a target area of the conductive structure is disconnected by applying a write-in voltage to a write-in path between any end of the conductive structure and the top of the storage structure, so that data write-in of the one-time programmable storage unit is realized; after the target area is disconnected, reading voltage is applied to the one-time programmable storage unit, and the current value of the first end and the current value of the second end are compared, so that read-in data are read. According to the one-time programmable storage unit, data reading can be carried out by comparing the current values of the first end and the second end of the conductive structure, the data reading can be realized without arranging an additional reference unit, and the storage density and the write-in stability of a storage chip where the one-time programmable storage unit is located can be improved.

Disclosed herein are related to a memory array including one-time programmable (OTP) cells. In one aspect, the memory array includes a set of OTP cells including a first subset of OTP cells connected between a first program control line and a first read control line. Each OTP cell of the first subset of OTP cells may include a programmable storage device and a switch connected between the first program control line and the first read control line. The first program control line may extend towards a first side of the memory array along a first direction, and the first read control line may extend towards a second side of the memory array facing away from the first side of the memory array.

The utility model provides an OTP (One Time Programmable) and electronic equipment. The OTP comprises an array consisting of a plurality of units; each unit comprises three transistors which are arranged in sequence; a programming transistor and two selection transistors; in each unit, the middle transistor is used as a programming transistor, the other two transistors are used as selection transistors, and the programming transistor and any one of the two selection transistors share one N-type doped region to serve as a source electrode. On the basis of keeping high reliability and high safety, the number of transistors in a unit for storing one bit is reduced, four transistors needed in one unit are reduced to three transistors needed in one unit, the size of the memory unit is greatly reduced, the size of the memory is reduced, and the utilization rate of the transistors is improved.

A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.

A system starting method includes: reading secure startup data; judging whether a private key number in the secure startup data is the same as a public key number recorded in a one time programmable memory, where the one time programmable memory records a currently effective public key number; when the private key number is the same as the public key number, performing a system startup procedure; and when the private key number is different from the public key number, sending a startup ending instruction.