41 results about "NOP" patented technology

A virtual memory management unit (306) includes a redundancy insertion module (307) which is used for inserting redundancy into an encoded data stream to be compressed, such that after being compressed each logical data block fits into a different one from a set of equal-sized physical data blocks of a given size. For example, said redundancy may be given by no-operation (NOP) instructions represented by a number of dummy sequences of a given length (L) into an encoded data stream to be compressed, each dummy sequence being composed of a number of identical binary or hexadecimal fill-in values.

Instruction set extension using operand bearing no-operation (NOP) or other instructions. In one embodiment, an apparatus can execute a first instruction with an operand associated with a second instruction. The apparatus includes a decoder to identify an operand associated with the second instruction as being designated for the first instruction. An execution unit executes an operation indicated by the first instruction to operate on the operand associated with the second instruction. The second instruction may occur before or after the first instruction in the program sequence.

An apparatus and a method are provided for a parallel processing very long instruction word (VLIW) computer. The apparatus includes: an index code generation unit sequentially generating an index code, which is associated with a number of no operation (NOP) instruction word between effective instruction words, with respect to each of instruction word groups to be executed in a VLIW computer; an instruction compression unit sequentially deleting the NOP instruction word which corresponds to the index code with respect to each of instruction word groups; and an instruction word conversion unit converting the effective instruction words to include the index code, the effective instruction words corresponding to the NOP instruction words.

A microprocessor to reduce wasteful power consumption of the floating-point unit. An instruction invalidation logic circuit is utilized to substitute the instruction not-to-use-the-floating-point unit, in the instruction string supplied from the instruction cache, with an invalidating instruction, hold that invalidating instruction in the floating-point register, and supply that invalidating instruction to a floating-point decoder in the floating-point unit. In cases when the invalidating instruction was continuous, the power consumption in the floating-point data path as well as the in the floating-point decoder and floating-point register is reduced.

A processor is described in which the need to encode no-operation instructions (nops) in the program is minimised by providing a device for generating nops in response to information encoded in operative instructions.

The invention discloses a synthesis method of amikacin. The synthesis method comprises following steps: firstly, a partially silanization protection product of kanamycin A is prepared; dehydration of the partially silanization protection product with PHBA under the action of DCC is carried out so as to obtain a acylated product; the acylated product is subjected to hydrolysis, nitrilase, and column chromatography purification so as to obtain amikacin. According to the synthesis method, NOP is not used, synthesis of an active ester via esterification is avoided, damage on the health of workers is reduced greatly, solid waste generated in production process is reduced greatly, product yield is increased, and the synthesis method is especially suitable for industrialized production.

A processor implementation supports selection of an execution mode for debug instruction instances based on respective addresses thereof in addressable memory can provide an attractive mechanism for executing debug instructions in a way that allows some instances of the instructions to operate with debug semantics while suppressing other instances by executing them with no-operation (NOP) semantics. In some embodiments, selection of operative execution semantics may be based on attributes of a memory page in which a particular debug instruction instance resides. In some embodiments, portions of an address space may be delimited (e.g., using values stored in bounding registers and addresses of particular debug instruction instances compared against the delimited portions to select appropriate execution semantics. In some embodiments, both types of evaluations may be used in selecting appropriate execution semantics for a particular debug instruction instance.

Efficient techniques are described for not executing an issued conditional non-branch instruction. A conditional non-branch instruction is identified as being eligible for a prediction, the prediction indicating that the eligible conditional non-branch (ECNB) instruction would not execute. The ECNB instruction executes as a no operation (NOP) instruction in response to the prediction that the ECNB instruction would not execute. A source operand required for the ECNB instruction to execute is not fetched in response to the prediction to not execute.

The invention discloses a method, a device and a system which uses a one time programmable (OTP) internal storage as a multi-time programmable (MTP) internal memory configuration. Using the OTP internal memory through the method enables encoding to be renewed one or more times, but the advantages that the size is small and processing and manufacturing can be achieved easily are kept. The encoding can be a procedure code of a processor, such as a startup code, a startup code kernel or other command codes. In a way, one OTP inner memory can be functionally operated like an MTP, and is a No Operations (NOP) command through being intelligentized, and then if a specific subprogram or a function is needed to be modified, a user writes a command (such as a JUMP command) to enter the address of NOP, so that some specifically existing commands are enabled to be bypassed, and a command code of a new module is carried out.

The present invention discloses a method for compressing instruction codes. This method comprises: compressing an instruction block including a plurality of instructions according to Huffman-Encoding technique; determining whether it's necessary to insert no-operation (nop) instructions among the plurality of compressed instructions according to a compression ratio, so as to generate a plurality of new instruction blocks conforming with the compression ratio; if it's necessary to insert nop instructions, inserting nop instructions among the plurality of compressed instructions to form the plurality of new instruction blocks; and repeating the above-mentioned steps until no nop instructions have to be inserted.

A method for estimating energy usage of a program code executed by a very long instruction word (VLIW) processor. The program code includes multiple instructions, which are organized as groups referred to as execution sets. The instructions of an execution set are executed simultaneously. A no operation (NOP) energy and incremental instruction energy for each execution set of the program code are determined to compute a base energy of each execution set. An inter-execution set energy of each execution set is then computed. The estimated energy usage of each execution set is determined by adding the corresponding inter-execution set energies to the base energies. A stall energy consumed on account of executing the program code is then computed. Finally, the estimated energy usage of the program code is determined by adding the stall energy to the determined energies of all the execution sets.

Provided is a technique that is capable of efficiently compressing instructions by inserting instruction compression bits into valid instruction bundles and deleting no operation (NOP) instruction bundles. Accordingly, the number of instructions that can be parallel-processed in a processor may be increased.

A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.

The invention relates to a robot controller and a robot system. The robot controller includes queues, a storage unit, and an execution control unit. The queues are provided for respective controlled groups serving as controlled units. The storage unit stores therein instructions directed to the respective controlled groups, one at a time, from a bottom end of each of the queues. When having accepted a predetermined operation request, the execution control unit simultaneously fetches the instructions directed to the controlled groups, one for each of the controlled groups at a time, from tops of the queues, and makes all of the controlled groups simultaneously start the operations based on such instructions. If there is any controlled group to which no corresponding instruction exists, the storage unit stores therein a no-operation instruction (NOP). If the fetched instruction is the no-operation instruction (NOP), the execution control unit keeps the controlled group from operating until an instruction is fetched next time.

An electronic apparatus generating compiled data used in a very long instruction word (VLIW) processor including a plurality of function units is provided. The electronic apparatus includes a storage and a processor configured to control the storage to store the compiled data in which a plurality of VLIW instructions are compiled, identify a VLIW instruction from the compiled data; and update, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within a cycle corresponding to a latency of the identified VLIW instruction and if an end cycle of another VLIW instruction is within the cycle corresponding to the latency of the identified VLIW instruction, the compiled data by including information on a cycle difference between an end cycle of the identified VLIW instruction and the end cycle of the another VLIW instruction in the multi-cycle nop instruction.