12 results about "Virtual memory management" patented technology

An arrangement for managing memory in a content-based publish / subscribe systems. The system receives communications from subscribers and publishers. The subscriptions and published services, such as events and advertisements, are matched together and packed in batches together so that the context memory of a large language model is used in an efficient manner. The data that is repeating itself in plurality of communications can be stored in a shared prompt memory and the size of the batches is reduced.

Apparatuses, systems, and techniques for memory management are disclosed. In at least one embodiment, memory management is provided for a heterogenous system, for example, a system including a CPU and a GPU, in which redundant or unnecessary memory transfers are reduced.

The invention belongs to the technical field of large-scale deep learning model training, and particularly relates to a video memory scheduling system based on dynamic sequence length assembly line parallel training. The system comprises a dynamic recalculation module, a video memory arrangement and prefetching module and a mapping reconstruction module, the system collects the length and load information of each micro-batch before each round of iteration, establishes an optimization model with the goal of minimizing the iteration time, dynamically generates a re-calculation plan, and realizes inter-stage video memory load balancing; by introducing a collating stream and an asynchronous scheduler outside a main computing stream, overlapping execution of video memory collating and computing prefetching is realized, and the influence of fragment collating on training performance is reduced; a dynamic physical block mapping strategy is designed based on a CUDA virtual memory management mechanism, the physical block granularity is adaptively adjusted according to the idle state of the video memory, and the API calling and context switching overhead is reduced. Experimental results show that the video memory utilization rate and the system stability are remarkably improved, and an efficient video memory scheduling scheme is provided for large model training.

The invention relates to the technical field of local intrusion detection, in particular to a network information security state detection and evaluation system and method.The system comprises a memory page attribute portrait collecting module, a memory management unit event monitoring module, a memory page access, modification and execution request intercepting and capturing module and a memory management unit event executing module, and the memory page attribute portrait collecting module is used for hooking a missing page exception handling function through an operating system kernel module; and querying the virtual memory manager to obtain the permission bit and the source information of the memory page. According to the method, access, modification and execution requests of the memory page are intercepted by hooking a missing page exception handling function of an operating system kernel, a microcosmic instruction execution sequence is captured by utilizing an extended page table (EPT) monitoring instruction extraction technology, and a memory page attribute portrait containing a permission bit, a source, a JIT state and a timestamp is constructed; by means of the processing mode, unprecedented depth and breadth monitoring on memory activity is achieved, monitoring on a traditional file or API level is exceeded, and underlying logic of memory management is directly deepened.

The application provides a method for accelerating processing of a distributed virtual memory request, applied to a distributed virtual memory management node, and the method comprises the following steps: receiving and storing a distributed virtual memory request sent by a first request node; monitoring a processing time length of the distributed virtual memory request; and in response to the processing time length of the distributed virtual memory request exceeding a time length threshold, performing accelerated processing on the distributed virtual memory request. The application also provides a distributed virtual memory management node, a computer readable storage medium and a computer program product. According to the technical scheme of the application, the scheduling and broadcasting mechanism of the distributed virtual memory request can be optimized, the request accumulation can be effectively relieved, the risk of core blocking and request timeout can be reduced, and thus the overall performance of the system and the address consistency maintenance efficiency can be improved.

This invention discloses a heterogeneous storage control system, method, and medium based on multidimensional address structure awareness, belonging to the field of high-performance computing architecture. The system integrates an L1 / L2 hierarchical multidimensional translation backup buffer (MD-TLB), a hardware tensor page table walker with an exception state machine, a pipelined spatial address operation unit (SAMU) supporting indirect step size and lookup table caching, and a consistency engine supporting range invalidation. The controller establishes physical address sovereignty through a memory pinning protocol and an IOMMU exemption mechanism; efficiently processes sparse tensors using indirect step size logic; ensures atomicity and resource reclamation during task switching through pipelined draining and a safety heartbeat watchdog; and eliminates bus storms using a range consistency protocol. This scheme significantly reduces the number of address translation stages, solves the problems of sparse data adaptation and hardware deadlock in heterogeneous computing, and achieves highly reliable, low-latency semantic virtual memory management.

The invention provides a method for accelerating processing of a distributed virtual memory request, the method is applied to a distributed virtual memory management node, and the method comprises the following steps: receiving and storing the distributed virtual memory request sent by a first request node; monitoring the processing duration of the distributed virtual memory request; and in response to the condition that the processing duration of the distributed virtual memory request exceeds a duration threshold, performing acceleration processing on the distributed virtual memory request. The invention further provides a distributed virtual memory management node, a computer readable storage medium and a computer program product. According to the technical scheme of the invention, the scheduling and broadcasting mechanism of the distributed virtual memory request can be optimized, the request accumulation can be effectively relieved, and the core blockage and request timeout risk can be reduced, so that the overall performance of the system and the address consistency maintenance efficiency can be improved.

The present invention discloses a virtual memory management method and device that supports physical addresses larger than virtual addresses. The method includes: determining the target virtual address corresponding to the instruction fetch address or memory access address in any of the user mode, supervisor mode or machine mode; determining the target physical address corresponding to the target virtual address by accessing the virtual memory management unit, the virtual memory management unit having a built-in page table entry for mapping the virtual address to the physical address, and the target virtual address bit width may be less than or equal to the target physical address bit width, especially in the field of multi-core applications; finally returning the target physical address to the corresponding instruction fetch unit or memory access unit, and ensuring correctness and validity. By adopting the embodiment of the present invention, the address translation from virtual address to physical address can be completed when the virtual address bit width is less than the physical address bit width, and the multi-core architecture can be ensured to work effectively in multiple modes such as user mode, supervisor mode and machine mode. The applicability of the present invention is high.

The present invention provides a method for compensating the main memory capacity of an electronic device, which relates to the field of electronic device memory technology. The method collects historical program execution data to set compensation space, obtains K time intervals, analyzes congestion parameters to obtain K congestion parameters, inputs a compensation analysis model, obtains K virtual memory compensation parameter sets, performs weighted calculations on each of the K virtual memory compensation parameters, and performs compensation management. When the real-time congestion parameter is greater than the congestion parameter of the real-time time interval, the real-time virtual memory compensation parameter is obtained and the compensation space is managed. The present invention solves the technical problems in the prior art of virtual memory being set too large, wasting hard disk space, or too small to meet program execution requirements. The method implements memory compensation based on the user's electronic device program execution habits, thereby improving the accuracy of virtual memory management and the speed of program execution.

A data processing network includes request nodes having local memory accessible as distributed virtual memory (DVM) and coupled by an interconnect structure. Multiple DVM domains are assigned, each containing a DVM node for processing DVM operation requests from request nodes in the domain. Upon receiving a request, the DVM node sends a snoop message to other request nodes in its domain and to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes and sends a completion message to the first request node. Each peer DVM node sends a snoop message to request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this manner, DVM operations are performed in parallel.

The invention relates to a memory management method and device and a storage medium. Relates to the technical field of computers. The method is applied to a firmware IP, and comprises the steps that if it is determined that a first physical memory needs to be configured, a first virtual address range corresponding to a first virtual memory allocated to the first physical memory is determined based on an address mapping table and / or dynamic virtual memory management information; the first virtual memory comprises a part of or all storage space of a target virtual memory in the distributable virtual memory; determining the first virtual address range and a first physical address of the first physical memory as item information corresponding to the first physical memory; updating or creating a management entry corresponding to the first physical memory in the address mapping table based on the item information of the first physical memory; the capacity of the allocable virtual memory corresponds to the address bus width of the firmware IP, and the capacity of the allocable physical memory where the first physical memory is located is larger than the capacity of the allocable virtual memory. And the memory access of the firmware IP is not limited by the own address bus width.

The embodiment of the invention discloses a virtual memory management method and system, a graphics processor and electronic equipment. The method comprises the steps that an allocation request sent by a target thread of the graphics processor is received; wherein the allocation request comprises a first memory demand of the target thread; based on the first memory demand of the target thread and the tracking information of the virtual memory, determining an allocation result of the target thread; wherein the virtual memory is managed through a corresponding binary tree; the binary tree comprises n layers, a root node of the binary tree is located on the nth layer of the binary tree, the jth layer of the binary tree comprises 2n-j nodes, and j is a positive integer not larger than n; the virtual memory comprises 2n-1 memory blocks; the tracking information comprises the state of the memory block corresponding to each node of the binary tree.