155 results about "Virtual address space" patented technology

The invention discloses a memory access method, a program product, equipment and a medium, and relates to the technical field of computers, firmware is utilized to determine to-be-reserved physical memory information, the to-be-reserved physical memory information is analyzed and continuously split to obtain physical memory segments, and the physical memory segments are divided and aligned; dividing the virtual address space, and performing alignment processing on the divided virtual address space; performing memory mapping on the processed physical memory segment and a physical address space corresponding to the processed virtual address space; generating a page table by utilizing a physical address space corresponding to the mapped and processed virtual address space; when an access instruction of a user is obtained, the corresponding target physical address space is screened from the page table to determine the mapped target physical memory segment, so that the user accesses the target physical memory segment based on the user mode process, the range and capacity of the memory segment are dynamically configured, the stability of the memory during key load operation is guaranteed, and the memory access performance is improved.

The invention discloses a method, a product and equipment for sharing a file system by multiple hosts and a storage medium, and relates to the technical field of computers, which comprises the following steps: configuring a shared memory device as a character device, directly mapping to a user mode virtual address space, bypassing a kernel page cache, and directly reading and writing a physical address of the shared memory. A shared memory is divided into a super block area, a metadata area, a log area and a data area during formatting, all hosts perform unified operation through the shared metadata area, stand-alone cache interference is avoided, a hidden metadata file is created to map a non-data area during mounting, a log item is scanned to reconstruct a directory file structure, and the mounting efficiency is improved. All hosts generate a directory file structure completely consistent with the shared memory through log replay, the problem of data consistency caused by a cache strategy in a traditional multi-host file system is solved, and the effects that multiple hosts share a unified memory view, operation is real-time and synchronous, and data access delay is reduced are achieved.

The invention discloses a cross-host memory sharing method, system and device and a medium, the memory sharing system comprises a master node and a plurality of slave nodes, the memory sharing method is applied to the master node, and the method comprises the steps that a memory application request of a target slave node is received; applying for a target memory in a target memory sharing area according to a memory size requirement corresponding to the request, feeding back memory information of the target memory to a target slave node, so that the target slave node judges a corresponding memory type according to the memory information, and if a process corresponding to the target slave node executes a memory mapping method, sending the target memory to the target slave node. If yes, the target memory can be mapped to the proceeding virtual address space according to the target type and the offset corresponding to the target memory, so that the process can use the distributed target memory. Therefore, it can be guaranteed that when one node writes the memory, other nodes cannot synchronously write the memory, and then the data consistency of the shared memory accessed by multiple hosts is guaranteed.

The embodiments of the present disclosure provide data processing methods, a computer system, a computer-readable storage medium and a computer program product. A data processing method comprises: acquiring a first control command transmitted by a second service program, and determining a physical address region; applying for a virtual address region from a second virtual address space to which a service data storage region is mapped, and on the basis of the virtual address region, generating a second control command; and establishing a mapping relationship between the virtual address region and the physical address region for a first service program to access the physical address region on the basis of the virtual address region in the second control command acquired from a control command storage region. The technical solution provided in the embodiments of the present disclosure realizes high-speed data transmission between service programs.

The embodiment of the invention discloses a GPU video memory channel allocation method and device, equipment and a storage medium. An exemplary embodiment of the method comprises the following steps: pre-applying for a plurality of physical video memory pages from a physical video memory space; mapping video memory colors to the plurality of physical video memory pages according to a mapping table of colored partitions and video memory colors of the physical video memory pages to obtain video memory channels corresponding to the colored partitions; in response to a detected target task of performing video memory operation according to the required color and the required space, querying an unallocated colored partition of a video memory channel corresponding to the required color; and distributing a target physical video memory page to the target task from the plurality of physical video memory pages according to the demand space, and returning a virtual address space corresponding to the target physical video memory page to the target task for use.

The invention discloses a zero-copy data transmission method and device, a medium and a product, and belongs to the technical field of data transmission, and the method comprises the steps that an application program requests a memory buffer area from a kernel module; the kernel module allocates a physical memory buffer area according to the request, and returns a specially designed descriptor (including a handle corresponding to an address pointer); the application program submits a descriptor to the kernel module and requests an address pointer of the memory buffer area; after the kernel module verifies the descriptor, the physical memory buffer area is mapped to a virtual address space of the application program, and a corresponding address pointer is returned; the application program writes data needing to be sent according to the address pointer, and after writing is completed, the descriptor is submitted to the kernel module and the written data is requested to be sent; after the kernel module verifies the descriptor, a DMA controller is configured and started, and the written data is directly read from the physical memory buffer area and pushed to a network card to be sent. According to the invention, the security and certainty can be improved while the transmission performance is ensured.

The invention relates to a memory management method and device applied to a server-free data center, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: in response to a virtual memory application instruction, performing virtual memory allocation in a local computing resource pool to obtain a virtual address space; in response to the virtual address access instruction, acquiring cache information of the computing resource pool, and triggering missing page interruption under the condition that data corresponding to the virtual address is not hit in the cache information; the cache information comprises locally cached cache data and page table information; acquiring physical memory resources in a memory resource pool according to the virtual address and the page table information under the condition of triggering missing page interruption of the anonymous page; and updating the page table information and the cache information according to the physical memory resources. By adopting the method, the processing delay of the data center can be reduced while the decoupled memory management logic is used for improving the resource utilization rate.

The invention relates to an electric power mobile application security protection method based on a swan gap microkernel, which comprises the following steps of: S1, establishing a hardware trust root, and storing a device root key and a certificate chain by utilizing a non-tampering storage area built in a chip; s2, establishing a complete trusted boot chain based on a hardware root of trust, and verifying the integrity and credibility of the next layer by each layer from Bootloader to a swan microkernel and then to an application program; s3, constructing a triple authentication system based on user identity, equipment identity and biological characteristics, and performing user authentication; s4, according to a user authentication result, realizing fine-grained authority control based on an RBAC model and ABAC, and ensuring that authority check can be executed during resource access every time by utilizing an IPC security mechanism of a swan micro kernel; and S5, creating an independent execution environment for each power application according to the process isolation capability of the swan microkernel, and ensuring that memories among the applications cannot be mutually accessed through virtual address space isolation. The reliability of power mobile application safety protection is effectively improved.

The invention discloses a time delay optimization method and device of a network interconnection system, electronic equipment and a medium, and relates to the field of network communication, and the method comprises the steps: adjusting the BAR resource window size of a non-transparent bridge processor in a BIOS based on a firmware file of a target processor, and re-burning the adjusted BIOS to a BMC processor, and initializing each DMA channel in the non-transparent bridge processor to obtain a physical address of each DMA channel, identifying the minimum physical address as a mapping initial address of the BAR, and mapping the mapping initial address and the BAR address space sum to a virtual address space of a user mode so as to access each DMA channel. The problem that the requirements for the overall bandwidth and low delay of the storage controller cannot be met when one DMA channel is started is solved, the data concurrent processing capacity of the non-transparent bridge processor is improved by enabling the four DMA channels and mapping the four DMA channels to the user mode, and therefore the interconnection bandwidth of the controllers is higher, and the interconnection delay of the controllers is lower.

The invention relates to the technical field of data acquisition, and discloses a PCIe-based DMA data zero copy processing method and system. The method is applied to a zero copy processing system, and comprises a HOST module for distributing a physical DMA buffer area and mapping a physical address of the DMA buffer area to a logically continuous virtual address space; the HOST module is used for constructing a preset descriptor queue and sending a head address of the queue to the FPGA module; the FPGA module receives the initial address of the queue through a PCIe interface, analyzes a descriptor, and writes DMA data with a preset transmission length into a sub DMA buffer area of the HOST module; and the HOST module monitors the state of the DMA buffer area and adopts a dynamic flow control mechanism to adjust the data transmission rate of the FPGA module according to the state. According to the method provided by the embodiment of the invention, the physical DMA buffer area is mapped to the logically continuous virtual address space, and the application program can directly access the DMA data in the user space without copying through the middle of a kernel, so that zero-copy access is realized, the data processing delay is reduced, and the data transmission efficiency is improved.

The invention provides a unified memory system based on heterogeneous computing, belongs to the field of parallel computing and artificial intelligence, and realizes memory sharing by constructing a global virtual address space and eliminating explicit data transmission between a host end and an equipment end. The core module comprises: 1) a cache consistency manager, which adopts an adaptive protocol (write broadcast / write invalidation) and a cache directory table (CCDT) to ensure data consistency; 2) an MMU memory management unit which supports dynamic address translation, on-demand distribution and page migration; and 3) an intelligent data migration unit which dynamically migrates the hotspot data to a near-end memory based on the prediction model and reduces the access delay. The architecture is suitable for edge AI applications with high requirements on real-time performance and energy efficiency.

The invention provides an aggregate communication method, system and device based on a hybrid expert model, and relates to the technical field of communication, in particular to the technical fields of chip processors, computing power clusters, aggregate communication operation, large models and the like. The set communication method is applied to a communication receiving end and comprises the steps that a data writing instruction is received, and the data writing instruction comprises to-be-processed data and first address information; accessing a virtual expert address in a pre-created virtual address space according to the first address information; based on the size of the to-be-processed data, applying for a corresponding actual physical space for the virtual expert address; and writing the to-be-processed data into the actual physical space. According to the set communication method provided by the invention, set communication can be realized without memory information synchronization.

The invention provides a DPU equipment initialization method, and relates to the field of computer equipment. According to the method, a BAR space mapping process, a PCI device initialization process, a PF data channel initialization process and a VP data channel initialization process are executed respectively; the method comprises the following steps: firstly, carrying out IO remap mapping operation on a BAR register, and mapping a physical address of the BAR register to a virtual address space of a Linux kernel to obtain a BAR space; then PCI device initialization is carried out through the BAR space; secondly, initializing a PCI driver and a kernel timer, and on the basis, maintaining a work queue task and periodically executing port state polling; and finally, distributing an interrupt vector to the VP data channel, and managing the on-off of the VP data channel through the interrupt vector. The invention provides a complete and systematized initialization processing scheme of the DPU high-speed daughter card based on the domestic chip, which is beneficial to improving the development efficiency of domestic equipment.

The invention relates to a video memory management method and device, electronic equipment, a storage medium and a program product. The method comprises the steps that a target user memory context corresponding to a target user process is created, and the target user memory context is used for managing a target virtual address space corresponding to the target user process and a target video memory space corresponding to the target user process; for at least two pieces of GPU firmware used for executing a task of the target user process, virtual address subspaces in the target virtual address space are distributed to the at least two pieces of GPU firmware; and for any one of the at least two pieces of GPU firmware, the GPU firmware updates the page table information of the firmware memory context corresponding to the GPU firmware according to the page table information of the target user memory context and the virtual address subspace corresponding to the GPU firmware.

The invention provides an intelligent grading and excess subscription management system and method for a GPU video memory, and relates to the technical field of GPU video memory management, and the method comprises the steps: firstly building a grading storage system comprising a first performance region and a second performance region; then receiving a video memory allocation request containing task priority and service quality requirements, and monitoring a data access mode and access frequency; the initial placement position of the data block is dynamically determined through the intelligent engine according to the task priority, the data access mode and the frequency; predicting target access probability distribution of each data block by adopting an LSTM network; then migrating data between the first performance area and the second performance area through a swap-in and swap-out mechanism based on the distribution and periodicity characteristics, and ensuring the service quality of the first performance area; finally, the global oversale proportion is dynamically adjusted through an overpurchase safety management module, an independent virtual address space is distributed for each task, and safe overpurchase can be achieved through the process.

The invention relates to the technical field of computer system structures, in particular to a unified memory and data transmission system and management method for an FPGA heterogeneous platform, and the system comprises a CPU component which is used for detecting and initializing an FPGA component, constructing a globally unified virtual address space view, managing a global page table, maintaining a mapping table, managing PCIe communication and processing exceptions; the FPGA component is used for PCIe DMA data transmission, conversion from a virtual address to a physical address, striped on-chip storage and storage of user acceleration function logic implementation; and the PCIe bus is used for data transmission of the CPU component and the FPGA component. Physical memory resources of the CPU component and the FPGA component are integrated and dynamically mapped to a unified virtual address space in a software and hardware cooperation mode, a simple, safe and flexible unified memory system and management method are provided, and efficient memory management and data transmission between the CPU and the FPGA are achieved.

The invention provides an address management method and device for a heterogeneous system and computer equipment, and relates to the technical field of computers, in particular to the fields of data processing, data transmission and the like. According to the implementation scheme, a second virtual address space of a data transmission module is divided into second sub-virtual address spaces with the same number as that of data processing modules, and the size of the second sub-virtual address spaces is the same as that of first virtual address spaces of the data processing modules; distributing a unique identifier to the data processing module, wherein the unique identifier is a natural number; for the first virtual address space, the first virtual address space is offset by a preset offset through the unique identifier, so that a second sub-virtual address space corresponding to the first virtual address space is determined in the second sub-virtual address space, and the preset offset is a product of the unique identifier and the size of the first virtual address space; and establishing a mapping relationship between the first virtual address space and the corresponding second sub-virtual address space.

A method for accessing a shared memory database applied to a server is provided. The method includes: invoking a API interface and obtaining an access request sent by an external program; sending an identification file in a database to the external program according to the access request, controlling the external program to wait to access a shared memory according to an identification value in the identification file; according to the identification value in the identification file, opening a channel for the external program to access the shared memory; mapping the shared memory to a virtual address space of the external program, and the database being loaded into the external program; controlling the database and the external program to perform a data interaction in the shared memory.

The invention discloses an AI model reasoning method and device and related equipment, and relates to the technical field of artificial intelligence. The AI model and the obtained input data are used for iterative reasoning, a reasoning result is obtained, a processing module in the AI model corresponds to a first physical storage area indicated by the first virtual address space, and the first physical storage area is used for storing KV generated by the processing module in the iterative reasoning process. And when the first physical storage area is not enough to continue to store KV generated by the processing module executing data processing in the Nth reasoning process, allocating a second physical storage area indicated by a second virtual address space to the processing module to store the KV. Wherein the second virtual address space is continuous with the first virtual address space. Thus, the KV generated by the processing module is stored in a mode of allocating the physical storage area according to needs, the utilization rate of the physical storage area can be improved, and operators in the processing module do not need to have the capacity of splicing the KV in a virtual address space.

The invention discloses a data sharing method and device and electronic equipment, and belongs to the technical field of electronics. The data sharing method comprises the steps that at least two physical pages which are stored in a CPU kernel mode physical address space and correspond to target data are determined, and the target data are data corresponding to at least one process; and establishing a first mapping relationship between each physical page and a first virtual address, wherein the first virtual address is a virtual address in a first virtual address space of the heterogeneous processor.

Methods and systems are provided for allocating memory. An example method includes: allocating, for an application logic, a region of external primary memory included in a memory appliance; selecting, by a client device in response to a first request to reclaim a first portion of local primary memory in the client device, a portion of external primary memory from the region of external primary memory; copying data from the first portion of local primary memory to the portion of external primary memory; and converting a portion of a first virtual address space at the client device by remapping at least one virtual address in the first virtual address space at the client device from the first portion of local primary memory to the portion of external primary memory.

This application discloses a storage system, a data processing method, an apparatus, a node, and a storage medium, and pertains to the field of data storage technologies. In the method, a client determines an address that is in a storage unit and that is used to store to-be-written data, and sends the to-be-written data to a first storage device that is in a storage node and that is corresponding to the storage unit, so that the first storage device stores the to-be-written data while a CPU of the storage node does not need to determine a hard disk LBA corresponding to virtual address space, and a hard disk does not need to determine a corresponding physical address based on the hard disk LBA.

The invention relates to the technical field of computers, in particular to a data transmission method and device, electronic equipment and a storage medium, and is used for improving camera data transmission efficiency in a cross-system environment. The method is applied to the electronic equipment comprising a host machine, the host machine is used for creating and running a virtual machine through a virtualization engine, and operating systems are different. The method comprises the following steps: in response to an image acquisition request initiated by a target application in a virtual machine, creating a shared memory area through a host machine; calling an image acquisition device through a host machine to obtain image frame data, and storing the image frame data in a shared memory area; mapping a physical address of the image frame data in the shared memory region into an initial address visible to a virtual machine through a virtualization engine; mapping the initial address to a virtual address space of the application process layer by layer through an operating system of the virtual machine to obtain a target address; and reading the image frame data from the shared memory area based on the target address, and displaying the image frame data on the target application.

This disclosure describes approaches for securing memory among non-secure / secure processing environments such as in a TrustZone-M processor architecture. An example method of controlling memory access includes: configuring a memory locking service in a computing device having a secure processing environment and a non-secure processing environment, and executing the memory locking service in the secure processing environment; receiving a request with the memory locking service to lock a specified memory region of the computing device, with the specified memory region being associated with the non-secure processing environment; associating the specified memory region with the secure processing environment (e.g., by using a Security Attribution Unit to upgrade the region to secure memory); subsequently, identifying an access attempt to the specified memory region, with the access attempt being received from the non-secure processing environment; and controlling the access attempt to the specified memory region, based on a policy.

A storage system, a data processing method, an apparatus, a node, and a storage medium, where a client determines an address that is in a storage unit and that is used to store to-be-written data, and sends the to-be-written data to a first storage device that is in a storage node and that is corresponding to the storage unit. The first storage device stores the to-be-written data without the storage node determining a hard disk LBA corresponding to virtual address space, and without a hard disk determining a corresponding physical address based on the hard disk LBA.

The invention provides a data processing method and system, and the method comprises the steps: responding to an access request carrying a target resource identifier, and querying a virtual address mapping relation corresponding to the target resource identifier; under the condition that the virtual address mapping relationship is not queried, determining a target resource type according to the target resource identifier, and determining an allocated target virtual address from a logic memory pool corresponding to the target resource type, the logic memory pool being obtained by performing resource type division in a virtual address space; a target memory allocation interface is called, a target resource corresponding to the target resource identifier is loaded to a target physical memory, a mapping relation between the target physical memory and an allocated target virtual address is established, a virtual address handle corresponding to the target virtual address is generated, and the target memory allocation interface integrates memory allocation interfaces of all host platforms; accessing the target resource according to the virtual address handle; through the design of virtualization and abstract interfaces, the cross-platform performance consistency can be ensured, and the development complexity can be reduced.

The application is suitable for the technical field of processors, and particularly relates to a random generation method and system of address mapping relationship and related equipment. The method comprises the following steps: establishing a virtual address space, a guest physical address space and a real physical address space; randomly allocating address segments to the virtual address space, the guest physical address space and the real physical address space according to an address start position and an address segment length of external parameters; obtaining a paging mode configuration of a current computer system, and constraining the virtual address space and the guest physical address space according to the paging mode configuration; establishing a random mapping relationship among the virtual address space, the guest physical address space and the real physical address space according to the paging mode configuration, and obtaining an address mapping result. Compared with the prior art, the application can quickly and randomly generate a one-level or two-level address mapping relationship without constructing a complete set of page tables on the basis of meeting the paging rules defined in the RISC-V specification.

The invention provides a plug-in installation method and device, equipment, a medium and a program product, and relates to the technical field of computers. The method comprises the steps that M specified plug-in dynamic libraries are mapped to a virtual address space of an application program process based on a preloading mechanism, each plug-in dynamic library comprises a plug-in context, and the plug-in context comprises a dependency relationship between a plug-in associated with a plug-in context object symbol name and other plug-ins; in response to a pre-initialization request for the M plug-in dynamic libraries, pre-initializing the M plug-in dynamic libraries according to M respective plug-in context object symbol names and dependency relationships between plug-ins associated with the respective plug-in context object symbol names and other plug-ins; and in response to respective pre-initialization of the M plug-in dynamic libraries and in response to the application program to execute initialization of the plug-in system, initializing the M pre-initialized plug-in dynamic libraries according to the dependency relationship between the plug-in and other plug-ins.

The invention provides an address space management method and a secure container, and relates to the technical field of computers.The method comprises the steps that a two-stage address translation page table EPT corresponding to at least one LibOS process in at least one container instance is constructed; each EPT is used for representing a mapping relation between a user physical address corresponding to each LibOS process and a real physical address so as to construct a mutually isolated virtual address space between different LibOS processes; and based on the VMFUNC instruction, switching the EPT corresponding to the current LibOS process in a user mode so as to switch to the EPT corresponding to the target LibOS process. According to the method, security isolation of multiple LibOS process address spaces can be realized; meanwhile, address space view switching is completed in a user mode by using a VMFUNC instruction, high-performance overhead brought by VM-Exit and system calling is completely avoided, and extremely-low-delay and high-efficiency process and instance switching is achieved.

Embodiments of the present disclosure relate to a method, apparatus, device and medium for processing map data. The method is applied to an operating system and includes: receiving a data reading request; obtaining map metadata and spatial index data, and determining target flattened map shard data corresponding to a target data item to be accessed and position information to be accessed of the target data item in the target flattened map shard data according to positioning information, map metadata and spatial index data, or according to a current frame and map metadata; determining a target virtual address space mapped by the target flattened map shard data; obtaining an offset dictionary, and determining a virtual address of the target data item according to the offset dictionary, the target virtual address space and the position information to be accessed; and reading data corresponding in a page cache based on the virtual address of the target data item. Embodiments of the present disclosure implement single-level memory management, the memory occupied by the map during operation is safe and controllable, and the efficiency of map data access is improved.