122 results about "Virtual address space" patented technology

The embodiments of the present disclosure provide data processing methods, a computer system, a computer-readable storage medium and a computer program product. A data processing method comprises: acquiring a first control command transmitted by a second service program, and determining a physical address region; applying for a virtual address region from a second virtual address space to which a service data storage region is mapped, and on the basis of the virtual address region, generating a second control command; and establishing a mapping relationship between the virtual address region and the physical address region for a first service program to access the physical address region on the basis of the virtual address region in the second control command acquired from a control command storage region. The technical solution provided in the embodiments of the present disclosure realizes high-speed data transmission between service programs.

The invention discloses a zero-copy data transmission method and device, a medium and a product, and belongs to the technical field of data transmission, and the method comprises the steps that an application program requests a memory buffer area from a kernel module; the kernel module allocates a physical memory buffer area according to the request, and returns a specially designed descriptor (including a handle corresponding to an address pointer); the application program submits a descriptor to the kernel module and requests an address pointer of the memory buffer area; after the kernel module verifies the descriptor, the physical memory buffer area is mapped to a virtual address space of the application program, and a corresponding address pointer is returned; the application program writes data needing to be sent according to the address pointer, and after writing is completed, the descriptor is submitted to the kernel module and the written data is requested to be sent; after the kernel module verifies the descriptor, a DMA controller is configured and started, and the written data is directly read from the physical memory buffer area and pushed to a network card to be sent. According to the invention, the security and certainty can be improved while the transmission performance is ensured.

The invention relates to a memory management method and device applied to a server-free data center, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: in response to a virtual memory application instruction, performing virtual memory allocation in a local computing resource pool to obtain a virtual address space; in response to the virtual address access instruction, acquiring cache information of the computing resource pool, and triggering missing page interruption under the condition that data corresponding to the virtual address is not hit in the cache information; the cache information comprises locally cached cache data and page table information; acquiring physical memory resources in a memory resource pool according to the virtual address and the page table information under the condition of triggering missing page interruption of the anonymous page; and updating the page table information and the cache information according to the physical memory resources. By adopting the method, the processing delay of the data center can be reduced while the decoupled memory management logic is used for improving the resource utilization rate.

The invention relates to an electric power mobile application security protection method based on a swan gap microkernel, which comprises the following steps of: S1, establishing a hardware trust root, and storing a device root key and a certificate chain by utilizing a non-tampering storage area built in a chip; s2, establishing a complete trusted boot chain based on a hardware root of trust, and verifying the integrity and credibility of the next layer by each layer from Bootloader to a swan microkernel and then to an application program; s3, constructing a triple authentication system based on user identity, equipment identity and biological characteristics, and performing user authentication; s4, according to a user authentication result, realizing fine-grained authority control based on an RBAC model and ABAC, and ensuring that authority check can be executed during resource access every time by utilizing an IPC security mechanism of a swan micro kernel; and S5, creating an independent execution environment for each power application according to the process isolation capability of the swan microkernel, and ensuring that memories among the applications cannot be mutually accessed through virtual address space isolation. The reliability of power mobile application safety protection is effectively improved.

The invention relates to the technical field of data acquisition, and discloses a PCIe-based DMA data zero copy processing method and system. The method is applied to a zero copy processing system, and comprises a HOST module for distributing a physical DMA buffer area and mapping a physical address of the DMA buffer area to a logically continuous virtual address space; the HOST module is used for constructing a preset descriptor queue and sending a head address of the queue to the FPGA module; the FPGA module receives the initial address of the queue through a PCIe interface, analyzes a descriptor, and writes DMA data with a preset transmission length into a sub DMA buffer area of the HOST module; and the HOST module monitors the state of the DMA buffer area and adopts a dynamic flow control mechanism to adjust the data transmission rate of the FPGA module according to the state. According to the method provided by the embodiment of the invention, the physical DMA buffer area is mapped to the logically continuous virtual address space, and the application program can directly access the DMA data in the user space without copying through the middle of a kernel, so that zero-copy access is realized, the data processing delay is reduced, and the data transmission efficiency is improved.

The invention provides a unified memory system based on heterogeneous computing, belongs to the field of parallel computing and artificial intelligence, and realizes memory sharing by constructing a global virtual address space and eliminating explicit data transmission between a host end and an equipment end. The core module comprises: 1) a cache consistency manager, which adopts an adaptive protocol (write broadcast / write invalidation) and a cache directory table (CCDT) to ensure data consistency; 2) an MMU memory management unit which supports dynamic address translation, on-demand distribution and page migration; and 3) an intelligent data migration unit which dynamically migrates the hotspot data to a near-end memory based on the prediction model and reduces the access delay. The architecture is suitable for edge AI applications with high requirements on real-time performance and energy efficiency.

The invention relates to a video memory management method and device, electronic equipment, a storage medium and a program product. The method comprises the steps that a target user memory context corresponding to a target user process is created, and the target user memory context is used for managing a target virtual address space corresponding to the target user process and a target video memory space corresponding to the target user process; for at least two pieces of GPU firmware used for executing a task of the target user process, virtual address subspaces in the target virtual address space are distributed to the at least two pieces of GPU firmware; and for any one of the at least two pieces of GPU firmware, the GPU firmware updates the page table information of the firmware memory context corresponding to the GPU firmware according to the page table information of the target user memory context and the virtual address subspace corresponding to the GPU firmware.

The invention provides an intelligent grading and excess subscription management system and method for a GPU video memory, and relates to the technical field of GPU video memory management, and the method comprises the steps: firstly building a grading storage system comprising a first performance region and a second performance region; then receiving a video memory allocation request containing task priority and service quality requirements, and monitoring a data access mode and access frequency; the initial placement position of the data block is dynamically determined through the intelligent engine according to the task priority, the data access mode and the frequency; predicting target access probability distribution of each data block by adopting an LSTM network; then migrating data between the first performance area and the second performance area through a swap-in and swap-out mechanism based on the distribution and periodicity characteristics, and ensuring the service quality of the first performance area; finally, the global oversale proportion is dynamically adjusted through an overpurchase safety management module, an independent virtual address space is distributed for each task, and safe overpurchase can be achieved through the process.

The invention relates to the technical field of computer system structures, in particular to a unified memory and data transmission system and management method for an FPGA heterogeneous platform, and the system comprises a CPU component which is used for detecting and initializing an FPGA component, constructing a globally unified virtual address space view, managing a global page table, maintaining a mapping table, managing PCIe communication and processing exceptions; the FPGA component is used for PCIe DMA data transmission, conversion from a virtual address to a physical address, striped on-chip storage and storage of user acceleration function logic implementation; and the PCIe bus is used for data transmission of the CPU component and the FPGA component. Physical memory resources of the CPU component and the FPGA component are integrated and dynamically mapped to a unified virtual address space in a software and hardware cooperation mode, a simple, safe and flexible unified memory system and management method are provided, and efficient memory management and data transmission between the CPU and the FPGA are achieved.

The invention provides an address management method and device for a heterogeneous system and computer equipment, and relates to the technical field of computers, in particular to the fields of data processing, data transmission and the like. According to the implementation scheme, a second virtual address space of a data transmission module is divided into second sub-virtual address spaces with the same number as that of data processing modules, and the size of the second sub-virtual address spaces is the same as that of first virtual address spaces of the data processing modules; distributing a unique identifier to the data processing module, wherein the unique identifier is a natural number; for the first virtual address space, the first virtual address space is offset by a preset offset through the unique identifier, so that a second sub-virtual address space corresponding to the first virtual address space is determined in the second sub-virtual address space, and the preset offset is a product of the unique identifier and the size of the first virtual address space; and establishing a mapping relationship between the first virtual address space and the corresponding second sub-virtual address space.

The invention discloses an AI model reasoning method and device and related equipment, and relates to the technical field of artificial intelligence. The AI model and the obtained input data are used for iterative reasoning, a reasoning result is obtained, a processing module in the AI model corresponds to a first physical storage area indicated by the first virtual address space, and the first physical storage area is used for storing KV generated by the processing module in the iterative reasoning process. And when the first physical storage area is not enough to continue to store KV generated by the processing module executing data processing in the Nth reasoning process, allocating a second physical storage area indicated by a second virtual address space to the processing module to store the KV. Wherein the second virtual address space is continuous with the first virtual address space. Thus, the KV generated by the processing module is stored in a mode of allocating the physical storage area according to needs, the utilization rate of the physical storage area can be improved, and operators in the processing module do not need to have the capacity of splicing the KV in a virtual address space.

Methods and systems are provided for allocating memory. An example method includes: allocating, for an application logic, a region of external primary memory included in a memory appliance; selecting, by a client device in response to a first request to reclaim a first portion of local primary memory in the client device, a portion of external primary memory from the region of external primary memory; copying data from the first portion of local primary memory to the portion of external primary memory; and converting a portion of a first virtual address space at the client device by remapping at least one virtual address in the first virtual address space at the client device from the first portion of local primary memory to the portion of external primary memory.

The invention relates to the technical field of computers, in particular to a data transmission method and device, electronic equipment and a storage medium, and is used for improving camera data transmission efficiency in a cross-system environment. The method is applied to the electronic equipment comprising a host machine, the host machine is used for creating and running a virtual machine through a virtualization engine, and operating systems are different. The method comprises the following steps: in response to an image acquisition request initiated by a target application in a virtual machine, creating a shared memory area through a host machine; calling an image acquisition device through a host machine to obtain image frame data, and storing the image frame data in a shared memory area; mapping a physical address of the image frame data in the shared memory region into an initial address visible to a virtual machine through a virtualization engine; mapping the initial address to a virtual address space of the application process layer by layer through an operating system of the virtual machine to obtain a target address; and reading the image frame data from the shared memory area based on the target address, and displaying the image frame data on the target application.

This disclosure describes approaches for securing memory among non-secure / secure processing environments such as in a TrustZone-M processor architecture. An example method of controlling memory access includes: configuring a memory locking service in a computing device having a secure processing environment and a non-secure processing environment, and executing the memory locking service in the secure processing environment; receiving a request with the memory locking service to lock a specified memory region of the computing device, with the specified memory region being associated with the non-secure processing environment; associating the specified memory region with the secure processing environment (e.g., by using a Security Attribution Unit to upgrade the region to secure memory); subsequently, identifying an access attempt to the specified memory region, with the access attempt being received from the non-secure processing environment; and controlling the access attempt to the specified memory region, based on a policy.

A storage system, a data processing method, an apparatus, a node, and a storage medium, where a client determines an address that is in a storage unit and that is used to store to-be-written data, and sends the to-be-written data to a first storage device that is in a storage node and that is corresponding to the storage unit. The first storage device stores the to-be-written data without the storage node determining a hard disk LBA corresponding to virtual address space, and without a hard disk determining a corresponding physical address based on the hard disk LBA.

The invention provides a data processing method and system, and the method comprises the steps: responding to an access request carrying a target resource identifier, and querying a virtual address mapping relation corresponding to the target resource identifier; under the condition that the virtual address mapping relationship is not queried, determining a target resource type according to the target resource identifier, and determining an allocated target virtual address from a logic memory pool corresponding to the target resource type, the logic memory pool being obtained by performing resource type division in a virtual address space; a target memory allocation interface is called, a target resource corresponding to the target resource identifier is loaded to a target physical memory, a mapping relation between the target physical memory and an allocated target virtual address is established, a virtual address handle corresponding to the target virtual address is generated, and the target memory allocation interface integrates memory allocation interfaces of all host platforms; accessing the target resource according to the virtual address handle; through the design of virtualization and abstract interfaces, the cross-platform performance consistency can be ensured, and the development complexity can be reduced.

The application is suitable for the technical field of processors, and particularly relates to a random generation method and system of address mapping relationship and related equipment. The method comprises the following steps: establishing a virtual address space, a guest physical address space and a real physical address space; randomly allocating address segments to the virtual address space, the guest physical address space and the real physical address space according to an address start position and an address segment length of external parameters; obtaining a paging mode configuration of a current computer system, and constraining the virtual address space and the guest physical address space according to the paging mode configuration; establishing a random mapping relationship among the virtual address space, the guest physical address space and the real physical address space according to the paging mode configuration, and obtaining an address mapping result. Compared with the prior art, the application can quickly and randomly generate a one-level or two-level address mapping relationship without constructing a complete set of page tables on the basis of meeting the paging rules defined in the RISC-V specification.

The invention provides a plug-in installation method and device, equipment, a medium and a program product, and relates to the technical field of computers. The method comprises the steps that M specified plug-in dynamic libraries are mapped to a virtual address space of an application program process based on a preloading mechanism, each plug-in dynamic library comprises a plug-in context, and the plug-in context comprises a dependency relationship between a plug-in associated with a plug-in context object symbol name and other plug-ins; in response to a pre-initialization request for the M plug-in dynamic libraries, pre-initializing the M plug-in dynamic libraries according to M respective plug-in context object symbol names and dependency relationships between plug-ins associated with the respective plug-in context object symbol names and other plug-ins; and in response to respective pre-initialization of the M plug-in dynamic libraries and in response to the application program to execute initialization of the plug-in system, initializing the M pre-initialized plug-in dynamic libraries according to the dependency relationship between the plug-in and other plug-ins.

The invention provides an address space management method and a secure container, and relates to the technical field of computers.The method comprises the steps that a two-stage address translation page table EPT corresponding to at least one LibOS process in at least one container instance is constructed; each EPT is used for representing a mapping relation between a user physical address corresponding to each LibOS process and a real physical address so as to construct a mutually isolated virtual address space between different LibOS processes; and based on the VMFUNC instruction, switching the EPT corresponding to the current LibOS process in a user mode so as to switch to the EPT corresponding to the target LibOS process. According to the method, security isolation of multiple LibOS process address spaces can be realized; meanwhile, address space view switching is completed in a user mode by using a VMFUNC instruction, high-performance overhead brought by VM-Exit and system calling is completely avoided, and extremely-low-delay and high-efficiency process and instance switching is achieved.

The embodiment of the invention provides a memory mapping method and device of a QXL display device, equipment and a medium, the method simulates the QXL display device on a virtual machine, the virtual machine is deployed with a mirror image file corresponding to a kernel source code of a Linux system, the kernel source code comprises a driving source code, and the driving source code comprises a first driving source code and a second driving source code. Driving the source code to obtain an initial address and a size of a physical memory area of the QXL display equipment; the method comprises the following steps: for an ARM64 architecture, mapping a physical memory area of a QXL display device to a target virtual address space of a Linux kernel by using an input / output cache remapping interface of the Linux kernel; and the input / output cache remapping interface is used for mapping a physical memory area of the QXL display equipment according to the memory alignment requirement of the ARM64 architecture. According to the embodiment of the invention, additional secondary data copying can be avoided, and the problem of system crash or abnormal behaviors caused by misalignment of the virtual equipment under the ARM64 architecture can be prevented.

Embodiments of the present specification provide a data processing method and system, the method comprising: a reasoning framework, in response to a cold start instruction sent by a cloud platform, cold starting on a target graphics processor, sending an opening hijacking command to a hijacking module, and during the process of loading first model weights of a first reasoning model, initiating a video memory application to the target graphics processor; the hijacking module, in response to the opening hijacking command, hijacking the video memory application, and redirecting the video memory application to a first virtual address in a fixed virtual address space; the reasoning framework, in a case where it is determined that the first model weights are completed loading, sending an ending hijacking command to the hijacking module, and based on the first model weights in the first virtual address, constructing a first reasoning execution graph to execute a first reasoning task using the first reasoning execution graph. By hijacking the CUDA video memory allocation and redirecting it to a pre-reserved fixed address, the address of the model weights is ensured to be persistent and stable, so that the CUDA Graph continues to be effective in multiple loadings and hot switching.

This application discloses a method for managing dynamic libraries, applicable to a computer system. The method includes: requesting at least one huge page memory for an application program marked as in huge page mode; mapping the dynamic libraries that the application program relies on to the virtual address space corresponding to the at least one huge page memory; and loading the dynamic libraries into the at least one huge page memory when the application program is running. The solution provided in an embodiment of the application, using huge page memory to load dynamic libraries, can improve the hit rate of TLB queries.

The invention relates to a method, a computing device, a computer readable storage medium and a computer program product for direct remote memory access of a graphics processor. The method comprises the following steps: respectively obtaining page granularity of a to-be-communicated source equipment memory and a to-be-communicated target equipment memory; in response to the determined page granularity of the predetermined size of at least one unaligned PCIE in the source equipment memory and the target equipment memory, constructing a virtual address space mapped with a physical address space with the page granularity of the predetermined size based on the physical address space of the unaligned memories of the equipment, the mapped virtual address space meets the requirements of the PCIE page table; and based on the constructed virtual address space, performing communication between memories of the source device and the target device in a direct remote memory access mode. According to the invention, an additional physical memory aligned with the memory page does not need to be configured as an intermediate cache, the memory calling operation can be simplified, and the transmission delay is remarkably reduced.

The present application discloses a method for processing duplicate images in memory, which includes: generating a second process of the application based on a first process of the running application, where the second process has the same virtual address space and memory object reference relationship as the first process; extracting a list of image objects in the memory of the running application in the second process based on the memory object reference relationship; determining duplicate images in the list of image objects in the second process and the virtual addresses of the duplicate images in the virtual address space; obtaining the virtual addresses of the duplicate images by the first process; and modifying the memory object reference relationship of the first process based on the virtual addresses of the duplicate images obtained by the first process so that the virtual addresses of the duplicate images in the first process merge to reference the same object in the memory. The present application also discloses an electronic device and a storage medium.

A migration method includes: downgrading, by a source node, a physical page in a local memory corresponding to a process to a physical page of a compute express link (CXL) memory pool having a first physical address; reconstructing, by a target node, a first virtual address space as a second virtual address space; determining, by the target node, a second physical address of the physical page in the CXL memory pool; and mapping, by the target node, the second physical address to the second virtual address space, wherein the CXL memory pool is shared by the source node and the target node, the first physical address is based on a physical address encoding rule of the source node, and the second physical address is based on a physical address encoding rule of the target node.

This application discloses a data processing method, apparatus, computer device, and computer-readable storage medium. By performing memory mapping processing on a first file based on a target process, a mapped region of the first file in the virtual address space of the target process is obtained. The first file contains first target data and storage space-related data associated with the first target data. In response to a first data access instruction, the storage space-related data in the first file is obtained based on the mapped region. A first data object is generated based on the storage space-related data. Based on the first data object and the storage space-related data encapsulated in the first data object, a portion of the first target data in the first file is obtained. Responding to the first data access instruction based on the portion of the first target data allows the first data object generated in the target process to contain a small amount of storage space-related data, rather than all the data in the first file, thus reducing data usage in memory.

The application provides a memory performance test method and device, a microprocessor architecture and a storage medium, and is applied to the technical field of computers. After obtaining a memory mapping request of a user state program, the method obtains target page table attributes associated with a target file descriptor carried by the memory mapping request and allocates target physical memory. Then, the method configures page table entries of a memory page table according to the target page table attributes, establishes address mapping between the target physical memory and a virtual address space in the memory page table, and finally feeds back address information of the virtual address space to the user state program, so that the user state program performs memory testing based on the obtained address information. The file descriptor is associated with target page table attributes preconfigured by the user state program. By initiating a memory mapping request carrying different file descriptors, virtual address spaces mapped according to different page table attributes can be obtained, the test process is greatly simplified, the flexibility of the test process is improved, and the test efficiency is improved.

The invention relates to the technical field of heterogeneous environment task migration, and particularly provides a heterogeneous environment task migration method and system and a medium. According to the method, a uniform data layout and a virtual address space structure are constructed to unify state representation modes among different instruction set architectures; the extensible executable file is expanded on the basis of a fat binary file, and a symbol table is split into a basic symbol table shared across instruction set architectures and an independent extended symbol table of each instruction set architecture; and executing task migration across the instruction set architecture by the runtime environment in combination with the basic symbol table and the extended symbol table based on the migration points and the trigger pages embedded in the construction process. According to the method, the mobility, the cross-platform compatibility and the system analyzability are balanced, and systematic support is provided for task migration in a heterogeneous environment.

The present disclosure provides a Mixture-of-Experts model based collective communication method, system and device. The collective communication method is applied to a communication receiving end, and includes: receiving a data write-in instruction, where the data write-in instruction includes to-be-processed data and first address information; accessing a virtual expert address in a pre-created virtual address space according to the first address information; applying for a corresponding actual physical space for the virtual expert address based on a size of the to-be-processed data; and writing the to-be-processed data into the actual physical space.

The present application relates to a method for direct remote memory access of a graphics processor, a computing device, a computer readable storage medium and a computer program product. The method comprises: obtaining page granularity of source device memory and target device memory to be communicated respectively; in response to determining that at least one of the source device memory and the target device memory is not aligned to a predetermined size page granularity of PCIE, constructing a virtual address space mapped to a physical address space of the device unaligned memory at the predetermined size page granularity, so that the mapped virtual address space meets the requirements of a PCIE page table; and communicating between the memories of the source device and the target device in a direct remote memory access manner based on the constructed virtual address space. The present application can avoid configuring additional memory page aligned physical memory as an intermediate cache, and can simplify memory call operations, and significantly reduce transmission delay.