74 results about "Virtual address space" patented technology

The invention relates to a memory management method and device applied to a server-free data center, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: in response to a virtual memory application instruction, performing virtual memory allocation in a local computing resource pool to obtain a virtual address space; in response to the virtual address access instruction, acquiring cache information of the computing resource pool, and triggering missing page interruption under the condition that data corresponding to the virtual address is not hit in the cache information; the cache information comprises locally cached cache data and page table information; acquiring physical memory resources in a memory resource pool according to the virtual address and the page table information under the condition of triggering missing page interruption of the anonymous page; and updating the page table information and the cache information according to the physical memory resources. By adopting the method, the processing delay of the data center can be reduced while the decoupled memory management logic is used for improving the resource utilization rate.

The invention relates to an electric power mobile application security protection method based on a swan gap microkernel, which comprises the following steps of: S1, establishing a hardware trust root, and storing a device root key and a certificate chain by utilizing a non-tampering storage area built in a chip; s2, establishing a complete trusted boot chain based on a hardware root of trust, and verifying the integrity and credibility of the next layer by each layer from Bootloader to a swan microkernel and then to an application program; s3, constructing a triple authentication system based on user identity, equipment identity and biological characteristics, and performing user authentication; s4, according to a user authentication result, realizing fine-grained authority control based on an RBAC model and ABAC, and ensuring that authority check can be executed during resource access every time by utilizing an IPC security mechanism of a swan micro kernel; and S5, creating an independent execution environment for each power application according to the process isolation capability of the swan microkernel, and ensuring that memories among the applications cannot be mutually accessed through virtual address space isolation. The reliability of power mobile application safety protection is effectively improved.

The invention provides an intelligent grading and excess subscription management system and method for a GPU video memory, and relates to the technical field of GPU video memory management, and the method comprises the steps: firstly building a grading storage system comprising a first performance region and a second performance region; then receiving a video memory allocation request containing task priority and service quality requirements, and monitoring a data access mode and access frequency; the initial placement position of the data block is dynamically determined through the intelligent engine according to the task priority, the data access mode and the frequency; predicting target access probability distribution of each data block by adopting an LSTM network; then migrating data between the first performance area and the second performance area through a swap-in and swap-out mechanism based on the distribution and periodicity characteristics, and ensuring the service quality of the first performance area; finally, the global oversale proportion is dynamically adjusted through an overpurchase safety management module, an independent virtual address space is distributed for each task, and safe overpurchase can be achieved through the process.

Methods and systems are provided for allocating memory. An example method includes: allocating, for an application logic, a region of external primary memory included in a memory appliance; selecting, by a client device in response to a first request to reclaim a first portion of local primary memory in the client device, a portion of external primary memory from the region of external primary memory; copying data from the first portion of local primary memory to the portion of external primary memory; and converting a portion of a first virtual address space at the client device by remapping at least one virtual address in the first virtual address space at the client device from the first portion of local primary memory to the portion of external primary memory.

The invention relates to the technical field of computers, in particular to a data transmission method and device, electronic equipment and a storage medium, and is used for improving camera data transmission efficiency in a cross-system environment. The method is applied to the electronic equipment comprising a host machine, the host machine is used for creating and running a virtual machine through a virtualization engine, and operating systems are different. The method comprises the following steps: in response to an image acquisition request initiated by a target application in a virtual machine, creating a shared memory area through a host machine; calling an image acquisition device through a host machine to obtain image frame data, and storing the image frame data in a shared memory area; mapping a physical address of the image frame data in the shared memory region into an initial address visible to a virtual machine through a virtualization engine; mapping the initial address to a virtual address space of the application process layer by layer through an operating system of the virtual machine to obtain a target address; and reading the image frame data from the shared memory area based on the target address, and displaying the image frame data on the target application.

This disclosure describes approaches for securing memory among non-secure / secure processing environments such as in a TrustZone-M processor architecture. An example method of controlling memory access includes: configuring a memory locking service in a computing device having a secure processing environment and a non-secure processing environment, and executing the memory locking service in the secure processing environment; receiving a request with the memory locking service to lock a specified memory region of the computing device, with the specified memory region being associated with the non-secure processing environment; associating the specified memory region with the secure processing environment (e.g., by using a Security Attribution Unit to upgrade the region to secure memory); subsequently, identifying an access attempt to the specified memory region, with the access attempt being received from the non-secure processing environment; and controlling the access attempt to the specified memory region, based on a policy.

The invention provides a data processing method and system, and the method comprises the steps: responding to an access request carrying a target resource identifier, and querying a virtual address mapping relation corresponding to the target resource identifier; under the condition that the virtual address mapping relationship is not queried, determining a target resource type according to the target resource identifier, and determining an allocated target virtual address from a logic memory pool corresponding to the target resource type, the logic memory pool being obtained by performing resource type division in a virtual address space; a target memory allocation interface is called, a target resource corresponding to the target resource identifier is loaded to a target physical memory, a mapping relation between the target physical memory and an allocated target virtual address is established, a virtual address handle corresponding to the target virtual address is generated, and the target memory allocation interface integrates memory allocation interfaces of all host platforms; accessing the target resource according to the virtual address handle; through the design of virtualization and abstract interfaces, the cross-platform performance consistency can be ensured, and the development complexity can be reduced.

The application is suitable for the technical field of processors, and particularly relates to a random generation method and system of address mapping relationship and related equipment. The method comprises the following steps: establishing a virtual address space, a guest physical address space and a real physical address space; randomly allocating address segments to the virtual address space, the guest physical address space and the real physical address space according to an address start position and an address segment length of external parameters; obtaining a paging mode configuration of a current computer system, and constraining the virtual address space and the guest physical address space according to the paging mode configuration; establishing a random mapping relationship among the virtual address space, the guest physical address space and the real physical address space according to the paging mode configuration, and obtaining an address mapping result. Compared with the prior art, the application can quickly and randomly generate a one-level or two-level address mapping relationship without constructing a complete set of page tables on the basis of meeting the paging rules defined in the RISC-V specification.

The invention provides a plug-in installation method and device, equipment, a medium and a program product, and relates to the technical field of computers. The method comprises the steps that M specified plug-in dynamic libraries are mapped to a virtual address space of an application program process based on a preloading mechanism, each plug-in dynamic library comprises a plug-in context, and the plug-in context comprises a dependency relationship between a plug-in associated with a plug-in context object symbol name and other plug-ins; in response to a pre-initialization request for the M plug-in dynamic libraries, pre-initializing the M plug-in dynamic libraries according to M respective plug-in context object symbol names and dependency relationships between plug-ins associated with the respective plug-in context object symbol names and other plug-ins; and in response to respective pre-initialization of the M plug-in dynamic libraries and in response to the application program to execute initialization of the plug-in system, initializing the M pre-initialized plug-in dynamic libraries according to the dependency relationship between the plug-in and other plug-ins.

The invention provides an address space management method and a secure container, and relates to the technical field of computers.The method comprises the steps that a two-stage address translation page table EPT corresponding to at least one LibOS process in at least one container instance is constructed; each EPT is used for representing a mapping relation between a user physical address corresponding to each LibOS process and a real physical address so as to construct a mutually isolated virtual address space between different LibOS processes; and based on the VMFUNC instruction, switching the EPT corresponding to the current LibOS process in a user mode so as to switch to the EPT corresponding to the target LibOS process. According to the method, security isolation of multiple LibOS process address spaces can be realized; meanwhile, address space view switching is completed in a user mode by using a VMFUNC instruction, high-performance overhead brought by VM-Exit and system calling is completely avoided, and extremely-low-delay and high-efficiency process and instance switching is achieved.

Embodiments of the present specification provide a data processing method and system, the method comprising: a reasoning framework, in response to a cold start instruction sent by a cloud platform, cold starting on a target graphics processor, sending an opening hijacking command to a hijacking module, and during the process of loading first model weights of a first reasoning model, initiating a video memory application to the target graphics processor; the hijacking module, in response to the opening hijacking command, hijacking the video memory application, and redirecting the video memory application to a first virtual address in a fixed virtual address space; the reasoning framework, in a case where it is determined that the first model weights are completed loading, sending an ending hijacking command to the hijacking module, and based on the first model weights in the first virtual address, constructing a first reasoning execution graph to execute a first reasoning task using the first reasoning execution graph. By hijacking the CUDA video memory allocation and redirecting it to a pre-reserved fixed address, the address of the model weights is ensured to be persistent and stable, so that the CUDA Graph continues to be effective in multiple loadings and hot switching.

The invention relates to a method, a computing device, a computer readable storage medium and a computer program product for direct remote memory access of a graphics processor. The method comprises the following steps: respectively obtaining page granularity of a to-be-communicated source equipment memory and a to-be-communicated target equipment memory; in response to the determined page granularity of the predetermined size of at least one unaligned PCIE in the source equipment memory and the target equipment memory, constructing a virtual address space mapped with a physical address space with the page granularity of the predetermined size based on the physical address space of the unaligned memories of the equipment, the mapped virtual address space meets the requirements of the PCIE page table; and based on the constructed virtual address space, performing communication between memories of the source device and the target device in a direct remote memory access mode. According to the invention, an additional physical memory aligned with the memory page does not need to be configured as an intermediate cache, the memory calling operation can be simplified, and the transmission delay is remarkably reduced.

A migration method includes: downgrading, by a source node, a physical page in a local memory corresponding to a process to a physical page of a compute express link (CXL) memory pool having a first physical address; reconstructing, by a target node, a first virtual address space as a second virtual address space; determining, by the target node, a second physical address of the physical page in the CXL memory pool; and mapping, by the target node, the second physical address to the second virtual address space, wherein the CXL memory pool is shared by the source node and the target node, the first physical address is based on a physical address encoding rule of the source node, and the second physical address is based on a physical address encoding rule of the target node.

This application discloses a data processing method, apparatus, computer device, and computer-readable storage medium. By performing memory mapping processing on a first file based on a target process, a mapped region of the first file in the virtual address space of the target process is obtained. The first file contains first target data and storage space-related data associated with the first target data. In response to a first data access instruction, the storage space-related data in the first file is obtained based on the mapped region. A first data object is generated based on the storage space-related data. Based on the first data object and the storage space-related data encapsulated in the first data object, a portion of the first target data in the first file is obtained. Responding to the first data access instruction based on the portion of the first target data allows the first data object generated in the target process to contain a small amount of storage space-related data, rather than all the data in the first file, thus reducing data usage in memory.

The application provides a memory performance test method and device, a microprocessor architecture and a storage medium, and is applied to the technical field of computers. After obtaining a memory mapping request of a user state program, the method obtains target page table attributes associated with a target file descriptor carried by the memory mapping request and allocates target physical memory. Then, the method configures page table entries of a memory page table according to the target page table attributes, establishes address mapping between the target physical memory and a virtual address space in the memory page table, and finally feeds back address information of the virtual address space to the user state program, so that the user state program performs memory testing based on the obtained address information. The file descriptor is associated with target page table attributes preconfigured by the user state program. By initiating a memory mapping request carrying different file descriptors, virtual address spaces mapped according to different page table attributes can be obtained, the test process is greatly simplified, the flexibility of the test process is improved, and the test efficiency is improved.

The invention relates to the technical field of heterogeneous environment task migration, and particularly provides a heterogeneous environment task migration method and system and a medium. According to the method, a uniform data layout and a virtual address space structure are constructed to unify state representation modes among different instruction set architectures; the extensible executable file is expanded on the basis of a fat binary file, and a symbol table is split into a basic symbol table shared across instruction set architectures and an independent extended symbol table of each instruction set architecture; and executing task migration across the instruction set architecture by the runtime environment in combination with the basic symbol table and the extended symbol table based on the migration points and the trigger pages embedded in the construction process. According to the method, the mobility, the cross-platform compatibility and the system analyzability are balanced, and systematic support is provided for task migration in a heterogeneous environment.

The present disclosure provides a Mixture-of-Experts model based collective communication method, system and device. The collective communication method is applied to a communication receiving end, and includes: receiving a data write-in instruction, where the data write-in instruction includes to-be-processed data and first address information; accessing a virtual expert address in a pre-created virtual address space according to the first address information; applying for a corresponding actual physical space for the virtual expert address based on a size of the to-be-processed data; and writing the to-be-processed data into the actual physical space.

The present application relates to a method for direct remote memory access of a graphics processor, a computing device, a computer readable storage medium and a computer program product. The method comprises: obtaining page granularity of source device memory and target device memory to be communicated respectively; in response to determining that at least one of the source device memory and the target device memory is not aligned to a predetermined size page granularity of PCIE, constructing a virtual address space mapped to a physical address space of the device unaligned memory at the predetermined size page granularity, so that the mapped virtual address space meets the requirements of a PCIE page table; and communicating between the memories of the source device and the target device in a direct remote memory access manner based on the constructed virtual address space. The present application can avoid configuring additional memory page aligned physical memory as an intermediate cache, and can simplify memory call operations, and significantly reduce transmission delay.

The invention relates to the technical field of embedded systems and automatic software generation, in particular to a heterogeneous single-chip microcomputer drive code automatic system and method based on an RISC-V instruction set, and the method comprises the following steps: receiving and analyzing an IP-XACT or JSON format peripheral description file provided by a hardware team; the method comprises the following steps: respectively calling a special parser to process different file formats, accurately extracting register address mapping, bit field definition, clock domain configuration, interrupt number and DMA channel information, constructing a tree-shaped peripheral data model of a cross-heterogeneous SoC, accurately mapping a physical address of a register to an RISC-V virtual address space, defining an interrupt trigger type and a DMA transmission direction, and establishing a tree-shaped peripheral data model of the cross-heterogeneous SoC; a unique hardware identifier is distributed to each peripheral; according to the method, the drive generation intelligence level of the heterogeneous RISC-V single-chip microcomputer can be comprehensively improved, and the key technical bottlenecks that multi-format peripheral description analysis is difficult, high-frequency data transmission is interrupted and lost, DMA configuration is complex and the like are solved.

According to examples, a compressed memory dump apparatus generates one or more compressed dump files from a virtual address space (VAS) of a target process. Memory regions identified from the VAS are grouped into memory buckets so that a memory bucket includes respective memory regions. Parallel threads are spawned to execute parallel dumping operations. The parallel dumping operations include reading the memory regions, compressing the memory buckets to generate compressed chunks, and writing the compressed chunks to the dump files. A compressed memory dump parser module can be used to retrieve the original memory content from the compressed dump files.

A computing system including two or more processing units shares virtual memory for a program between the two or more processing units. Each of the processing units may include memory management circuitry to manage a respective page table corresponding to the virtual memory. A first portion of the addresses of the virtual address space of the program are mapped to addresses of physical memory associated with a first one of the two or more processing units, while a second portion of the addresses of the virtual address space are mapped to addresses in physical memory associated with a second one of the two or more processing units.

The invention relates to an end-to-end multi-core data direct connection method based on RDMA (Remote Direct Memory Access), which comprises the following steps: 1) an equipment enumeration step: identifying and acquiring type information and a physical DMA memory of each heterogeneous chip; 2) a chip memory binding and virtual mapping step: binding a DMA memory with a file descriptor, and constructing a unified virtual address space to realize cross-chip memory pooling management; (3) a data direct connection step: binding a file descriptor with an RDMA memory registration object, establishing an end-to-end data transmission channel, and finishing high-speed data transmission under the condition of no CPU (Central Processing Unit) participation; and 4) a resource release step: uniformly recovering equipment resources and updating state information after the task is completed. By taking the data processing unit as a core, the unified memory view is constructed, and cross-chip RDMA straight-through transmission is realized, so that CPU intervention and host memory overhead are remarkably reduced, and the overall performance of the system is improved.

The invention relates to the technical field of image processing, and discloses a cell image storage method, device and equipment and a storage medium, and the method comprises the steps: creating an image storage file on external storage equipment; creating a memory mapping object of the image storage file; mapping the image storage file to a virtual address space of the process through the memory mapping object to obtain a pointer pointing to the virtual address space; in the process of collecting the cell images, the cell images are stored in the image storage file through the pointer. The problem that the storage speed is low when the cell image is stored in the hard disk can be solved.

In a system including a processing unit and a set of one or more stacked memory chips, the processing unit can request data. When the data is distributed such that there is at least one non-contiguous memory sector in the smallest unit of memory segments usable by the system, then a gather operation can be utilized to instruct the set of one or more stacked memory chips to gather the requested data into a virtual address space, e.g., a gather accelerated address space. The requested data can be aligned to the byte chunk size used by the processing unit and at least some of the unneeded memory segments can be skipped, e.g., not copied into the virtual address space. The requested data in the virtual address space can be communicated to the processing unit using less bandwidth resources than when not using the gather operation.

A method of managing access to a physical memory formed of n memory page frames using a set of virtual address spaces having n virtual address spaces each formed of a plurality p of contiguous memory pages. The method includes receiving a write request to write a block of data to a virtual address within a virtual address space i of the n virtual address spaces, the virtual address defined by the virtual address space i, a memory page j within that virtual address space i and an offset from the start of that memory page j; translating the virtual address to an address of the physical memory using a virtual memory table having n by p entries specifying mappings between memory pages of the virtual address spaces and memory page frames of the physical memory, wherein the physical memory address is defined by: (i) the memory page frame mapped to the memory page j as specified by the virtual memory table, and (ii) the offset of the virtual address; and writing the block of data to the physical memory address.

The invention provides an external device memory access method, a memory access system and an electronic device. The external device memory access method is applied to a central processing unit (CPU), and the CPU is connected with at least one PCIE device. The CPU comprises a virtual address space; the processor accesses the memory of the PCIE equipment through the physical memory address of the PCIE equipment mapped by the virtual address; the method comprises the following steps: receiving an operation instruction for operating the memory of the PCIE equipment; determining a mapping relation between the operation address and the virtual address in the virtual address space based on a preset function, and executing the operation instruction; the preset function is used for configuring a mapping relation between the operation address and the virtual address in the virtual address space under the condition that the virtual address space does not comprise the operation address. According to the method, the CPU can access all memories of the large-memory PCIE equipment.

The invention provides a page table query method of a memory management unit and a related device, which are applied to a to-be-queried page table between a virtual address space and a physical address space, and the method comprises the following steps: obtaining a query request comprising a target virtual address; determining a query index corresponding to the query request according to the partial data of the target virtual address and a physical address corresponding to the to-be-queried page table; and querying the to-be-queried page table based on the query index so as to determine a target physical address corresponding to the target virtual address. According to the page table query method and device, the query index is determined according to the partial data of the target virtual address and the physical address corresponding to the to-be-queried page table, so that repeated query and redundant entries caused by alias can be reduced or even eliminated, the page table query efficiency is improved, meanwhile, the query index is associated with the physical address corresponding to the to-be-queried page table, and the query efficiency is improved. In this way, the hit rate in the query process is increased, memory access delay is further reduced, and therefore the overall performance of the memory management unit is remarkably improved.

Apparatuses, systems, and techniques to allocate portions of a virtual address space to allow virtual machines to share data. In at least one embodiment, at least a portion of a virtual memory address space is made accessible to multiple virtual machines and is mapped to memory addresses of different physical devices using, at least in part, a cache-coherent protocol.

The embodiment of the invention provides a large-page memory processing method and device, a storage medium and a program product. In the large-page memory processing method, a mechanism for actively mapping a large page of a code segment is introduced into a missing page processing flow executed by a kernel. Based on the mechanism, after a kernel determines a target virtual page with page missing abnormity, if a target interval which corresponds to the target virtual page and meets a large page alignment condition is located in a virtual address space of a code segment and has a continuous available physical memory matched with the size of the large page, the target virtual page is subjected to page missing abnormity; if yes, the kernel allocates a large-page physical memory matched with the large-page size in the direct physical memory. The kernel can reconstruct the large-page mapping relation of the target area according to the large-page physical memory before returning to the user mode. On the basis, a large page mapping mechanism is moved forward from background asynchronous scanning to a link of actually accessing a code segment, so that the code segment can obtain large page mapping as soon as possible in a key access path, and the hit rate and instruction access efficiency of the iTLB are greatly improved.

Techniques are disclosed relating to access control for threads executed by a computer processor. Processor circuitry may include an execution pipeline, a base register and a limit register. The base register and the limit register may define a range of virtual addresses for a thread executed by the execution pipeline. Control circuitry may access a translation table that stores translation entries that map a virtual address space to a physical address space, wherein a given entry includes a thread-private state indication. for a virtual address provided by the thread at a first permission level, the control circuitry may: determine that the thread-private state indication of a corresponding entry of the translation table is set and in response to the determination, provide a translation of the virtual address only if the virtual address falls within the range of virtual addresses.