15 results about "Context switch" patented technology

Embodiments of the present disclosure provide a data read / write method, system, and apparatus, a computing device, and a storage medium. The data read / write method comprises: receiving, by means of an asynchronous I / O layer, a data read / write request sent from a user space, and storing the data read / write request in a request queue; when the asynchronous I / O layer determines that the data read / write request is of a pass-through type, sending the data read / write request to a driver layer; and parsing the data read / write request by means of the driver layer, and sending request information of the data read / write request to a target processing end device for read / write processing. The data read / write request sent from the user space is received by means of the asynchronous I / O layer, and is sent to the driver layer after the data read / write request is determined to be of the pass-through type, thereby reducing context switching and data copying overhead, and improving the processing efficiency of I / O operations. The request is parsed at the driver layer and sent to the processing end device for read / write processing, thereby optimizing the scheduling of I / O tasks, reducing disk addressing time and I / O latency, and improving overall performance and system stability.

The computing device includes a processor and a context switcher. The context switcher includes a data structure module for storing a context, which includes the starting address of a thread and values ​​associated with that thread. In an idle state, the processor loads a first context for a first thread from the corresponding data structure module in synchronization with a first cycle of a clock signal. In an active state, the processor processes the first thread according to the first context. Furthermore, in an active state, the processor provides a second context for a second thread to the context switcher. This second thread follows and will be processed in parallel with the first thread. The second context is stored in a subsequent data structure module within the context switcher's data structure module, which corresponds to a subsequent processor for processing the second thread.

The application discloses a kind of based on the write optimization scheduling method of key-value storage system of coroutine, task scheduler and key-value storage system, by encapsulating write request as coroutine task, avoid operating system kernel context switching storm;Second, by introducing the queue state perception scheduling strategy for three queues, efficient overlap of processor execution phase and disk execution phase is realized, the resource utilization of processor and disk is significantly improved, and the scheduling strategy is according to the order of I / O task completion queue priority highest, post task queue second, write request queue lowest, so that the key processing path after disk persistence completion can be executed preferentially, and the next batch of write request is awakened in time, so as to reduce the overall waiting time of write request and system write delay;Third, the completion state is detected by independent I / O polling task, instead of using interrupt or callback mode, avoid the kernel state and user state switching overhead caused by interrupt processing.

This invention provides a persistent context cache storage method, apparatus, device, system, and medium, aiming to leverage SSDs to address the limitations of GPU memory and the low read / write efficiency of traditional offloading schemes in long context inference. The system constructs an asynchronous zero-copy read / write pipeline with a bypass kernel, aggregates physical SSDs into a unified logical storage pool, and loads the master snapshot object to restore historical indexes for fast startup. Based on this, the system implements concurrency control and read-priority scheduling for mixed loads through a native context cache concurrency control mechanism and a read-first read / write scheduler, prioritizing read requests and accelerating the inference process. A shadow object snapshot persistence mechanism periodically persists context cache metadata, ensuring the persistence and reusability of context cache data. This invention eliminates context switching and file system overhead in traditional offloading schemes, improves SSD bandwidth utilization, and reduces inference latency for large language models.

The invention belongs to the technical field of large-scale deep learning model training, and particularly relates to a video memory scheduling system based on dynamic sequence length assembly line parallel training. The system comprises a dynamic recalculation module, a video memory arrangement and prefetching module and a mapping reconstruction module, the system collects the length and load information of each micro-batch before each round of iteration, establishes an optimization model with the goal of minimizing the iteration time, dynamically generates a re-calculation plan, and realizes inter-stage video memory load balancing; by introducing a collating stream and an asynchronous scheduler outside a main computing stream, overlapping execution of video memory collating and computing prefetching is realized, and the influence of fragment collating on training performance is reduced; a dynamic physical block mapping strategy is designed based on a CUDA virtual memory management mechanism, the physical block granularity is adaptively adjusted according to the idle state of the video memory, and the API calling and context switching overhead is reduced. Experimental results show that the video memory utilization rate and the system stability are remarkably improved, and an efficient video memory scheduling scheme is provided for large model training.

The application relates to the technical field of computers and discloses a GPU computing resource scheduling method and device and a storage medium, and adaptive regulation and control of time slice intervals are realized by constructing a multi-dimensional evaluation model chain; first, task computing density and display memory requirements are used to generate task computing characteristic coefficients; performance efficiency coefficients are output in combination with task average response time and preemption overhead proportion; then, ready queue length and context switching frequency are fused to generate a load synergy factor under the constraints of task characteristics and performance coefficients; meanwhile, hardware health coefficients are evaluated based on hardware temperature and cache hit rate changes; and finally, the optimal time slice interval is dynamically calculated through an interval decision model according to the load synergy factor and the hardware health coefficient. The application solves the problem that fixed time slice scheduling cannot adapt to dynamic changes of mixed workloads, and realizes the collaborative optimization of resource utilization, task response speed and system stability.

The present application relates to a kind of lightweight distributed task scheduling systems, lightweight distributed task scheduling system for embedded device is based on distributed equipment and sensing unit, through the distributed communication soft bus technology, realize the fast networking authentication, connection, data sharing capability between equipment;Distributed task scheduling technology is used to realize equipment state perception, task evaluation, task allocation migration and load balancing capability;At the same time, for the single-thread model of embedded resource limited equipment design, simplify concurrent programming model, avoid lock competition, reduce context switching overhead, and through task priority scheduling, cost evaluation model and load balancing management, realize the reasonable allocation of task between distributed equipment and the reasonable use of resources.Solve the problem of resource limitation and collaborative scheduling difficulty between distributed cluster embedded devices, realize the fast sharing of data between embedded devices and the management and resource scheduling capability of distributed equipment, realize the stability improvement and resource utilization improvement of distributed system.

A system call method and device, the method comprising: a kernel of a first virtual machine receiving an interrupt instruction of a first process, the first process running in a user space of a second virtual machine, the kernel of the first virtual machine running in a kernel space of the second virtual machine, the second virtual machine being configured to provide a running environment of the first virtual machine, at this time, a CPU switching from a user state to a kernel state; the kernel of the first virtual machine mapping a first address associated with the interrupt instruction to a second address, the kernel of the first virtual machine executing the interrupt instruction based on the second address, obtaining an interrupt processing result, and sending the interrupt processing result to the first process, at this time, the CPU switching from the kernel state to the user state. Therefore, in the process of the first virtual machine calling the system, the CPU only needs to switch between the kernel state and the user state twice, thereby reducing the privilege level overhead, the context switching overhead, and the resource consumption of the CPU.

This invention relates to the field of communication protocol optimization technology, specifically to a communication method and system for LED devices based on protocol stack optimization, comprising the following steps: a physical layer data frame acquisition module, a protocol path intelligent decision-making module, a cross-layer instruction direct mapping module, and a dynamic stack parameter optimization module. In this invention, the physical layer data frame acquisition module acquires the raw signal bitstream and converts it into physical layer data frames. The protocol path intelligent decision-making module determines and triggers zero-copy processing logic based on the protocol type identifier, blocking network interruption requests. The cross-layer instruction direct mapping module directly writes the payload data segment to the target video memory address through a memory mapping mechanism, significantly reducing the context switching latency and CPU load caused by data unpacking. Simultaneously, the dynamic stack parameter optimization module adjusts the sliding window size parameter according to the communication quality evaluation matrix, effectively solving the timing jitter problem existing in traditional protocol stacks when processing high-frequency LED control instructions.

This invention relates to the field of cloud computing resource management technology and discloses an AI-based dynamic scheduling and operation and maintenance system for large-scale data center computing resources. The system includes a kernel status monitoring module, a scheduling priority quantification module, a resource configuration retrieval module, and a synchronous clock scheduling execution module. It collects the system call trajectory of the task to be scheduled in the kernel state and the synchronous blocking state of the network protocol stack, extracts runtime characteristic data representing the execution phase, and calculates the scheduling urgency index by combining the topological weights of the task's directed acyclic graph. Then, it matches the target control group quota and writes the target control group quota into the resource limit parameter file when the task enters the communication waiting window. This invention locks the resource quota update action within the task's logical rest period, effectively eliminating the kernel state context switching overhead caused by computing power scheduling, ensuring the logical clock consistency of large-scale parallel computing tasks, and improving the global turnover efficiency of the resource pool.

This invention discloses a global register activity analysis and context switching optimization method for atomic task flows, belonging to the fields of embedded system software optimization, compiler backend technology, and real-time operating system kernel design. The method first transforms the directed acyclic graph describing the task execution logic into a linear execution sequence, and then calculates the active interval (the time span from generation to last use) of each data variable by traversing this sequence. Subsequently, using a zero-copy register forwarding algorithm, by detecting data dependencies between adjacent tasks, physical register safety gaps, and interface alignment conditions, the physical registers carrying the data are locked and redundant memory loading instructions are eliminated during the code generation stage. Finally, by calculating the intersection of the set of registers actually modified by the task flow and the set of registers saved by the callers according to the target architecture ABI specification, a minimum context switching set (Cmin) code is dynamically generated, saving only the necessary registers.

A method and apparatus for mitigating row hammer attacks is provided. A row hammer alert is generated by a component of a memory architecture controlling operation of a memory device. The component may be a memory controller, coherency logic, or data fabric. The component obtains a physical address of an aggressor row that caused the alert and obtains an identifier of an execution context corresponding to the physical address. The component generates an error message for a processing device, the error message including the identifier of the execution context. The processing device retrieves the error message when performing a context switch. The processing device then generates an event received by the operating system. The operating system then takes action to reduce row hammer by the execution context, such as ending, restarting, or throttling the execution context.

This application discloses a fine-grained cooperative preemption method and medium for multi-tasking GPUs. The method may include: determining the category of preemption schemes for thread blocks, including exhaustion, context switching, and flushing; collecting information on all thread blocks in the stream processor to be preempted, and constructing a first cost function for the stream processor; determining and classifying the available preemption schemes for each thread block; calculating the throughput overhead and latency overhead of each thread block under the available preemption schemes, and then calculating the corresponding second cost function; and determining the preemption scheme for each thread block with the goal of minimizing the stream processor's cost function. This invention can solve the high preemption overhead problem of stream processor task switching, and achieve efficient stream processor preemption and task resource adjustment in multi-tasking GPUs.