227 results about "Context switch" patented technology

The embodiment of the invention provides a data read-write method, system and device, computing equipment and a storage medium, and the data read-write method comprises the following steps: receiving a data read-write request sent by a user mode through an asynchronous I / O layer, and storing the data read-write request into a request queue; under the condition that the asynchronous I / O layer determines that the data read-write request is of a straight-through type, the data read-write request is sent to a driving layer; and analyzing the data read-write request through the driving layer, and sending request information of the data read-write request to target processing end equipment for read-write processing. The asynchronous I / O layer receives the data read-write request sent by the user mode and sends the data read-write request to the driving layer after the data read-write request is determined to be of the straight-through type, context switching and data copying expenses are reduced, the processing efficiency of I / O operation is improved, the request is analyzed in the driving layer and sent to the processing end equipment for read-write processing, scheduling of I / O tasks is optimized, and the user experience is improved. The disk addressing time and I / O delay are reduced, and the overall performance and the system stability are improved.

The invention provides an NPU instruction level context switching method and device, and relates to the technical field of data processing.The method comprises the steps that when a context switching instruction is received, a non-refresh instruction is forbidden, it is waited for completion of an instruction being executed, and context data is stored in a main storage module; after completion, recovering the context switching related instruction of the NPU module, and executing the target task; and after the target task is executed, recovering the context data to the NPU module, and recovering the execution of the non-refresh instruction. According to the method, optimization is carried out aiming at the problem that an existing NPU architecture generally can only support limited preemption at an algorithm boundary or a specific context switching point and even cannot preemption, so that a high-priority task must wait for a low-priority task to be completed, and remarkable priority inversion and / or key inversion are / is caused. A full-stack solution from a system on chip to an instruction set architecture and then to an operating system kernel is provided, and preemption of an NPU instruction level is achieved.

The invention discloses a real time operating system (RTOS) multi-task priority scheduling and real-time control method based on advanced RISC machines (ARM), and relates to the technical field of embedded computing and control. Comprising the following steps: S1, time slice management setting: dividing CPU time according to a preset time period to obtain time slices; s2, performing task scheduling: setting each task according to a task control block, and performing context switching and priority arbitration through an OSScheduler () function; and S3, performing exception response: performing forced interruption and exception recovery operation through a set multi-stage exception classification mechanism. Through a three-level decision model and a partition response mechanism, it can be ensured that a high-priority task can be responded in time within strict time constraints, the hard real-time requirement is met, meanwhile, CPU time is divided through a fixed time slice, a counter is updated through timer interruption, and therefore the time deviation of task execution can be reduced, and the task execution efficiency is improved. And the certainty of the system is improved.

Systems and methods provide for inherited access permissions, thereby facilitating read and write access by called contexts. Hardware logic may enforce access permissions in the system. When a processor core executes code associated with a first context, the processor core generates a first hardware signal identifying the first context. The processor core may then switch from the first context to the second context due to the first context calling the second context. The processor core may then generate a second hardware signal identifying the calling (first) context, and then the first hardware signal identifies the called (second) context. The hardware logic that enforces the access permissions may then determine that the second context is being called and that the second context includes either direct access permissions or inherited access permissions associated with the calling (first) context.

A method and related systems for dynamically adjusting on-device configurations for models based on detected context switches is disclosed. The system can use an on-device language model to determine context parameters in a first mode and then uses the context parameters to determine prediction models or prediction model parameters to use for inputs provided in a second mode.

The invention relates to the technical field of message pushing, in particular to an SaaS (Software as a Service) intelligent concurrent pushing system which comprises a tenant flow monitoring module, a resource binding module, a lock-free object writing module, a handle layout construction module and a cache prefetching delivery module. According to the method, the high-frequency business object is identified by monitoring the flow characteristics of the tenants, and the complete Slab page is dynamically applied and bound to the thread exclusive local allocation buffer area, so that physical isolation of bottom layer resources is realized to eliminate global lock competition and context switching overhead in a multi-thread environment; lock-free memory writing is executed based on a privatized pointer, the object construction efficiency is greatly improved, a compact storage structure in which a bitmap is adjacent to a connection handle is constructed, a hardware cache prefetching mechanism is triggered by utilizing bitmap reading, connection data is loaded to a CPU cache line in advance, and the connection data is stored in the cache line. And the cache miss rate is reduced and the concurrent delivery performance of massive messages is remarkably improved by utilizing a memory locality principle.

Systems and methods for efficient context switching in multithread processors are disclosed. A processing system comprises a direct memory access module configured to detect a preemption request generated by the scheduling circuit. Responsive to the preemption request, the direct memory access module determines whether execution of a first task from a plurality of tasks needs to be replaced by execution of a second task. When the replacement is necessitated, the module saves a first plurality of registers associated with the first task at a memory location transmitted by the scheduling circuit and queues the second task for execution. The memory location is transmitted by the scheduling circuit as part of the preemption request.

The invention relates to a user mode interruption processing method and device, equipment and a program product. Through the interrupt information carried by the user mode interrupt request, the operating system can quickly and accurately determine the source and the processing path of the target user mode interrupt in numerous possible interrupt situations. Meanwhile, the context switching time in the interrupt processing process can be effectively shortened by obtaining the current process and the current stack frame thereof, matching the current process and the current stack frame thereof with the target process and determining a mechanism of the target stack frame in combination with the interrupt address information, so that the context switching time in the interrupt processing process can be effectively shortened when the interrupt occurs. The target stack frame can be quickly determined to provide an accurate execution environment recovery basis for subsequent switching between the kernel mode and the user mode and execution of the interrupt service program, and the interrupt processing speed can be increased by switching the kernel mode to the user mode to run the interrupt service program of the user mode. And the overall performance and resource utilization rate of the operating system are improved.

The invention provides a file system client kernel mode and user mode communication method based on asynchronous communication. According to the asynchronous communication-based file system client kernel mode and user mode communication method provided by the embodiment of the invention, the context switching overhead of communication between the user mode and the kernel mode can be reduced, the data transmission throughput is improved, the resource utilization rate is optimized through dynamic queue management, and the problem of performance bottleneck in a high-concurrency scene is effectively solved.

A device includes a parallel processor and a context switch scheduling circuit that is part of or separate from the parallel processor. The parallel processor is configured to execute requests from a plurality of virtual functions. The context switch scheduling circuit is configured to, responsive to a first virtual function of the plurality of virtual functions becoming idle during a first time slice at the parallel processor, perform a context switch for a second virtual function of the plurality of virtual functions before expiration of the first time slice, and assign a second time slice at the parallel processor to the second virtual function.

The invention discloses a data zero-copy processing method and system based on an eBPF zero-trust gateway, and belongs to the technical field of computer network security. According to the method, an XDP program is loaded on a network card driving layer, and an AFXDP technology is combined to construct a kernel mode and user mode shared memory pool UMEM; when an original message arrives, an eBPF unit mounted by an XDP program intercepts the message in real time, a tunnel packaging space is reserved in situ in an original memory, and if the head space is insufficient, a new memory page is logically mapped from a UMEM standby buffer pool to achieve extension. Identity fingerprints are generated by extracting message feature vectors, load in-situ encryption is completed in cooperation with a kernel kTLS module, and data are prevented from being returned to a user mode for processing. According to the method, multiple copying and context switching of a kernel-user mode of a traditional SSL VPN are eliminated, the throughput is improved by 2-3 times, the delay is reduced to the microsecond level, the CPU utilization rate is reduced by 40% or above, application layer DDoS attacks are effectively defended, and the method is suitable for 5G edge computing and cloud native zero-trust gateway scenes.

The invention discloses a multi-core scheduling system and method based on interrupt affinity and a storage medium. The technical problem that data locality guarantee and load balancing are difficult to consider at the same time is solved by constructing a self-adaptive optimization closed loop of perception-decision-execution-feedback, and the method comprises the steps that a routing interruption configuration mechanism provides a basis for dynamic adjustment; an interrupt guide task placement mechanism ensures that an interrupt service program and an associated task are executed in the same CPU core, and the cache hit rate is increased; the execution overhead of an interrupt service program is brought into core load statistics through task context switching and a'task + ISR 'two-dimensional precise load evaluation mechanism triggered by ISR inlet / outlet double nodes, and real load awareness is achieved; a load-driven dynamic interrupt routing mechanism is combined with dual control of a hysteresis threshold and cooling time, so that a ping-pong effect is avoided. According to the method, dynamic load balancing is realized on the premise of keeping data locality, and the real-time response performance and throughput of the multi-core system are remarkably improved.

The invention discloses an RISC-V context switching optimization method and device and a medium, and belongs to the technical field of processors. The method comprises the steps of executing a current task based on the computing core; when a context switching operation is triggered, determining the residual space of the register stack based on the numerical value of the stack top register; judging whether the register stack can store the current task or not based on the residual space and the current task; if not, storing the current task based on the memory; if yes, storing the current task based on the register stack; and executing a replacement task based on the computing core, and switching back to the current task through the stack top register when the replacement task is completed. According to the method, the effect of improving the context switching speed in the RISC-V is achieved.

An elastic request handling technique limits a number of threads used to service input / output (I / O) requests of a low-latency I / O workload received by a file system server executing on a cluster having a plurality of nodes deployed in a virtualization environment. The limited number of threads (server threads) is constantly maintained as “active” and running on virtual central processing units (vCPUs) of a node. The file system server spawns and organizes the active server threads as one or more pools of threads. The server prioritizes the low-latency I / O requests by loading them onto the active threads and allowing the requests to run on those active threads to completion, thereby obviating overhead associated with lock contention and vCPU migration after a context switch (i.e., to avoid rescheduling a thread on a different vCPU after execution of the thread was suspended).

The invention discloses an instruction conversion context switching optimization method based on stack frame hierarchical compression, which comprises the following steps of: loading and executing an executable file in a dynamic instruction conversion mode, and establishing a storage instruction set and a recovery instruction set containing a context switching complete process for context switching related instructions; constructing a register group according to the association degree of registers in the storage instruction set so as to realize the combined storage of register data by adopting a continuous memory space in the ARM architecture, and carrying out hierarchical compression on push data according to a function call hierarchical structure, recovery of the register data and the stack pressing data is achieved in the recovery instruction set according to the mapping relation table and the incidence relation table recorded in the storage process, the flexibility of processing a complex nested structure and a data type is improved, and correct execution of a program is ensured.

Systems and methods are described to address shortcomings in a conventional conversation system via a novel technique utilizing artificial neural networks to train the conversation system whether or not to continue context. In some aspects, an interactive media guidance application determines a type of conversation continuity in a natural language conversation comprising first and second queries. The interactive media guidance application determines a first token in the first query and a second token in the second query. The interactive media guidance application identifies entity data for the first and second tokens. The interactive media guidance application retrieves, from a knowledge graph, graph connections between the entity data for the first and second tokens. The interactive media guidance application applies this data as inputs to an artificial neural network. The interactive media guidance application determines an output that indicates the type of conversation continuity between the first and second queries.

Systems, methods, and apparatuses for reducing context switches in a virtualized computing environment are provided herein. An example method comprises executing a supervisor, executing a first virtual machine on the supervisor, detecting a first exit from the first virtual machine, responsive to detecting the first exit, loading a userspace context without loading a supervisor context, executing a second virtual machine on the supervisor, detecting a second exit from the second virtual machine, and responsive to detecting the second exit, loading the supervisor context.

The invention provides a dynamic binary translation optimization method and system based on regional granularity. The method comprises the following steps: S1, initializing a program entry; s2, acquiring and analyzing an instruction; s3, performing cache query; s4, hot spot judgment; s5, performing interpretive execution; s6, initiating a compiling request; s7, compiling mode selection; s8, compiling and caching the code blocks; s9, skipping to a local code for execution; and S10, returning to the main cycle. According to the invention, the technical problems of limited optimization space, high context switching overhead and high code expansion rate are solved.

The invention discloses an intelligent storage integrated memory storage architecture. The intelligent storage integrated memory storage architecture comprises a computing type memory semantic solid state disk which is used for providing a unified memory address space based on a computing expression link protocol and supporting a host to perform byte granularity access through a loading / storage instruction; an internal intelligent layering and granularity management mechanism is arranged; a flexible data placement mechanism capable of perceiving semantics is set; the host operating system is connected with the computing type memory semantic solid state disk and is used for receiving the long-delay prompt sent by the computing type memory semantic solid state disk and carrying out context switching; and a uniform abstract interface layer is arranged, and is used for uniformly managing byte granularity memory access to the computing type memory semantic solid state disk and transmission of data placement semantic prompts, and submitting a task unloading request to the embedded computing engine. By means of the mode, the problem of multi-impedance mismatch of traditional hierarchical storage in performance, cost, energy efficiency and intelligent processing can be solved.

The invention relates to an efficient execution optimization method for an embedded operating system based on an MIPS instruction set, and belongs to the field of computer operating systems. The method comprises the following measures: improving the parallelism of instructions: maximizing the parallel execution of the instructions through the intelligent analysis and dynamic scheduling strategy of an operating system; enhancing branch prediction capability: based on process and thread affinity, adding an intelligent scheduling strategy, cache consistency optimization and affinity strategy dynamic adjustment; the context switching efficiency is optimized; and through an improved context switching mechanism, the overhead during task switching of the operating system is reduced. According to the method, the instruction parallelism is enhanced, so that the processor can more efficiently execute a plurality of instructions; the branch prediction accuracy is improved, and the performance loss caused by wrong prediction is reduced; by improving the context switching efficiency, the overhead during task switching is reduced. These measures collectively ensure smoother computing and more efficient management.

The embodiment of the invention provides a virtual processor context switching method and device, a storage medium and electronic device.The method comprises the steps that under the condition that a current virtual processor receives an interrupt signal, the affinity attribute of a current task executed on the current virtual processor is determined; under the condition that the affinity attribute represents that the virtual processor associated with the current task is the first virtual processor, predicting the switching probability of the current task; under the condition that the switching probability is greater than or equal to a preset probability threshold value, pre-caching context information of the first virtual processor in a cache region; when a context switching request is received, the current task is interrupted, the context information of the first virtual processor is extracted from the cache region and loaded to the first virtual processor, and the interrupted current task continues to be executed on the first virtual processor. And the problem of low virtualization real-time performance is solved.

The invention discloses a data transmission method based on a multi-thread IPC message channel, which relates to the technical field of data transmission and comprises the following steps of: selecting an IPC mechanism according to application requirements, defining a message format, creating an IPC object and setting corresponding access authority and attributes; an IPC object is initialized, and a plurality of threads are created based on task requirements. According to the data transmission method based on the multi-thread IPC message channel, by optimizing thread management and resource utilization, the performance and the response speed of a system are remarkably improved, threads in a thread pool can be reused, the complexity of thread life cycle management is reduced, in addition, by reasonably configuring the size of the thread pool and dynamically adjusting the number of the threads according to the system load, the data transmission efficiency is improved, and the service life of the system is prolonged. And meanwhile, context switching overhead caused by too many threads is avoided, and an efficient management mechanism of resources enables the system to respond to external requests more quickly and process data, so that faster response time and higher throughput are provided.

The invention discloses a thread scheduling method, electronic equipment, a storage medium and a program product, and relates to the technical field of computers, security check is performed on a source thread and a target thread through a thread switching request initiated by the source thread, an allocatable time period of the source thread allocated to the target thread is calculated according to a security detection result, and the allocatable time period of the source thread allocated to the target thread is sent to the electronic equipment. Bypassing a processing mechanism of a completely fair scheduler, updating the virtual running time of a source thread, distributing an allocable time period to a target thread, calling a context switching function to execute thread switching operation on the source thread and the target thread, and synchronously updating the virtual running time of the target thread when the target thread consumes the allocable time period. According to the thread scheduling method and device, the problem that in the related technology, when a complete fair scheduler processes high-frequency and collaborative thread tasks, due to the indirect handover mechanism and fair scheduling characteristics of the complete fair scheduler, the delay of thread scheduling is improved is solved, and the delay of thread scheduling is reduced.

The invention discloses a network traffic storage pre-filtering method and device. The method comprises the following steps: configuring a traffic filtering rule; acquiring an initial network flow; filtering the network traffic by using a traffic filtering rule to obtain filtered network traffic information; performing application identification filtering processing on the filtered network flow information to obtain effective network flow information; updating a traffic filtering rule by using the effective network traffic information; and performing classified storage processing on the effective network flow information based on the application type information of the effective network flow information. According to the method, the network traffic is directly filtered in the kernel mode by using the eBPF, so that data replication and context switching are avoided, and the filtering efficiency is improved. According to the method, the change of the network environment can be monitored in real time, and the filtering rule is dynamically adjusted according to the change, so that the accuracy and the flexibility of the filtering effect are ensured.

The embodiment of the invention provides a task scheduling and notification method and device, a storage medium and a program product. In the embodiment of the invention, at least part of asynchronous operation instructions with the incidence relation in the target task are divided into the same group, and during the execution period of the asynchronous operation instructions in the same group, a task scheduler schedules and executes other tasks. Under the condition that all the asynchronous operation instructions in the same group are executed, the task scheduler controls the target task to enter a scheduling waiting state so as to wait to be scheduled again, and then under the condition that the target task is scheduled, task context switching is carried out so that the target task can be switched back to continue to be executed; compared with a scheme that task context switching is triggered once after each asynchronous operation instruction is completed, the task context switching frequency can be reduced by performing task context switching under the condition that the asynchronous operation instructions in the same group are completely executed by taking the group as a unit, and the task execution performance is improved on the whole.

The invention relates to the technical field of lock scheduling prediction, in particular to a lock scheduling condition-based lock strategy adjustment method and a terminal, and the method comprises the steps of obtaining historically collected system operation data which comprises lock scheduling data, system load data and system scheduling overhead data; training a machine learning model according to the historically collected system operation data; predicting the contention degree of the lock in real time according to the trained machine learning model to obtain a prediction result; adjusting a scheduling strategy of the lock according to the prediction result; according to the technical scheme, the contention degree of the lock can be intelligently predicted, then the lock strategy is dynamically adjusted, the balance between high performance and fairness is achieved, the optimization of the lock scheduling strategy is achieved, unnecessary spinning and context switching can be reduced, the CPU use efficiency is improved, and therefore the overall stability and response capacity of the system are improved.

An apparatus comprises: pipeline 202 for processing instructions comprising decoder circuitry 210; extension processing circuitry 204 (threadlet extension) to perform delegated tasks asynchronously to

The present application relates to a context switching verification method and apparatus. The apparatus comprises: an excitation generation module generates an excitation signal according to a verification requirement for a module under test, and sends same to a reference model module and the module under test, the excitation signal being used for indicating a command sequence which needs to be processed and comprises at least one command under test; the module under test processes each command under test according to the excitation signal, sends at a preset processing node a target signal to the reference model module, and sends to a response inspection module first data generated during the command processing process; the reference model module processes each command under test according to the excitation signal and the target signal, and sends to the response inspection module second data generated during the processing command process; and the response inspection module verifies, according to the first data and the second data, the capability of the module under test executing a context switching command. The present application can automatically and accurately compare data and behaviors during context switching, thereby achieving context switching capability verification.

Methods, apparatus, and computer programs are disclosed for context switching. In some embodiments, a method comprises dedicating a first subset of a plurality of vector registers to a first thread of a plurality of threads for thread execution; and responsive to a context switch from the first thread to a second thread, bypassing saving a state of the first subset of the plurality of vector registers; and saving a state of a second subset of the plurality of vector registers, wherein the second subset of the plurality of vector registers is not dedicated to the first thread, and wherein the first and second subsets are mutually exclusive.

The invention discloses an RTOS inert processor context switching method, and relates to the technical field of electric digital data processing. According to the RTOS inert processor context switching method provided by the invention, task analysis is carried out in a software mode, special hardware does not need to be used for supporting, and the chip size and hardware resource overhead can be reduced. Moreover, the inert context switching logic is added in the context switching function of the real-time operating system to read the content of the second array and realize the dynamic conversion of storage and recovery operations, so that the defect when no hardware support exists can be overcome, and the system performance is improved.