64 results about "Bit stuffing" patented technology

A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8 / 10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices.

A protocol may enable support of the USB 2.0 LPM (Link Power Management) Addendum by a ULPI PHY (Universal Serial Bus Transceiver Macrocell Low-Pin Interface Physical Layer Device), facilitating transmitting the reserved PID (Physical Interface Device) token, used in the LPM Extended Transaction, through a ULPI bus. Bits [3:0] of a ULPI Tx Cmd (Transmit Command) byte may be reused, with the value of those bits being 4′b0 for a transmission (normally indicating a No PID transmission), by configuring the ULPI PHY to qualify the selected four Tx Cmd bits (bits [3:0] of the Tx Cmd) with the Opmode code. The ULPI PHY may thereby interpret bits [3:0] of the Tx Cmd byte based on the value of the Opmode, and may not transmit the Extended PID when the Opmode is set to 2′b10, that is, when the Opmode is indicative of bit-stuffing and NRZI encoding being disabled, for example during a Chirp transmission. When the Opmode code is set to 2′b0, indicative of normal bit-stuffing, and the Tx Cmd bits [3:0] are set to 4′b0 during a transmission (Tx Cmd bits[7:6]=2′b01), then the PHY may transmit the Extended PID, followed by the rest of the extended transaction onto a USB.

The present invention discloses a method and an arrangement providing transmission of data through a node, e.g. a switch, having different input and output line interfaces in a wide range of data speed, without introducing any loss of bits, but still maintaining the nominal bit rate. This is achieved by means of a very simple and flexible implementation. At the receiving side of the switch, one extra bit per frame is transferred over the time slot bus of the switch if the number of bits in the corresponding FIFO of the input line exceeds a predefined upper limit. In contrast, one bit less per frame is transferred if the number of bits in the corresponding FIFO of the input line goes below a predefined lower limit. At the transmitting side of the switch, a FLL circuit regulates the data rate out of the FIFOs. The FLL circuit is implemented as a P-regulator having i.a. the fill degree of the FIFO as a direct input. Consequently, excellent jitter and frequency stability are achieved, and because of not using an I-component, the FLL circuit becomes stable.