43 results about "Plesiochronous digital hierarchy" patented technology

The invention refers to a method of transmitting Ethernet data frames from a first local area network (LAN) to a second local area network (LAN) comprising mapping Ethernet frames from the first local area network onto Plesiochronous Digital Hierarchy format via Generic Framing Procedure (GFP) and transmitting the mapped Ethernet frames via a one or multiple En streams to an optional SDH-level network. The transmission is received at the second local area network through the optional SDH-level network via one or multiple En streams-network, and the Ethernet frames are demapped from the first local area network via Generic Framing Procedure, and transmitted into the second local area network.

The invention discloses convergent type Ethernet over plesiochronous digital hierarchy (EoPDH) network bridge equipment and a data transmission method thereof. The transmission process of up data in the method comprises the steps that: E1 digital signals sent by n E1 interfaces of a line interface module are simultaneously received at each E1-media access control (MAC) module end, the received E1 digital signals are converted to Ethernet data packets and then are successively sent to an Ethernet exchange chip through one Ethernet interface, and the Ethernet data packets are forwarded to a server side by the Ethernet exchange chip; and the transmission process of down data comprises the steps that: when the Ethernet data packets issued by the Ethernet exchange chip are received at each E1-MAC module end, the Ethernet data packets are converted to the E1 digital signals, then are copied for n copies, and are respectively sent to the corresponding n E1 interfaces, and afterwards, the signals are processed by the line interface module and are transmitted to a client side through a transmission line. The convergent type EoPDH network bridge equipment and the data transmission method thereof have the advantages that the implementation difficulty of the equipment is reduced, FPGA (field programmable gate array) resources are saved, and more E1 access quantities can be achieved.