627 results about "Test point" patented technology

The invention belongs to the technical field of PCB flying probe detection equipment, and particularly relates to a flying probe compensation method and system based on PCB curved surface modeling, and the method comprises the steps: obtaining the size of a PCB, and carrying out the equilateral triangle grid division; in the visual alignment process, the laser distance measuring sensor is synchronously driven to carry out rapid non-contact height measurement on the vertex of the grid; based on the vertex three-dimensional coordinates, fitting triangular patches through a space plane equation and splicing the triangular patches into a three-dimensional curved surface model; performing bilinear interpolation on an area formed by adjacent patches in the model to smooth a curved surface; and finally, selecting an interpolation function according to the position of the test point to calculate the accurate height, and generating a Z-axis displacement compensation value of the probe. According to the high-precision measurement and self-adaptive compensation of the PCB warpage, the efficiency and precision of the flying probe test are considered, and the problem of poor contact or overvoltage damage of the probe caused by the board warpage is effectively solved.

The invention provides a 3D structure core particle test layout design method supporting cross-layer cascade test and single core particle self-test, and the method comprises the following steps: a, designing the test point layout of 3D stacked core particles, each layer of core particles adopting a hexagonal arrangement mode, and enabling a test PIN in one layer to be connected with six signal PINs in the same layer; and meanwhile, a vertical test channel is arranged, so that the in-layer test PIN of each layer is connected with the corresponding test PIN of the adjacent layer through a vertical interconnection structure. According to the invention, full test coverage of 3D stacking is adapted, the problem that interlayer signals are difficult to test in a 3D structure is solved through the in-layer hexagonal layout and the vertical test channel, and full-scene coverage of in-layer, interlayer and cross-core particle signals is realized.

The invention discloses a hardware-in-the-loop test method and device and electronic equipment, relates to the technical field of automotive electronics, and adopts a simulated annealing algorithm in an optimization stage, adjusts parameters according to characteristics of an electronic stability control system, optimizes data distribution, and improves test data quality and fault detection capability. In the verification stage, the generated test data is subjected to actual operation test, the data problem is fed back by comparing actual output with an expected result, and the optimized test data which does not pass verification is sent to the target hardware-in-loop test model for optimization adjustment, so that a closed-loop optimization verification process is formed. The iterative closed-loop process comprehensively covers all possible working conditions and fault modes, key test points are prevented from being omitted, the reliability of the electronic stability control system is enhanced, the accuracy, effectiveness, comprehensiveness and sufficiency of hardware-in-the-loop test of the electronic stability control system are ensured, and the reliability of the electronic stability control system is improved. And the limitation of hardware-in-the-loop test of the electronic stability control system is reduced.

The invention belongs to the technical field of road engineering roadbed nondestructive testing, discloses a roadbed humidity nondestructive testing method based on wireless radio frequency signal multi-parameter inversion, and aims to solve the problems that a traditional roadbed humidity testing method is destructive, low in efficiency and discontinuous in monitoring or detection parameters are easily interfered. The method specifically comprises the following steps of: firstly, embedding an RFID tag and acquiring an on-site received signal strength indication value; then establishing a relation model of the received signal strength indication value and the roadbed moisture content, and extracting characteristic parameters only influenced by the moisture content; then, constructing a neural network model, taking the extracted characteristic parameters as input, and utilizing field data to train the model to invert the roadbed moisture content; and finally, the spatial distribution of the moisture content of the roadbed is obtained by combining the distribution of the test points and the roadbed structure information, so that the efficient, non-contact and continuous monitoring of the humidity state of the roadbed is realized.

The invention belongs to the technical field of semiconductor device performance testing, and particularly relates to a VCSEL epitaxial wafer resistivity distribution measuring method and system, and the method comprises the steps: constructing a three-dimensional discretization model representing an epitaxial wafer and an unknown parameter vector containing the vertical resistivity, the top transverse resistivity and the substrate leakage junction nonlinear resistance; a physical response function is defined, the vector is iterated through a discrete point fitting algorithm, so that the total residual error between the analog voltage difference output by the function and the actually measured voltage value under the cross-order-of-magnitude current is minimum, and the real vertical resistivity is extracted from the optimal parameter vector; and obtaining the vertical resistivity of each point on the two-dimensional test point grid so as to generate a distribution diagram and carry out anomaly detection. According to the invention, the problem of measurement distortion caused by the leakage defect of the substrate is solved, and the measurement accuracy of the vertical resistivity is improved.

The invention discloses a dynamic simulation test verification method and system for a pumped storage unit monitoring system, and the method comprises the steps: building a high-dimensional system state matrix of a pumped storage unit based on the physical parameters and structural features of a hydraulic, mechanical and electrical system of the unit, carrying out the dimension reduction of the high-dimensional system state matrix, and obtaining a dynamic simulation test result of the pumped storage unit; a dynamic simulation model of unit multi-physics field coupling is obtained; constructing a multi-dimensional parameter space based on the parameter sensitivity coefficient and the working condition boundary condition of the dynamic simulation model, and calculating optimal test point distribution through a high-dimensional point flow diameter algorithm to obtain a test scene library; based on the dynamic simulation model and the test scene library, obtaining a real-time monitoring signal sequence conforming to a monitoring system communication protocol; and based on the real-time monitoring signal sequence, signal acquisition, logic judgment and alarm control functions of the monitoring system are tested through an automatic test script, and a performance evaluation result of the monitoring system is obtained. The test comprehensiveness and effectiveness of the pumped storage unit monitoring system are improved.

Systems and Methods for capacitance testing of a unit under test with parasitic capacitance directed to a guard rail. The system includes test points, wherein the plurality of test points are divided into at least two groups; a stimulus source; a first group guard relay electrically connected to each of the test points in a first; a second group guard relay electrically connected to each of the test points in a second; a guard rail coupled to the first group guard relay and the second group guard relay; a first group return relay electrically connected to each of the test points in a first group; a second group return relay electrically connected to each of the test points in a second group; a current measurement rail coupled to the first group return relay and the second group return relay; a current meter coupled to the measurement rail; and a controller.

The invention discloses a non-standard ammeter anomaly detection method based on a parameterized protocol model, and the method comprises the steps: firstly constructing a parameterized protocol model which comprises test point models corresponding to a plurality of test points; loading the parameterized protocol model, and determining a detection execution sequence; generating a request frame for any test point according to communication information configured in the parameterized protocol model, sending the request frame to a tested ammeter, performing communication interaction with the tested ammeter, and receiving a response frame returned by the tested ammeter; performing verification on the response data, and performing field-level analysis and data conversion according to a verification result to obtain an actual detection value of the test point; and performing fault judgment according to the actual detection value and generating a detection report. According to the method, non-standard electricity meters of different models and different protocol formats can be adapted under the condition that detection program codes do not need to be modified.

The invention relates to the technical field of probe testing, in particular to a PCB flying probe test path optimization method based on electrical characteristics, which comprises the following steps: calculating accessibility scores of test points according to the distribution of board surface test points and elements to determine risk types of the test points; determining a risk area grade corresponding to the grid unit according to the accessibility score in combination with the potential shadow area; optimizing the test path of the probe according to the risk area grade corresponding to the grid unit, and adjusting the initial moving speed of the test path of the probe in different grid units; for the same moving time sequence of different probe groups, determining overlapped grids according to the initial probe angles and the test paths corresponding to the probes, and determining whether there is a collision risk between the probes in combination with the initial moving speeds of the probes in different grid units; and when a collision risk exists between the probes, corresponding adjustment measures are taken according to the number of the overlapped grids. According to the invention, the test path is optimized in combination with multi-dimensional design based on the electrical characteristics and testability of the board.

The invention relates to the technical field, and discloses a fisheye test needle group for testing a circuit board, which comprises a test board, the test board comprises a heating pressing block, an insulating component and a base, a test sample is placed between the heating pressing block and the insulating component, the test sample comprises a sample body and fisheye needles extending from pins on the sample body, and the fisheye needles are arranged on the base. A plurality of groups of double-end probes and elastic sheets are mounted in the base and are in butt joint with fisheye needles, the fisheye needles, the double-end probes and the elastic sheets form a test needle group, when the test sample sinks, the fisheye needles are in butt joint with the double-end probes, the elastic sheets are in butt joint with the fisheye needles to form two pairs of contacts, and when the test sample sinks to guide a first pair of contacts to appear, the first pair of contacts are in butt joint with the fisheye needles. And the wedge-shaped surface in the sinking direction guides the elastic sheet to incline so as to form the second pair of contacts, so that the current and voltage required by Kelvin testing can be met, the two pairs of contacts and a plurality of testing points are integrated in a single structure, and the use requirement is met by the appearance of lateral force while vertical downward force exists.

The invention relates to the technical field of circuit board detection, in particular to a printed circuit board drilling quality detection method and device, and the method comprises the steps: injecting sinusoidal current signals with preset frequencies into a plurality of test points of a to-be-detected drilling region of a printed circuit board, extracting impedance values under each frequency component, and calculating the drilling quality of the printed circuit board; constructing an equivalent impedance spectrum containing a real part and an imaginary part according to the impedance value; according to the interlayer structure and the equivalent impedance spectrum of the printed circuit board, calculating equivalent resistance and equivalent capacitance of the drilling area to be measured to form a characteristic parameter set; comparing the data of each grid point in the characteristic parameter set with a preset threshold value, and integrating the grid points exceeding the preset threshold value to generate a defect state mark; and performing electrical topology constraint on the defect state mark to generate a defect positioning result. According to the invention, hidden defects in the drill hole and interlayer structures can be deeply detected, the electrical performance of the drill hole can be comprehensively evaluated, and accurate defect positioning and state marking can be provided.

The invention relates to the technical field of semiconductor device testing and testing probes thereof, in particular to a semiconductor device testing probe and a semiconductor device testing method thereof. The method comprises the following steps: firstly, acquiring a contact stability coefficient of a test probe at each test monitoring moment, further determining all abnormal contact moments under each abnormal contact type in a preset historical test time period, and further determining the abnormal contact moments according to the total number of the abnormal contact types and the contact stability coefficient; according to the different abnormal contact types and the change distribution of the contact resistance in the preset time domain at the abnormal contact moment under the different abnormal contact types, acquiring the pressure application abnormal coefficient of the test probe and adjusting the applied pressure. According to the invention, the contact state is evaluated by analyzing the change characteristics of the contact resistance, and then the pressure application abnormal condition of the test probe is evaluated to adjust the pressure application, so that the good contact between the test probe and the device test point is ensured, and the test accuracy of the semiconductor device is improved.

The invention provides a method for detecting wafer bonding alignment deviation. The method comprises the steps that a preset number of metal test points are arranged on two wafers to be bonded according to preset coordinates, and every two metal test points on a first wafer and every two metal test points on a second wafer serve as a test loop; detecting the conduction condition of each group of test loops after the two wafers are bonded; and determining the bonding alignment deviation between the two wafers according to the conduction condition of each group of test loops. According to the invention, the detection precision of the wafer bonding alignment deviation can be improved.

The invention discloses a test control method and system for a direct-current power supply, and relates to the field of simulation testing, and the method comprises the steps: constructing a three-dimensional adaptive model to complete the matching calibration of system software and hardware, and achieving the load calibration through the comparison of dynamic load simulation and actual measurement data; in the testing process, a three-stage starting mechanism is adopted to power on step by step, fault protection is configured, and parameter scanning and real-time recording are executed according to a preset mode and a testing point; a double-closed-loop feedback mechanism is introduced, an inner loop adjusts output parameters, and an outer loop predicts power grid disturbance and performs advanced compensation; a safety threshold value is dynamically generated in combination with real-time environment data, linkage protection of approaching early warning and overrun protection is achieved, and a reliable effective data set is formed through fusion processing and double verification of multi-source test data. The system has the advantages that the precision and intelligence of the whole test process are realized through dynamic load simulation, a multi-level safety protection system is constructed through a three-level starting mechanism, and the precision, safety and data value of the test are comprehensively improved.

The invention discloses an impedance matching method and system for chip testing, electronic equipment and a medium, and relates to the technical field of data processing. The method comprises the following steps: establishing electrical connection between a test probe and a to-be-tested chip test point, and sending a preset detection signal; acquiring incident power and reflection power of the detection signal; calculating a first signal reflection coefficient based on the incident power and the reflection power, and determining an impedance deviation value and an adjustment direction according to a difference value between the first signal reflection coefficient and a preset standard reflection coefficient; determining a parameter adjustment step length according to the impedance deviation value; sequentially adjusting a variable resistor, a variable capacitor and a variable inductor in the impedance matching network according to the step length and the adjusting direction; detecting a second signal reflection coefficient when the impedance real part and imaginary part of the variable element reach the target range; and judging whether the second signal reflection coefficient converges to a preset range, and if yes, taking the current matching network parameter as an impedance matching result. By implementing the technical scheme provided by the invention, the impedance matching accuracy of the chip test can be improved.

The invention discloses a dynamic load identification method and device based on a physical guidance convolution long-short-term memory network, and relates to the field of data processing, and the method comprises the steps: constructing a dynamic load identification model based on the convolution long-short-term memory network, and training the dynamic load identification model, and obtaining a trained dynamic load identification model; loss functions used in the training process of the dynamic load recognition model comprise a data driving loss function and a physical guidance loss function, the physical guidance loss function is constructed based on a kinetic equation converted from a motion equation of a linear system under the action of power, and an overall transfer matrix is used; acquiring the acceleration and / or strain response time domain signal of each test point acquired in each time window when the to-be-identified dynamic load is applied to one or more action points on the structure, and inputting the acceleration and / or strain response time domain signal into the trained dynamic load identification model to obtain the predicted dynamic load corresponding to the one or more action points. The problem that current load identification is high in dependence on data is solved.

The invention relates to the technical field of wafer testing, in particular to a wafer testing result visualization method and system. Through spatial discretization processing, continuous physical coordinates of test points are mapped to a fixed N * N regular grid, and mass and disordered coordinate points are classified into limited and ordered grid units through the conversion, so that the complexity of data positioning is reduced from O (n) to O (1). When rendering is carried out, a system can directly access grid data at any position through simple coordinate transformation without traversing all test points based on a data structure established on the basis of the regular grid. More importantly, the rendering mode is dynamically selected and drawn, so that the rendering calculation amount of the system does not depend on the total amount of test points any more, but depends on the number of grids in the current viewport. And the processing object is fundamentally optimized from a'test point 'to a'viewport inner grid', so that the data processing and rendering efficiency is greatly improved.

The invention relates to the technical field of PCBs, and discloses a PCB hole chain capability test module and a design method and a test method thereof. At least a test point area and a hole chain test area are arranged in the test module; the design method comprises the following steps: according to the laminated structure of a target circuit board and the hole pattern distribution of each layer, determining the pattern and arrangement distribution of each test hole in the test module with the same laminated structure; based on the verification demand type of the test module, determining the hole wall spacing between the test holes; and determining a test hole chain formed by all the test holes in the hole chain test area according to the form and arrangement distribution of the test holes and the hole wall spacing, and further obtaining the structure of the test module. The test module obtained by the design method not only can realize the basic test of the reliability of the hole chain of the PCB product, but also can meet the verification requirements of different types such as equipment detection precision or materials.

This invention discloses a laser engraving system and method for a high-ink-capacity ceramic anilox roller, relating to the field of ceramic roller laser engraving, aiming to solve the problems of limited ink capacity and low production efficiency in existing technologies. The system includes a laser head, a ceramic roller, and a cell observation instrument, and also includes modules for cell image acquisition, test point positioning, engraving control, analysis, and sub-scanning planning. The laser head includes a laser, a high-frequency torque motor, etc. The high-frequency torque motor can drive the movement of a reflector to adjust the laser beam trajectory. The method generates anilox data, positions cells and test points, matches laser power to engrave test points, compares data output strategies, and dynamically adjusts the sub-scanning trajectory before engraving. This invention adopts a dual-scanning trajectory, combined with real-time visual feedback to adaptively control laser power and trajectory, to achieve fine cell engraving, improve ink capacity, ink transfer uniformity, and production efficiency, and avoid ceramic damage.

The invention discloses an automatic turn-back function testing method and device, relates to the technical field of train control system testing, and mainly aims to improve the efficiency of automatic turn-back function testing. According to the main technical scheme, a simulator corresponding to a tested vehicle-mounted end is created based on preset communication behavior logic, communication connection between the simulator and the tested vehicle-mounted end is established, the tested vehicle-mounted end is a turn-back receiving end, and the simulator is used for simulating a turn-back initiating end corresponding to the turn-back receiving end; the communication behavior logic represents a single-end behavior rule of a turn-back initiating end in a turn-back process; configuring a test case according to a turn-back operation test point in the automatic turn-back function, wherein the test case has a corresponding expected result; according to the test case, driving the simulator and the tested vehicle-mounted terminal to simulate and execute an automatic turn-back interaction process to obtain a test result; and comparing a test result with an expected result so as to verify whether the automatic turn-back function is normal based on the tested vehicle-mounted terminal and the simulator.

The utility model relates to the technical field of sensor detection, in particular to a high-precision current sensor rapid testing tool which comprises a bottom plate, the upper end of the bottom plate is fixedly connected with a first fixing plate, one side of the first fixing plate is rotatably connected with a first threaded rod through a sliding bearing, and the first threaded rod is rotatably connected with a first threaded plate. The lower end of the first threaded plate is fixedly connected with a first sliding block, and the first sliding block is slidably connected with a first sliding rail. The positioning device has the function of ensuring that the clamping device can quickly and accurately move to a designated position, high-precision position adjustment is achieved through a precise sliding rail and a thread transmission system, so that the precise positioning requirement under different operation requirements is met, the operation speed is increased through the clamping device, and the working efficiency is improved. And the material processing accuracy is greatly improved, so that all steps from material grabbing to final test point placement can be efficiently and accurately completed.

This utility model relates to the field of testing technology, and in particular to an elevator noise testing device and system, comprising: a support assembly; a testing host mounted on the support assembly; a housing and a main control module disposed within the housing; and testing components, including a noise acquisition module, a distance measurement module, a positioning module, and a distance fine-tuning module integrated into the testing host; the noise acquisition module, distance measurement module, positioning module, and distance fine-tuning module are respectively connected to the main control module. The elevator noise testing device provided in this application, through a three-level collaborative control system integrating the distance measurement module, positioning module, and distance fine-tuning module, achieves rapid positioning and automatically adjusts the distance between the noise acquisition module and the test point through the distance fine-tuning module, realizing millimeter-level positioning accuracy of the detection point, ensuring accurate capture of the maximum noise value, and improving testing accuracy.

The utility model discloses a waterproof performance testing device for double sealing gaskets of a shield tunnel joint, which relates to the technical field of shield tunnel equipment and comprises a base, supports are fixed on the base, two butted testing pipelines are mounted on the supports, an air blowing part is arranged on the side surface of one support, a plugging part is arranged on the side surface of the other support, and the testing pipelines are connected with the air blowing part. The air blowing part and the blocking part slide along the base, a sliding groove is formed in the base for the air blowing part and the blocking part to slide, a testing frame is fixed to the pipe seam of the two testing pipelines, a testing part is fixed to the interior of the testing frame, and a pressure gauge is fixed to the side face of each testing pipeline; the testing device is convenient to adjust and suitable for testing pipelines or sealing gaskets of different sizes, testing points can be set according to actual needs, sealing testing results of different positions of the sealing gaskets can be obtained, and testing precision is improved.

This invention provides a high-resistance probe station for chip testing, comprising a testing platform with a testing chamber connected to its upper surface; a loading mechanism including an x-axis translation module, a y-axis translation module, and a loading stage located within the testing chamber; a probe testing mechanism including a cylinder connected to the upper surface of the testing chamber, the cylinder having an output end connected to a testing probe, and an air-floating ring connected to the outside of the testing probe, the air-floating ring being positioned along the testing probe; and a vacuum adsorption mechanism including a vacuum pump located within the testing platform, the output end of the vacuum pump being connected to a negative pressure tube and a negative pressure tube. This invention significantly improves the insulation strength of localized areas by creating a dynamic high-voltage microenvironment at the test point through the air-floating ring, formed by the combined action of inert gas blowing and vacuum suction.

The present application relates to the technical field of electric fault detection, in particular to a pressure sensitive device damage diagnosis system combined with pulse test, comprising the following modules: an original signal acquisition module, inputting pulse sequences to the pressure sensitive device, recording voltage response signals and current response signals under each pulse sequence respectively, and generating a response signal set; based on the response signal set, wavelet decomposition is performed on the voltage response signals and the current response signals. In the present application, the pulse sequences are inputted and the voltage response signals and the current response signals under each pulse sequence are recorded, so that the data acquisition covers different working states and reduces the feature loss caused by a single test point. The voltage response signals and the current response signals are divided into different frequency intervals by using the wavelet decomposition method, which is helpful to separate the high-frequency and low-frequency features, so that the local abnormal signals are not covered by the global features, and the analysis ability for short-time fault features is enhanced.

The invention relates to the technical field of computers, and discloses a test case generation method and device, equipment and a medium, and the method comprises the steps: receiving a software test demand through a demand analysis agent, extracting a test point of the software test demand, and constructing a target knowledge graph according to the test point; generating an initial test case based on the test target knowledge graph through the case generation agent; executing the initial test case through the execution verification agent to obtain a test result; the test result comprises validity judgment and judgment basis of the initial test case; and in response to the test result, judging that the initial test case is an invalid test case, optimizing strategy parameters of each agent in the agent system based on the judgment basis through the evolutionary learning agent, and generating a new test case. The application can respond to the change of the test demand in real time, automatically adjust the test strategy, and improve the test quality and efficiency.

The invention relates to a gauge rod insulation test system, method and device and a storage medium. The gauge rod insulation test system comprises an industrial control assembly, a mechanical rust removal assembly, an insulation test assembly and a display assembly. The detection connection points of the insulation test assembly are respectively connected with the test points of the target test positions; the industrial control assembly is used for acquiring the surface state of the to-be-tested gauge rod at a target test position; under the condition that the surface state is the first state, controlling a mechanical rust removal assembly to remove a non-conductive layer on the target test position; controlling an insulation test assembly to perform insulation test on the test points of the target test positions to obtain insulation test data; and the control display assembly displays and stores the insulation test data. According to the automatic test system provided by the invention, by configuring the mechanical rust removal assembly, the insulation test assembly and the display assembly, automatic rust removal, automatic test and automatic recording of the gauge rod are realized, and the test efficiency and accuracy of the gauge rod can be greatly improved.

The invention relates to the technical field of integrated circuits and provides a chip verification method, computer equipment, a medium and a chip verification platform. The method comprises the following steps: based on test content of a first test point, selecting a necessary subsystem module associated with the first test point in a plurality of subsystem modules which are designed by a first chip and are integrated on a system top layer; identifying other subsystem modules except the necessary subsystem module associated with the first test point in the plurality of subsystem modules as unnecessary subsystem modules associated with the first test point; performing register transfer level compilation and emulation verification of test content for a first test point, including instantiating a chip top layer control module integrated on a chip top layer of a first chip design, instantiating a necessary subsystem module associated with the first test point, and performing a first test point design; and performing virtual module replacement operation on the unnecessary subsystem module associated with the first test point. In this way, compiling and simulation time is shortened, and verification efficiency is improved.

Systems and Methods for capacitance testing of a unit under test with parasitic capacitance directed to a guard rail. The system includes test points, wherein the plurality of test points are divided into at least two groups; a stimulus source; a first group guard relay electrically connected to each of the test points in a first; a second group guard relay electrically connected to each of the test points in a second; a guard rail coupled to the first group guard relay and the second group guard relay; a first group return relay electrically connected to each of the test points in a first group; a second group return relay electrically connected to each of the test points in a second group; a current measurement rail coupled to the first group return relay and the second group return relay; a current meter coupled to the measurement rail; and a controller.

The invention relates to a quick open and short circuit test dichotomy between any points of an IC wafer disc. A wafer bonding pad test channel is established based on a case board card framework, a test point TP corresponding to a wafer bonding pad is connected to N test unit board cards through a switch matrix, a connector and a carrier, and a power supply and communication link is formed by a backboard and a core control board. Each test unit board card executes an in-board dichotomy test and uploads an in-board open / short circuit initial determination result; the core control board executes an inter-board dichotomy grouping test on each slot position to determine a target board card set; and the test points TP of any two target board cards are divided into blocks and are positioned to the minimum block, point-to-point scanning is executed in the minimum block, and an open-short circuit positioning result is output. The method gives consideration to the configurable number of board cards and the multi-layer bipartite convergence path, and is suitable for the rapid open-short circuit positioning scene of the high-order-of-magnitude wafer bonding pad.