86 results about "Fault coverage" patented technology

The invention discloses a transformer internal multi-parameter information fusion discharge diagnosis and evaluation method, and relates to the technical field of power equipment state monitoring and fault diagnosis. According to the method, eight types of sensors are deployed in a transformer, and electrical, mechanical, thermotechnical and insulating multi-physical-field parameters are cooperatively collected; thirdly, performing three-stage preprocessing of abnormal value elimination, standardization and differential noise suppression on the data; then 12 types of fault features are extracted; carrying out feature layer fusion by adopting a dynamic weight distribution method based on AHP-working condition correction, and constructing a fusion feature vector; performing decision-making layer fusion through a five-layer fuzzy logic-neural network hybrid model, and outputting a fault probability and a fault type; and finally, dividing five fault levels according to the fault probability and outputting specific processing suggestions. According to the method, multi-parameter adaptive fusion and high-precision diagnosis are realized, the accuracy is high, the average time delay is low, and the problems of incomplete fault coverage and poor working condition adaptability of a traditional method are effectively solved.

The invention discloses an alternating current power supply system low-voltage switch cabinet for an intelligent station and a power supply control method, and relates to the technical field of electric power automation and intelligent control, and the switch cabinet comprises an intelligent monitoring terminal, a transfer learning module, a self-adaptive optimization engine and an equipment fingerprint similarity evaluation module. According to the alternating-current power supply system low-voltage switch cabinet for the intelligent station and the power supply control method, a quantitative evaluation system is established through equipment composite fingerprint similarity evaluation, reliable improvement guarantee is provided for the reuse rate and the fault coverage rate after a fault prediction model is applied, and the reliability of the system is improved. Moreover, the isomorphic dual-channel feature fusion network improves the characterization capability of the time sequence dependence features and the topological correlation features, improves the intermittent fault detection rate, and achieves the exponential shortening of the model optimization period through the cooperation with incremental learning, thereby reducing the operation and maintenance cost, shortening the non-planned shutdown time of equipment, and improving the reliability of the system. And the autonomous operation and maintenance level of the smart power grid can be effectively improved.

The invention discloses an injection molding process fault diagnosis system based on a knowledge graph, and relates to the technical field of injection molding process fault diagnosis. The injection molding process data comprises novel fault case data, maintenance and solution records, expert experience and feedback and new equipment specifications, data preprocessing and structuring are carried out, and a multi-source dynamic data stream is output; and the knowledge increment extraction verification module is used for executing entity identification and relation extraction based on the multi-source dynamic data flow. Multi-dimensional data such as novel fault cases and expert experience are captured in real time through the multi-source data dynamic acquisition module, and the problem that a static knowledge graph cannot be brought into new changes is solved; the knowledge increment extraction verification and self-adaptive updating module can dynamically expand the ontology, incrementally update the atlas and guarantee the data consistency, ensure that the atlas can incorporate fault knowledge related to new materials and new equipment in real time, and expand the fault coverage range.

The invention provides a sensor optimization layout method and device for on-line state monitoring of a turbine cooler, and belongs to the field of aviation electromechanics. The method provided by the invention comprises the steps of determining a sensor type based on a turbine cooler fault monitoring signal type and a fault coverage rate index; establishing a turbine cooler simulation model; fault signals are obtained, the fault signals are input into the simulation model, and the fault signals at least comprise operation parameters and vibration parameters; analyzing and identifying fault sensitive monitoring points based on the correlation between the output result of the simulation model and the fault signal, and determining the layout position of a sensor; and on the basis of the sensor layout position and the sensor type, arranging an online state monitoring sensor of the turbine cooler. According to the sensor optimization layout method and device for on-line state monitoring of the turbine cooler, the running state of the turbine cooler can be monitored on line, fault information can be obtained in real time, and high-precision fault positioning is achieved.

The present application relates to the technical field of battery swap stations, and particularly provides a fault diagnosis method and apparatus for a battery swap station device, an electronic device, and a storage medium, aiming to solve the technical problems in existing fault diagnosis methods of low efficiency and poor fault coverage caused by manual implementation. For this purpose, the fault diagnosis method for a battery swap station device of the present application comprises: collecting data information of a battery swap device and a battery pack; extracting a battery swap station data feature on the basis of the data information of the battery swap device and the battery pack; obtaining a fault diagnosis model; and performing fault diagnosis on the battery swap station device by means of the fault diagnosis model on the basis of the battery swap station data feature. Thus, the fault diagnosis accuracy for battery swap station devices is improved, and the coverage of diagnosis of all faulty components is improved.

The invention discloses a fault test method and system for a phase change memory array, and relates to the technical field of integrated circuits, and the method comprises the steps: analyzing a plurality of fault modes in the phase change memory array, and extracting the necessary and sufficient conditions of each fault mode, the necessary and sufficient conditions being the failure characteristics of a certain unit or a plurality of units in the array; deducing a test sequence suitable for the fault test of the phase change memory array according to the necessary and sufficient conditions; constructing a fault detection circuit based on the test sequence, and embedding the fault detection circuit into a phase change memory array; and performing fault testing on the phase change memory array by using the fault detection circuit, and judging the health state of each memory unit in the array to complete the fault testing. The algorithm provided by the invention can detect the special fault of the PCRAM, which cannot be identified by a traditional detection circuit, so that the fault coverage rate is greatly improved.

The invention provides a memory built-in self-test method, a controller and a circuit, and relates to the technical field of memory testing, and the test method comprises the following steps: S1, starting to write 0 in an ascending order from the lowest address; s2, reading 0 for the lowest address, and then writing 1 and reading 1 in an ascending order; s3, reading 1 for the lowest address, and then writing 0 and reading 0 in an ascending order; s4, reading 0 for the lowest address, and then writing 1 in an ascending order; s5, reading 1 for the highest address, and then writing 0 and reading 0 in a descending order; s6, reading 0 for the lowest address, and then writing 0 in an ascending order; s7, reading 0 for the highest address, and then writing 1 and reading 1 in a descending order; and S8, reading 1 from the lowest address in an ascending order. The invention also provides a memory built-in self-test controller and a memory built-in self-test circuit. Based on the newly proposed March-E algorithm, the test speed and the fault coverage rate can be improved and the power consumption can be reduced with relatively low area overhead.

The invention discloses a memory testing method, a memory testing device, a storage medium and electronic equipment, and the memory testing method comprises the steps: traversing each storage unit of a to-be-tested memory, performing data read-write operation on the traversed target storage unit and an adjacent storage unit adjacent to the target storage unit according to a preset advancing rule; performing logical operation on the read data of the target storage unit and the read data of the adjacent storage unit to obtain an actual logical relationship value; if the actual logic relation value is not consistent with the standard logic relation value, it is determined that the to-be-tested memory has a fault, by adopting the method, the fault condition of the memory can be detected through the actual logic relation value, the reliability of a test algorithm is high, meanwhile, the fault coverage rate and the test complexity are both considered, and the fault test efficiency is high.

The invention discloses a test system and method for a vehicle end controller based on European standard charging pile charging, the test system is connected with a to-be-tested controller, and the test system comprises a charging pile analog signal input unit, a vehicle-mounted equipment analog signal output unit, a vehicle communication network simulation unit and a controller power supply simulation unit. The test method comprises the following steps: configuring a software model and parameters related to communication, initializing a unit, disconnecting a relay, writing the software model and the parameters into a lower computer, generating related excitation signals according to a protocol and the parameters, then changing related data signals, and feeding back changes generated by the data signals to a PC (Personal Computer) end. The test system and method for the vehicle end controller based on European standard charging pile charging provided by the invention have the advantages that the adaptation cost is reduced, the full fault coverage test is realized, and the development efficiency is improved.

The invention provides a path-based test case priority sequence recommendation method and system, and relates to the technical field of software testing, and the method comprises the following steps: obtaining test execution information of a target test case based on new and old version programs; assigning each node position of a test coverage path in the target test case to generate a test path feature vector; based on an XGBoost algorithm, respectively taking the test path feature vector and the program execution result as input and output, and training a fault prediction model; based on the fault prediction model, determining a prediction fault probability of a basic coverage path in the new version program, and screening to obtain a fault coverage path; according to the method, the target association scores of the test coverage paths and the fault coverage paths in the target test cases are calculated based on the preset recommendation rule, the target test cases are arranged according to the target association scores from large to small, and the priority recommendation sequence is generated, so that the fault paths can be effectively covered, and the accuracy of priority ranking of the test cases can be improved.

The present invention discloses a DRAM test method, device, readable storage medium and electronic device. The DRAM to be tested is first subjected to a burst read / write access operation based on a first preset read / write unit in units of a preset burst length, and then subjected to a burst read / write access operation based on a second preset read / write unit. The first preset read / write unit is different from the second preset read / write unit. Since the read / write access of the preset read / write unit is to read and write from both ends of the preset read / write unit to the middle at the same time, and the preset write bits of the preset burst length are selected in sequence through a mask and the remaining bits are shielded until data is written to each bit corresponding to the preset burst length. Therefore, the method is closer to the user's use environment. Compared with the existing burst access test, the mask is used to achieve bit-by-bit access within a burst length, which can better stimulate the faults between cells and improve the fault coverage rate when testing the DRAM.

The invention provides an urban electric power intelligent scheduling method and platform based on electric power energy big data, and relates to the technical field of electric power scheduling, and the method comprises the steps: obtaining a main power distribution network and a redundant power distribution network of a target city; outputting a predicted fault source and a predicted fault coverage area; whether isolation control is performed on the predicted fault coverage area is judged, and a redundancy scheduling instruction is generated; performing power dispatching optimization according to the redundancy dispatching instruction to generate a redundancy power dispatching scheme; and carrying out emergency power dispatching according to the redundant power dispatching scheme, and sending out first abnormity reminding information. Through the method and the device, the technical problem of excessive or insufficient isolation possibly caused by difficulty in dynamic adjustment according to real-time conditions due to lack of judgment and analysis of fault isolation in the prior art can be solved, and the technical effects of quickly recovering power supply in a fault area and improving the stability of power grid operation and the emergency response efficiency are achieved.

The methods and systems are directed to automated computer analysis and machine learning. Specifically, the systems and methods for using machine learning to generate fault prediction models and applying the fault prediction models to logical circuits to optimize test point insertion determinations and optimize fault detection in the logical circuit. Disclosed are methods and systems that that generates training data from training circuits (and optionally generate training circuits), trains a learning segment (which may include an artificial neural network (ANN)) using the training data. The learning segment (once trained) generates fault prediction models to predict the quality of a TP inserted on a given circuit location and optimize TPI for a given circuit. The methods and systems described provide computational (CPU / processing) time advantages and precision over conventional methods.

The application provides a test scheme for checking data retention performance of NOR type Flash memory, focuses on the influence of erase-write cycles on the data retention performance, unifies the erase-write cycle number of the Flash memory test, stipulates clear temperature selection criteria, provides a reference for the Flash memory related test, and comprises the following steps: step one: determining the basic test algorithm of the NOR type Flash memory as the Checkerboard algorithm from the algorithm design complexity and the fault coverage; step two: improving the Checkerboard algorithm process and determining the data retention fault determination step; step three: carrying out a pre-experiment to determine the data retention performance test temperature, erase-write number and sample number of the NOR type Flash memory; step four: determining the erase-write number of the data retention test at normal temperature and the sample number under each erase-write number; step five: determining the test pattern, failure criterion, test duration and test cycle; step six: carrying out the data retention test combined with the erase-write cycle based on the non-replacement timing truncation test; and step seven: test data processing, fitting the average failure time under different erase-write numbers with the erase-write number to obtain the corresponding relationship between the average failure time and the erase-write number.

The present application provides a method and device for optimizing the layout of sensors for online status monitoring of a turbine cooler, which belongs to the field of aviation electromechanical. The method provided in the present application includes determining the sensor type based on the fault monitoring signal type and fault coverage index of the turbine cooler; establishing a turbine cooler simulation model; obtaining a fault signal, and inputting the fault signal into the simulation model, wherein the fault signal includes at least operating parameters and vibration parameters; identifying fault-sensitive monitoring points based on the correlation analysis between the output result of the simulation model and the fault signal, and determining the sensor layout position; arranging the online status monitoring sensor of the turbine cooler based on the sensor layout position and the sensor type. The method and device for optimizing the layout of sensors for online status monitoring of a turbine cooler provided in the present application can monitor the operating status of a turbine cooler online, obtain fault information in real time, and achieve high-precision fault location.

Safety mechanisms are embedded into a System on a Chip (SoC) and are operable to detect faults present in the logic circuitry in the SoC. Various types of faults in logic circuitry can occur, for example, a bit stuck at 0 or 1, or a transient or temporary fault due to radiation impacting the SoC. SoC devices are required to meet certain automotive safety integrity standards. The most stringent automotive safety integrity level requires that 90% of random latent faults are detected in all relevant logic, including all safety mechanism. Examples disclosed include hardware based checkers and hardware or software based pattern generation methods that achieve high online fault coverage in safety mechanism circuitry used for functional safety. A hardware based safety mechanism monitors the logic circuitry during operation. Any time the safety mechanism detects any faults in the logic circuitry, a fault notification is propagated to upstream logic.

The invention discloses a TSV (Through Silicon Via) pre-binding test circuit and test method based on an enhanced loop oscillator, and relates to the field of TSV test. The invention aims to solve the problem that an existing TSV pre-binding test method is difficult to meet accuracy and integration at the same time. No matter in a TSV open-circuit fault test mode or an electric leakage fault test mode, the test result of each loop can be output to the automatic test equipment from the counting port in a frequency counting mode, and the corresponding open-circuit position and electric leakage conductance information are given after analysis and calculation by the automatic test equipment. According to the invention, TSV open circuit, electric leakage and open circuit and electric leakage mixed faults can be effectively detected, and the severity of the faults can be quantitatively diagnosed. The open-circuit fault coverage rate can reach 95%, and the minimum capacitance resolution is 2.98 fF; for a leakage fault, the minimum leakage-detectable conductance is 4n Siemens, and the leakage conductance diagnosis error does not exceed 11%.

The application discloses a DRAM test method, device, readable storage medium and electronic equipment, through two rounds of tests on the DRAM to be tested, each first preset read-write unit of the DRAM to be tested is traversed based on a preset interval and a preset test unit until all storage units of the DRAM to be tested are traversed, for the target test unit traversed, data read-write operation is performed on the target test unit based on preset test data, the read data is compared with the corresponding written data, the final test result is obtained through the comparison result of the two rounds of tests, the non-continuous access mode with a certain interval can be simulated, the previous test blind area is covered and the chip defects which are difficult to be found in the prior art are detected, the multi-storage unit faults such as bridge faults and coupling faults are excited, the fault coverage is improved, the reliability of the test result is enhanced, and therefore the product yield is improved.

The application provides a new energy vehicle electric drive system fault early warning method, device, equipment and medium, relates to the technical field of fault early warning, and comprises the following steps: based on the current operation condition of the vehicle electric drive system, calling a target efficiency benchmark model matched with the operation condition from a partition adaptive model library to generate a first benchmark efficiency corresponding to the operation condition; based on the real-time operation efficiency of the vehicle electric drive system and the first benchmark efficiency, performing efficiency trend anomaly analysis and component structure anomaly analysis to determine an anomaly confidence; if the anomaly confidence meets a preset fault positioning condition, extracting the efficiency anomaly features corresponding to the vehicle electric drive system, and combining a fault mechanism mapping library to locate the fault components in the vehicle electric drive system and the corresponding fault early warning results. The application can effectively improve the technical problems in the prior art, such as limited fault coverage, delayed early warning response, poor operation condition robustness, weak fault attribution ability, and dependence on manually set fixed thresholds.

The application provides a micro-service architecture-oriented intelligent chaos test method and device, relates to the technical field of software testing, and solves the problems of one-sided fault coverage of traditional tests, rigid strategies, easy triggering of system risks and disconnection with business scenarios. The method comprises the following steps: collecting a service call chain through a distributed tracking technology, and constructing a dynamic dependency graph comprising node importance and link throughput; adopting an LSTM neural network to analyze a business log sequence to identify a business process stage, and establishing a "stage-link-fault" triplet rule; integrating topology features, business stages and real-time operation indexes to construct a state space, and optimizing a fault injection strategy based on a reinforcement learning algorithm and a multi-objective reward function; and limiting the injection intensity and range through a conflict detection and pre-check mechanism. The application is used for reliability verification of a micro-service system, and improves test efficiency and safety.

The present application discloses a fault scan chain shielding method based on a compression environment, which relates to the field of EDA detection. The method determines the total number of chip scan chains and the maximum number of fault scan chains, generates a vector set to be tested and a shielding signal; selects test vectors in sequence, performs fault shielding diagnosis on the scan chain according to the shielding signal and the fault arrangement combination, and determines the target scan chain; updates the shielding signal, and generates a target test vector set and a target shielding signal set when the detection fault coverage meets the system-set threshold; the shielding signal decoder performs a shielding test on the target scan chain according to the target test vector and the target shielding signal, and diagnoses and analyzes the scan chain fault according to the compression response output of the scan chain compressor. The test vector and shielding signal are determined in accordance with the principle that the scan chain with higher fault detection weight needs to be observed first, and the scan chain with higher occurrence frequency in the combination with lower shielding weight value needs to be shielded more, which can greatly improve the diagnostic efficiency and diagnostic accuracy.

The application provides a device fault maintenance guidance method and device and a cloud maintenance guidance service platform, relates to the technical field of industrial device fault maintenance, and the device fault maintenance guidance method comprises the following steps: acquiring fault image data of a target device; inputting the fault image data into a visual semantic feature extraction model, performing visual semantic coding processing on the fault image data through the visual semantic feature extraction model, and acquiring a semantic feature vector corresponding to the fault image data; based on the semantic feature vector, performing nearest neighbor retrieval in a preset fault case vector library, and determining at least one candidate fault case vector that satisfies a preset condition in terms of similarity with the semantic feature vector; and generating corresponding candidate fault case information and maintenance guidance information according to the at least one candidate fault case vector. The application can realize end-to-end mapping from a device fault appearance image to maintenance guidance information, and significantly improves the response speed and fault coverage completeness of industrial device fault maintenance.

The present invention discloses a method for in-situ diagnosis of digital interface faults in an integrated modular electronic system, which includes: dividing the internal control objects of the integrated modular electronic system into several types of objects, and defining the communication and control methods for the several types of objects; testing the digital interfaces of the integrated modular electronic system according to the defined communication and control methods for the several types of objects; diagnosing digital interface faults of the integrated modular electronic system according to the test results of the digital interfaces. The method for in-situ diagnosis of digital interface faults in the integrated modular electronic system involved in the present invention effectively covers interface control faults of digital parallel buses, digital serial buses, and discrete control lines of system control units, functional thread control units, and module control units, and has the characteristic of comprehensive fault coverage; it is executed without unplugging and disassembling equipment or modules, and has the characteristics of simple operation and suitability for on-site maintenance.

This invention provides a method, system, device, and storage medium for testing DRAM memory cells. The method includes: writing preset test data into all memory cells of the DRAM to be tested, wherein the memory cells are grouped into memory cell groups according to a preset burst length; creating an access array, accessing the memory cell groups, and obtaining the row and column addresses of the memory cell groups; reading the current test data of the corresponding memory cell group according to the row and column addresses, and comparing it with the preset test data of the memory cell group; if the comparison results are consistent, the memory cell group is determined to have been accessed; obtaining the four adjacent row and column addresses on the diagonal according to the row and column addresses, and determining whether the corresponding adjacent memory cell groups have been accessed according to the adjacent row and column addresses; if all adjacent memory cell groups have been accessed, the test is determined to have passed. This invention can cover test blind spots and detect chip defects that are difficult to find, improve fault coverage, and enhance product quality.

The present invention discloses a cross-domain overall optimization method, system, equipment and medium for human-machine collaborative functional testing, which relates to the field of electronic information technology, including: determining the relationship between fault coverage and system inherent reliability by performing reliability analysis on the mainboard functional testing process; establishing a fault tree, extracting component reliability information from a historical maintenance data set, determining the reliability range of all functional test modules, and obtaining the correlation relationship between the modules; based on the fault tree analysis, analyzing the impact of concurrent failures of modules containing the same bottom event on the system inherent reliability, and correcting the system inherent reliability calculation formula; constructing an optimization model for the functional testing process, and proposing a two-stage optimization solution method considering reliability uncertainty; the optimization method, system, equipment and medium enhance the cross-domain overall optimization capability of the model, and provide more reliable decision support for human-machine collaborative testing.

The invention relates to a method, in particular a computer-implemented method, for carrying out a memory test in a data processing device which has a number of processor cores (3) and can access a memory element (4) to be tested, comprising: - defining a number of memory areas (42) of equal size in the memory element (4) corresponding to the number of processor cores (3); - Assigning (S3) the memory areas (42) to a respective processor core (3); - Simultaneously executing (S4-S9) identical memory test software in all processor cores (3) in order to test the respectively assigned memory area (42) for errors; - Signaling (S10) an error if the memory test software detects an error.

The invention relates to the technical field of pipeline systems, and discloses a pipeline system with an intelligent monitoring function, which comprises a pipeline body, an interface monitoring module, a data relay unit and a remote monitoring terminal, the pipeline body is formed by connecting a plurality of sections of pipe bodies through connectors, and the interface monitoring modules are embedded in grooves in the outer walls of the connectors; the data relay units are arranged at intervals in the length direction of the pipeline body and connected with the interface monitoring module in a wired mode. The remote monitoring terminal is connected with the data relay unit through a wireless communication network, the interface monitoring module comprises a leakage monitoring assembly, a radial displacement monitoring assembly and an axial pull-out monitoring assembly, and the leakage, the radial displacement and the axial pull-out monitoring are integrated through the interface monitoring module for monitoring the leakage, the radial displacement and the axial pull-out and a cooperative structure of the data relay unit and the remote monitoring terminal. Compared with a traditional single fault monitoring scheme, the fault coverage range is remarkably improved, the fault response time is remarkably shortened, and the fault removal precision and efficiency of communication pipeline faults are improved.

The application belongs to the technical field of chip testing, and discloses a chip detection system and method based on ATE and implementation integration. An electrical connection is established between a chip interface unit and a chip to be tested. The chip interface unit comprises an adaptive clamp and a connecting circuit board. A precise contact array is arranged in the adaptive clamp, which is used to reliably connect the chip to be tested and the connecting circuit board. A detection analysis unit executes various types of detection programs of the chip to be tested and collects detection data. A result processing unit receives, integrates and processes the detection data collected by the detection analysis unit, and generates a detection report. In the above manner, the shortcomings of single ATE testing and implementation testing are made up, and the test fault coverage is improved.

The invention relates to an RTL fault simulation method and device, electronic equipment and a computer readable medium. The method comprises the following steps: analyzing an RTL file to generate an RTL graph containing RTL nodes and behavior-level nodes; simulating all RTL nodes at the same time to obtain input signals of behavior-level nodes; constructing a dependency graph between the input signals of the behavior-level nodes, and traversing the dependency graph to determine redundant behavior-level nodes in the RTL graph; redundant behavior level nodes in the RTL graph are eliminated, non-redundant behavior level nodes are determined, and then simulation is conducted on the remaining non-redundant nodes; and judging whether the current circuit is stable or not based on the signal value, if not, iteratively executing the steps until the current circuit is stable, and if yes, executing RTL fault simulation of a preset period and then outputting an RTL fault simulation result and a fault coverage rate. The problem that redundant execution exists due to the fact that an existing RTL fault simulation method does not consider the dependency relationship between input of the nodes is solved.

The invention discloses a test point insertion method and device based on circuit cost, equipment and a storage medium, and relates to the technical field of EDA. Determining the insertion point type of the current round and the updated candidate test point set of the last round, and selecting candidate test points from the candidate test point set to insert the candidate test points into the circuit for cost simulation; respectively calculating cost difference values of circuit cost simulation before and after the candidate test points are inserted, and selecting target test points and corresponding target insertion sites of which the cost difference values meet a difference value threshold value; and inserting the target test point into the netlist data, and updating the candidate test point set according to the number of the remaining insertion points. According to the scheme, for different types of control points and observation points, corresponding cost functions are constructed according to respective circuit characteristics, the circuit characteristics are perfectly matched, the circuit fault coverage rate and the observable fault number are greatly improved, and the algorithm implementation speed is optimized. In the later DFT test stage, the test complexity and the number of test vectors are remarkably reduced, the scanning test efficiency is improved, and the influence of untestable faults is reduced.