8 results about "Fault coverage" patented technology

The application provides a new energy vehicle electric drive system fault early warning method, device, equipment and medium, relates to the technical field of fault early warning, and comprises the following steps: based on the current operation condition of the vehicle electric drive system, calling a target efficiency benchmark model matched with the operation condition from a partition adaptive model library to generate a first benchmark efficiency corresponding to the operation condition; based on the real-time operation efficiency of the vehicle electric drive system and the first benchmark efficiency, performing efficiency trend anomaly analysis and component structure anomaly analysis to determine an anomaly confidence; if the anomaly confidence meets a preset fault positioning condition, extracting the efficiency anomaly features corresponding to the vehicle electric drive system, and combining a fault mechanism mapping library to locate the fault components in the vehicle electric drive system and the corresponding fault early warning results. The application can effectively improve the technical problems in the prior art, such as limited fault coverage, delayed early warning response, poor operation condition robustness, weak fault attribution ability, and dependence on manually set fixed thresholds.

The application provides a micro-service architecture-oriented intelligent chaos test method and device, relates to the technical field of software testing, and solves the problems of one-sided fault coverage of traditional tests, rigid strategies, easy triggering of system risks and disconnection with business scenarios. The method comprises the following steps: collecting a service call chain through a distributed tracking technology, and constructing a dynamic dependency graph comprising node importance and link throughput; adopting an LSTM neural network to analyze a business log sequence to identify a business process stage, and establishing a "stage-link-fault" triplet rule; integrating topology features, business stages and real-time operation indexes to construct a state space, and optimizing a fault injection strategy based on a reinforcement learning algorithm and a multi-objective reward function; and limiting the injection intensity and range through a conflict detection and pre-check mechanism. The application is used for reliability verification of a micro-service system, and improves test efficiency and safety.

The application belongs to the technical field of chip testing, and discloses a chip detection system and method based on ATE and implementation integration. An electrical connection is established between a chip interface unit and a chip to be tested. The chip interface unit comprises an adaptive clamp and a connecting circuit board. A precise contact array is arranged in the adaptive clamp, which is used to reliably connect the chip to be tested and the connecting circuit board. A detection analysis unit executes various types of detection programs of the chip to be tested and collects detection data. A result processing unit receives, integrates and processes the detection data collected by the detection analysis unit, and generates a detection report. In the above manner, the shortcomings of single ATE testing and implementation testing are made up, and the test fault coverage is improved.

The present application belongs to the technical field of test vector optimization in electronic information processing discipline, and relates to a kind of adaptive intelligent generation and optimization method of chip test vector, by analyzing the netlist file of the chip to be tested, three types of weights of signal controllability, signal observability and fault sensitivity are given to each signal path, the comprehensive eigenvalue of each node is calculated by forward and backward propagation algorithm, and three-dimensional topological atlas is constructed;Based on the three-dimensional topological atlas, the potential energy function of the candidate test vector is defined, which is dynamically adjusted by the redundancy coefficient, coverage coefficient and entropy weight coefficient according to the optimization progress index;Gradient descent operator, topological tunneling operator and topological homotopy operator are used for collaborative evolution search, and operator selection, population size and termination condition are scheduled through three-layer adaptive mechanism;Using producer-consumer architecture combined with incremental forward fault propagation, the test vector set is efficiently screened, and the fully adaptive and efficient generation of test vector set with high fault coverage and low redundancy is realized.

This application discloses a memory testing method, memory testing equipment, and computer program product. The method includes: executing a preset basic fault detection algorithm on multiple consecutive addresses within a memory region under test using at least one preset first test pattern array to detect basic faults in the multiple consecutive addresses; and executing a preset hold fault detection algorithm on the at least one first test pattern array and at least one preset second test pattern array to detect hold faults in the multiple consecutive addresses. Each second test pattern array is a binary sequence repeating every M bits, and each M bit includes at least one logical value with at least three consecutive transitions, where M is a natural number, and 8 ≤ M ≤ the number of bits in the memory cell. This application can significantly improve fault coverage and defect interception rate.

The present disclosure provides a method for obtaining fault coverage of a test algorithm and related equipment, and belongs to the technical field of semiconductor integrated circuit testing. The method comprises: obtaining a fault characteristic equation of a fault model of an object to be tested; obtaining an algorithm logic equation of a test algorithm; and determining whether the test algorithm covers the fault model according to the algorithm logic equation and the fault characteristic equation. The present disclosure provides a scheme for obtaining fault coverage of a test algorithm with low cost and high efficiency.

The application discloses a kind of liquid flow battery system fault diagnosis method, belong to liquid flow battery system monitoring technical field, including the following steps: S1, carries out multidimensional parameter monitoring;S2, carries out dynamic data preprocessing;S3, establishes health state evaluation model;S4, carries out fault diagnosis and classification;S5, carries out self-adapting optimization mechanism.The application establishes electrolyte flow rate-pile polarization voltage multivariate regression model, and integrates vibration spectrum, spectrum analysis and other multidimensional characteristics, constructs high-dimensional fault feature space.Make the accuracy rate of distinguishing mass transfer efficiency anomaly and electrode failure improve, misjudgment rate reduces.Fault coverage rate rises to, support the accurate classification of multiple kinds of faults.

This application discloses an integrated testing fixture, testing method, and apparatus for CNC machine tools. The integrated testing fixture includes a power supply configured to supply power to a power supply module; multiple motors, each corresponding to a multiple drive modules, with each motor connected to the power output port of its corresponding drive module; and a controller configured to acquire feedback information from the control module and issue commands to the control module to control the power supply and the operation of the motors. This application, through integrated testing of CNC machine tools, can fully simulate energy feedback and bus voltage surges under real common bus conditions. It also fully considers communication protocol matching and pre-charging logic coordination between modules, and can simulate phase loss faults in the power grid, effectively improving testing efficiency, accuracy, and fault coverage, while avoiding the problems of traditional discrete testing.