61 results about "Fault coverage" patented technology

The invention discloses a transformer internal multi-parameter information fusion discharge diagnosis and evaluation method, and relates to the technical field of power equipment state monitoring and fault diagnosis. According to the method, eight types of sensors are deployed in a transformer, and electrical, mechanical, thermotechnical and insulating multi-physical-field parameters are cooperatively collected; thirdly, performing three-stage preprocessing of abnormal value elimination, standardization and differential noise suppression on the data; then 12 types of fault features are extracted; carrying out feature layer fusion by adopting a dynamic weight distribution method based on AHP-working condition correction, and constructing a fusion feature vector; performing decision-making layer fusion through a five-layer fuzzy logic-neural network hybrid model, and outputting a fault probability and a fault type; and finally, dividing five fault levels according to the fault probability and outputting specific processing suggestions. According to the method, multi-parameter adaptive fusion and high-precision diagnosis are realized, the accuracy is high, the average time delay is low, and the problems of incomplete fault coverage and poor working condition adaptability of a traditional method are effectively solved.

The invention discloses an alternating current power supply system low-voltage switch cabinet for an intelligent station and a power supply control method, and relates to the technical field of electric power automation and intelligent control, and the switch cabinet comprises an intelligent monitoring terminal, a transfer learning module, a self-adaptive optimization engine and an equipment fingerprint similarity evaluation module. According to the alternating-current power supply system low-voltage switch cabinet for the intelligent station and the power supply control method, a quantitative evaluation system is established through equipment composite fingerprint similarity evaluation, reliable improvement guarantee is provided for the reuse rate and the fault coverage rate after a fault prediction model is applied, and the reliability of the system is improved. Moreover, the isomorphic dual-channel feature fusion network improves the characterization capability of the time sequence dependence features and the topological correlation features, improves the intermittent fault detection rate, and achieves the exponential shortening of the model optimization period through the cooperation with incremental learning, thereby reducing the operation and maintenance cost, shortening the non-planned shutdown time of equipment, and improving the reliability of the system. And the autonomous operation and maintenance level of the smart power grid can be effectively improved.

The invention discloses an injection molding process fault diagnosis system based on a knowledge graph, and relates to the technical field of injection molding process fault diagnosis. The injection molding process data comprises novel fault case data, maintenance and solution records, expert experience and feedback and new equipment specifications, data preprocessing and structuring are carried out, and a multi-source dynamic data stream is output; and the knowledge increment extraction verification module is used for executing entity identification and relation extraction based on the multi-source dynamic data flow. Multi-dimensional data such as novel fault cases and expert experience are captured in real time through the multi-source data dynamic acquisition module, and the problem that a static knowledge graph cannot be brought into new changes is solved; the knowledge increment extraction verification and self-adaptive updating module can dynamically expand the ontology, incrementally update the atlas and guarantee the data consistency, ensure that the atlas can incorporate fault knowledge related to new materials and new equipment in real time, and expand the fault coverage range.

The present application relates to the technical field of battery swap stations, and particularly provides a fault diagnosis method and apparatus for a battery swap station device, an electronic device, and a storage medium, aiming to solve the technical problems in existing fault diagnosis methods of low efficiency and poor fault coverage caused by manual implementation. For this purpose, the fault diagnosis method for a battery swap station device of the present application comprises: collecting data information of a battery swap device and a battery pack; extracting a battery swap station data feature on the basis of the data information of the battery swap device and the battery pack; obtaining a fault diagnosis model; and performing fault diagnosis on the battery swap station device by means of the fault diagnosis model on the basis of the battery swap station data feature. Thus, the fault diagnosis accuracy for battery swap station devices is improved, and the coverage of diagnosis of all faulty components is improved.

The invention discloses a test system and method for a vehicle end controller based on European standard charging pile charging, the test system is connected with a to-be-tested controller, and the test system comprises a charging pile analog signal input unit, a vehicle-mounted equipment analog signal output unit, a vehicle communication network simulation unit and a controller power supply simulation unit. The test method comprises the following steps: configuring a software model and parameters related to communication, initializing a unit, disconnecting a relay, writing the software model and the parameters into a lower computer, generating related excitation signals according to a protocol and the parameters, then changing related data signals, and feeding back changes generated by the data signals to a PC (Personal Computer) end. The test system and method for the vehicle end controller based on European standard charging pile charging provided by the invention have the advantages that the adaptation cost is reduced, the full fault coverage test is realized, and the development efficiency is improved.

The invention provides a path-based test case priority sequence recommendation method and system, and relates to the technical field of software testing, and the method comprises the following steps: obtaining test execution information of a target test case based on new and old version programs; assigning each node position of a test coverage path in the target test case to generate a test path feature vector; based on an XGBoost algorithm, respectively taking the test path feature vector and the program execution result as input and output, and training a fault prediction model; based on the fault prediction model, determining a prediction fault probability of a basic coverage path in the new version program, and screening to obtain a fault coverage path; according to the method, the target association scores of the test coverage paths and the fault coverage paths in the target test cases are calculated based on the preset recommendation rule, the target test cases are arranged according to the target association scores from large to small, and the priority recommendation sequence is generated, so that the fault paths can be effectively covered, and the accuracy of priority ranking of the test cases can be improved.

The invention provides an urban electric power intelligent scheduling method and platform based on electric power energy big data, and relates to the technical field of electric power scheduling, and the method comprises the steps: obtaining a main power distribution network and a redundant power distribution network of a target city; outputting a predicted fault source and a predicted fault coverage area; whether isolation control is performed on the predicted fault coverage area is judged, and a redundancy scheduling instruction is generated; performing power dispatching optimization according to the redundancy dispatching instruction to generate a redundancy power dispatching scheme; and carrying out emergency power dispatching according to the redundant power dispatching scheme, and sending out first abnormity reminding information. Through the method and the device, the technical problem of excessive or insufficient isolation possibly caused by difficulty in dynamic adjustment according to real-time conditions due to lack of judgment and analysis of fault isolation in the prior art can be solved, and the technical effects of quickly recovering power supply in a fault area and improving the stability of power grid operation and the emergency response efficiency are achieved.

The application provides a test scheme for checking data retention performance of NOR type Flash memory, focuses on the influence of erase-write cycles on the data retention performance, unifies the erase-write cycle number of the Flash memory test, stipulates clear temperature selection criteria, provides a reference for the Flash memory related test, and comprises the following steps: step one: determining the basic test algorithm of the NOR type Flash memory as the Checkerboard algorithm from the algorithm design complexity and the fault coverage; step two: improving the Checkerboard algorithm process and determining the data retention fault determination step; step three: carrying out a pre-experiment to determine the data retention performance test temperature, erase-write number and sample number of the NOR type Flash memory; step four: determining the erase-write number of the data retention test at normal temperature and the sample number under each erase-write number; step five: determining the test pattern, failure criterion, test duration and test cycle; step six: carrying out the data retention test combined with the erase-write cycle based on the non-replacement timing truncation test; and step seven: test data processing, fitting the average failure time under different erase-write numbers with the erase-write number to obtain the corresponding relationship between the average failure time and the erase-write number.

Safety mechanisms are embedded into a System on a Chip (SoC) and are operable to detect faults present in the logic circuitry in the SoC. Various types of faults in logic circuitry can occur, for example, a bit stuck at 0 or 1, or a transient or temporary fault due to radiation impacting the SoC. SoC devices are required to meet certain automotive safety integrity standards. The most stringent automotive safety integrity level requires that 90% of random latent faults are detected in all relevant logic, including all safety mechanism. Examples disclosed include hardware based checkers and hardware or software based pattern generation methods that achieve high online fault coverage in safety mechanism circuitry used for functional safety. A hardware based safety mechanism monitors the logic circuitry during operation. Any time the safety mechanism detects any faults in the logic circuitry, a fault notification is propagated to upstream logic.

The application discloses a DRAM test method, device, readable storage medium and electronic equipment, through two rounds of tests on the DRAM to be tested, each first preset read-write unit of the DRAM to be tested is traversed based on a preset interval and a preset test unit until all storage units of the DRAM to be tested are traversed, for the target test unit traversed, data read-write operation is performed on the target test unit based on preset test data, the read data is compared with the corresponding written data, the final test result is obtained through the comparison result of the two rounds of tests, the non-continuous access mode with a certain interval can be simulated, the previous test blind area is covered and the chip defects which are difficult to be found in the prior art are detected, the multi-storage unit faults such as bridge faults and coupling faults are excited, the fault coverage is improved, the reliability of the test result is enhanced, and therefore the product yield is improved.

The application provides a new energy vehicle electric drive system fault early warning method, device, equipment and medium, relates to the technical field of fault early warning, and comprises the following steps: based on the current operation condition of the vehicle electric drive system, calling a target efficiency benchmark model matched with the operation condition from a partition adaptive model library to generate a first benchmark efficiency corresponding to the operation condition; based on the real-time operation efficiency of the vehicle electric drive system and the first benchmark efficiency, performing efficiency trend anomaly analysis and component structure anomaly analysis to determine an anomaly confidence; if the anomaly confidence meets a preset fault positioning condition, extracting the efficiency anomaly features corresponding to the vehicle electric drive system, and combining a fault mechanism mapping library to locate the fault components in the vehicle electric drive system and the corresponding fault early warning results. The application can effectively improve the technical problems in the prior art, such as limited fault coverage, delayed early warning response, poor operation condition robustness, weak fault attribution ability, and dependence on manually set fixed thresholds.

The application provides a micro-service architecture-oriented intelligent chaos test method and device, relates to the technical field of software testing, and solves the problems of one-sided fault coverage of traditional tests, rigid strategies, easy triggering of system risks and disconnection with business scenarios. The method comprises the following steps: collecting a service call chain through a distributed tracking technology, and constructing a dynamic dependency graph comprising node importance and link throughput; adopting an LSTM neural network to analyze a business log sequence to identify a business process stage, and establishing a "stage-link-fault" triplet rule; integrating topology features, business stages and real-time operation indexes to construct a state space, and optimizing a fault injection strategy based on a reinforcement learning algorithm and a multi-objective reward function; and limiting the injection intensity and range through a conflict detection and pre-check mechanism. The application is used for reliability verification of a micro-service system, and improves test efficiency and safety.

The present application discloses a fault scan chain shielding method based on a compression environment, which relates to the field of EDA detection. The method determines the total number of chip scan chains and the maximum number of fault scan chains, generates a vector set to be tested and a shielding signal; selects test vectors in sequence, performs fault shielding diagnosis on the scan chain according to the shielding signal and the fault arrangement combination, and determines the target scan chain; updates the shielding signal, and generates a target test vector set and a target shielding signal set when the detection fault coverage meets the system-set threshold; the shielding signal decoder performs a shielding test on the target scan chain according to the target test vector and the target shielding signal, and diagnoses and analyzes the scan chain fault according to the compression response output of the scan chain compressor. The test vector and shielding signal are determined in accordance with the principle that the scan chain with higher fault detection weight needs to be observed first, and the scan chain with higher occurrence frequency in the combination with lower shielding weight value needs to be shielded more, which can greatly improve the diagnostic efficiency and diagnostic accuracy.

The application provides a device fault maintenance guidance method and device and a cloud maintenance guidance service platform, relates to the technical field of industrial device fault maintenance, and the device fault maintenance guidance method comprises the following steps: acquiring fault image data of a target device; inputting the fault image data into a visual semantic feature extraction model, performing visual semantic coding processing on the fault image data through the visual semantic feature extraction model, and acquiring a semantic feature vector corresponding to the fault image data; based on the semantic feature vector, performing nearest neighbor retrieval in a preset fault case vector library, and determining at least one candidate fault case vector that satisfies a preset condition in terms of similarity with the semantic feature vector; and generating corresponding candidate fault case information and maintenance guidance information according to the at least one candidate fault case vector. The application can realize end-to-end mapping from a device fault appearance image to maintenance guidance information, and significantly improves the response speed and fault coverage completeness of industrial device fault maintenance.

This invention provides a method, system, device, and storage medium for testing DRAM memory cells. The method includes: writing preset test data into all memory cells of the DRAM to be tested, wherein the memory cells are grouped into memory cell groups according to a preset burst length; creating an access array, accessing the memory cell groups, and obtaining the row and column addresses of the memory cell groups; reading the current test data of the corresponding memory cell group according to the row and column addresses, and comparing it with the preset test data of the memory cell group; if the comparison results are consistent, the memory cell group is determined to have been accessed; obtaining the four adjacent row and column addresses on the diagonal according to the row and column addresses, and determining whether the corresponding adjacent memory cell groups have been accessed according to the adjacent row and column addresses; if all adjacent memory cell groups have been accessed, the test is determined to have passed. This invention can cover test blind spots and detect chip defects that are difficult to find, improve fault coverage, and enhance product quality.

The present invention discloses a cross-domain overall optimization method, system, equipment and medium for human-machine collaborative functional testing, which relates to the field of electronic information technology, including: determining the relationship between fault coverage and system inherent reliability by performing reliability analysis on the mainboard functional testing process; establishing a fault tree, extracting component reliability information from a historical maintenance data set, determining the reliability range of all functional test modules, and obtaining the correlation relationship between the modules; based on the fault tree analysis, analyzing the impact of concurrent failures of modules containing the same bottom event on the system inherent reliability, and correcting the system inherent reliability calculation formula; constructing an optimization model for the functional testing process, and proposing a two-stage optimization solution method considering reliability uncertainty; the optimization method, system, equipment and medium enhance the cross-domain overall optimization capability of the model, and provide more reliable decision support for human-machine collaborative testing.

The invention relates to the technical field of pipeline systems, and discloses a pipeline system with an intelligent monitoring function, which comprises a pipeline body, an interface monitoring module, a data relay unit and a remote monitoring terminal, the pipeline body is formed by connecting a plurality of sections of pipe bodies through connectors, and the interface monitoring modules are embedded in grooves in the outer walls of the connectors; the data relay units are arranged at intervals in the length direction of the pipeline body and connected with the interface monitoring module in a wired mode. The remote monitoring terminal is connected with the data relay unit through a wireless communication network, the interface monitoring module comprises a leakage monitoring assembly, a radial displacement monitoring assembly and an axial pull-out monitoring assembly, and the leakage, the radial displacement and the axial pull-out monitoring are integrated through the interface monitoring module for monitoring the leakage, the radial displacement and the axial pull-out and a cooperative structure of the data relay unit and the remote monitoring terminal. Compared with a traditional single fault monitoring scheme, the fault coverage range is remarkably improved, the fault response time is remarkably shortened, and the fault removal precision and efficiency of communication pipeline faults are improved.

The application belongs to the technical field of chip testing, and discloses a chip detection system and method based on ATE and implementation integration. An electrical connection is established between a chip interface unit and a chip to be tested. The chip interface unit comprises an adaptive clamp and a connecting circuit board. A precise contact array is arranged in the adaptive clamp, which is used to reliably connect the chip to be tested and the connecting circuit board. A detection analysis unit executes various types of detection programs of the chip to be tested and collects detection data. A result processing unit receives, integrates and processes the detection data collected by the detection analysis unit, and generates a detection report. In the above manner, the shortcomings of single ATE testing and implementation testing are made up, and the test fault coverage is improved.

The invention relates to an RTL fault simulation method and device, electronic equipment and a computer readable medium. The method comprises the following steps: analyzing an RTL file to generate an RTL graph containing RTL nodes and behavior-level nodes; simulating all RTL nodes at the same time to obtain input signals of behavior-level nodes; constructing a dependency graph between the input signals of the behavior-level nodes, and traversing the dependency graph to determine redundant behavior-level nodes in the RTL graph; redundant behavior level nodes in the RTL graph are eliminated, non-redundant behavior level nodes are determined, and then simulation is conducted on the remaining non-redundant nodes; and judging whether the current circuit is stable or not based on the signal value, if not, iteratively executing the steps until the current circuit is stable, and if yes, executing RTL fault simulation of a preset period and then outputting an RTL fault simulation result and a fault coverage rate. The problem that redundant execution exists due to the fact that an existing RTL fault simulation method does not consider the dependency relationship between input of the nodes is solved.

The application provides a multifunctional test point allocation method and system based on an adaptive switch matrix, relates to the technical field of electronic testing, and realizes dynamic connection of physical probes and logical test points by acquiring integrated circuit topology information to construct a switch matrix; the same probe is allocated to different test points in different time periods by using time division multiplexing technology, test response signals are collected and deviation values are calculated; a fault point is determined based on the deviation, the influence degree of the fault point on surrounding nodes is analyzed, and a test priority level is obtained; the test timing is dynamically adjusted according to the priority level, high-priority nodes are preferentially tested, the switch state is controlled to realize intelligent allocation of test resources, and the test efficiency and fault coverage are improved.

Embodiments of the present application relate to a kind of fast RAM detection method, system, detection equipment and storage medium, the method comprises: when the MCU is powered on, the memory space of RAM is detected in the unit of first quantity of bytes, and the RAM detection result is obtained, the first quantity is determined according to running memory space and the length of byte in advance;Based on the RAM detection result, the power-on result corresponding to the MCU is determined.Through again the MCU is powered on, the data of RAM memory space is detected in the unit of first quantity of bytes, and the fast RAM detection of RAM memory space is completed.Thereby, the technical effects that can realize shortening detection time and keeping fault coverage unchanged can be realized.

The present application discloses a test point insertion method, device, equipment and storage medium based on circuit cost, relating to the technical field of EDA. Determine the type of insertion points in this round and the set of candidate test points after the previous round of update, select candidate test points from the set of candidate test points and insert them into the circuit for cost simulation; calculate the cost differences of the circuit cost simulation before and after inserting the candidate test points respectively, and select the target test points and corresponding target insertion sites whose cost differences meet the difference threshold; insert the target test points into the netlist data, and update the set of candidate test points according to the remaining number of insertion points. This solution constructs corresponding cost functions for different types of control points and observation points according to their respective circuit characteristics, perfectly fits the characteristics of the circuit, greatly improves the circuit fault coverage rate and the number of observable faults, and optimizes the implementation speed of the algorithm. In the later DFT test stage, it significantly reduces the test complexity and the number of test vectors, improves the efficiency of scan testing and reduces the impact of untestable faults.

The application discloses a vehicle intelligent auxiliary diagnosis method and system and a storage medium, and belongs to the technical field of intelligent cloud diagnosis. The method mainly comprises the following steps: if the fault information comprises a fault code, then in a pre-constructed fault knowledge graph, a first fault cause set and a first solution set are determined; if the fault information does not comprise a fault code, then according to the belonging relationship between a first fault phenomenon in the fault information and the fault knowledge graph, a fault phenomenon entity weight corresponding to the first fault phenomenon and a second fault cause are determined, and according to the number of a second fault phenomenon corresponding to the second fault cause, the belonging degree weight of the second fault cause is determined; according to the fault phenomenon entity weight and the belonging degree weight, the correlation degree weight of the second fault cause is determined, and finally, the second fault cause set and the corresponding second solution set are determined. The application improves the fault coverage rate and the fault diagnosis efficiency of vehicle fault diagnosis, and improves the situation that the personal maintenance experience is insufficient.

The invention relates to a built-in self-test method, architecture and system oriented to an in-memory computing macro-cell, and the method comprises the steps: executing a first test mode: inserting a computing activation vector and a computing enabling instruction in an MBIST test algorithm, and carrying out a computing test after a read operation to detect a coupling fault between a storage array and bit multiplication logic; and judging whether the storage reading result and the calculation result are correct or not, if so, entering a second test mode or judging that the self-test is correct and completing the detection, and otherwise, diagnosing the fault position based on the detection result. According to the test method provided by the invention, the calculation enabling and the calculation activation vector are inserted in the traditional MBIST algorithm, and the additionally executed multiply-accumulate calculation operation is verified after the read operation, so that the test efficiency is greatly improved on the premise of covering the fault type of the traditional memory. The specific fault of data coupling between the storage unit and the calculation unit can be further effectively detected, and the fault coverage rate is increased.

This invention discloses a fault testing method and system for phase-change memory arrays, relating to the field of integrated circuit technology. The method includes analyzing multiple fault modes in the phase-change memory array, extracting the necessary and sufficient conditions for each fault mode, where the necessary and sufficient conditions are the failure characteristics of one or more cells in the array; deriving a test sequence suitable for fault testing of the phase-change memory array based on the necessary and sufficient conditions; constructing a fault detection circuit based on the test sequence and embedding it into the phase-change memory array; and using the fault detection circuit to perform fault testing on the phase-change memory array, determining the health status of each memory cell in the array, and completing the fault testing. The algorithm of this invention can detect PCRAM-specific faults that traditional detection circuits cannot identify, thereby significantly improving fault coverage.

The application provides an equivalent traversal fault injection method for register error injection single event effect simulation, and is used for solving the technical problem that simulation time consumption and simulation fault coverage exist in contradiction in single event effect simulation of a large-scale integrated circuit register unit. The method is based on a multi-register unit fault injection model, adopts a traversal fault injection file set simulation mode of all register units, maximally discovers a fault condition caused by a single event effect in a to-be-tested circuit, and deletes invalid fault injection files in a fault injection file set corresponding to a register associated group of a non-enabled register unit and an enabled register unit. Space dimension screening is performed on non-working register units in the entire simulation period, and time dimension screening is performed on non-working time of a specified register, so that the time and space costs of simulation are greatly reduced, and the single event fault simulation and evaluation requirements in the design stage of a large-scale space integrated circuit are met.

The utility model discloses an electric wide-body vehicle fault reporting system which comprises a VCU control module, an exterior control module, a power control module, a T-BOX terminal, an instrument and a signal receiving terminal, the whole VCU control module comprises a VCU controller and a controlled assembly which are in signal connection with each other, and the exterior control module comprises an exterior controller and an exterior assembly which are in signal connection with each other. The VCU controller, the external controller and the power control module respectively feed back fault signals to the CAN bus, the T-BOX terminal and the instrument respectively read the fault signals on the CAN bus, the T-BOX terminal feeds back the fault signals to the signal receiving terminal to inform the fault information, and the instrument displays the fault information. According to the utility model, fault coverage and accurate positioning of the whole vehicle are realized, dynamic reliability optimization is carried out, the anti-interference capability is improved, efficient communication is realized, and data collaborative analysis is realized.

The invention provides a sequential circuit fault simulation method, which is used for simulating a sequential circuit fault coverage rate by injecting a fault point into a sequential circuit, and comprises the following steps: S1, obtaining a to-be-simulated circuit netlist, identifying whether a strongly connected component exists in the to-be-simulated circuit netlist, if the to-be-simulated circuit only comprises a simple loop, executing the step S2, and if the to-be-simulated circuit only comprises the simple loop, executing the step S3; if the to-be-simulated circuit contains the complex strong communication component, executing the step S3; s2, simulating a simple loop circuit in a compilation mode, and realizing state updating and fault point injection through an instruction sequence; s3, adopting a preset total in-degree analysis method to calculate the total in-degree of nodes in the circuit containing the complex strongly connected component, and taking the node with the minimum total in-degree as an entrance node so as to hierarchically unfold the circuit; s4, fault points are injected into the circuit containing the complex strong communication components, simulation is carried out, and event scheduling is managed by adopting a preset lazy event propagation strategy in the simulation process; and S5, outputting a simulation report and a fault coverage rate.

The invention relates to the technical field of power transmission equipment, discloses a preparation method of a material compatibility type intelligent early-warning insulated bus, and aims to solve the problems that fault monitoring of an existing insulated bus depends on an external sensor, only a single parameter can be detected, the risk of missing report exists, the insulation aging trend pre-judgment capability is lacked, and the reliability is poor. The technical problem that potential risks cannot be avoided in advance in the prior art is solved, an insulating base material, a functional sensing material, a synergistic dispersant and a functional additive are selected according to a preset ratio, a pre-dispersion liquid is prepared after classification pretreatment, then the pre-dispersion liquid and a pre-molten insulating base material are blended, in-situ dispersion and cross-linking reaction are synchronously executed, an insulating layer is formed by adopting a temperature gradient coating process, and the insulating layer is prepared. And finally, an electrode and an early warning module are integrated, a finished product is obtained through constant-temperature maintenance and performance calibration, the sensing material cooperatively responds to different faults, full-fault coverage is achieved, and the method guarantees stable material compatibility, accurate finished product early warning, rapid response, adaptation to multiple application scenes and remarkable industrial application value.

The invention discloses a digital twinning-based complex product testability scheme heuristic generation method, which comprises the following steps: constructing a digital twinning model of a complex product sensing system, the digital twinning model integrating component fault data and a multi-level signal flow graph; analyzing a fault propagation path based on the multi-level signal flow graph, and determining a candidate test point set; and using an improved genetic algorithm to optimize the candidate test point set according to the component fault data and the fault propagation path, and generating an optimal testability scheme. According to the method, in the testability scheme generation process, the digital twin technology and the heuristic algorithm are combined, and collaborative improvement of the test efficiency, the fault coverage degree and the resource utilization rate is achieved.