44 results about "Fault coverage" patented technology

The invention discloses a transformer internal multi-parameter information fusion discharge diagnosis and evaluation method, and relates to the technical field of power equipment state monitoring and fault diagnosis. According to the method, eight types of sensors are deployed in a transformer, and electrical, mechanical, thermotechnical and insulating multi-physical-field parameters are cooperatively collected; thirdly, performing three-stage preprocessing of abnormal value elimination, standardization and differential noise suppression on the data; then 12 types of fault features are extracted; carrying out feature layer fusion by adopting a dynamic weight distribution method based on AHP-working condition correction, and constructing a fusion feature vector; performing decision-making layer fusion through a five-layer fuzzy logic-neural network hybrid model, and outputting a fault probability and a fault type; and finally, dividing five fault levels according to the fault probability and outputting specific processing suggestions. According to the method, multi-parameter adaptive fusion and high-precision diagnosis are realized, the accuracy is high, the average time delay is low, and the problems of incomplete fault coverage and poor working condition adaptability of a traditional method are effectively solved.

The invention discloses an alternating current power supply system low-voltage switch cabinet for an intelligent station and a power supply control method, and relates to the technical field of electric power automation and intelligent control, and the switch cabinet comprises an intelligent monitoring terminal, a transfer learning module, a self-adaptive optimization engine and an equipment fingerprint similarity evaluation module. According to the alternating-current power supply system low-voltage switch cabinet for the intelligent station and the power supply control method, a quantitative evaluation system is established through equipment composite fingerprint similarity evaluation, reliable improvement guarantee is provided for the reuse rate and the fault coverage rate after a fault prediction model is applied, and the reliability of the system is improved. Moreover, the isomorphic dual-channel feature fusion network improves the characterization capability of the time sequence dependence features and the topological correlation features, improves the intermittent fault detection rate, and achieves the exponential shortening of the model optimization period through the cooperation with incremental learning, thereby reducing the operation and maintenance cost, shortening the non-planned shutdown time of equipment, and improving the reliability of the system. And the autonomous operation and maintenance level of the smart power grid can be effectively improved.

The invention discloses an injection molding process fault diagnosis system based on a knowledge graph, and relates to the technical field of injection molding process fault diagnosis. The injection molding process data comprises novel fault case data, maintenance and solution records, expert experience and feedback and new equipment specifications, data preprocessing and structuring are carried out, and a multi-source dynamic data stream is output; and the knowledge increment extraction verification module is used for executing entity identification and relation extraction based on the multi-source dynamic data flow. Multi-dimensional data such as novel fault cases and expert experience are captured in real time through the multi-source data dynamic acquisition module, and the problem that a static knowledge graph cannot be brought into new changes is solved; the knowledge increment extraction verification and self-adaptive updating module can dynamically expand the ontology, incrementally update the atlas and guarantee the data consistency, ensure that the atlas can incorporate fault knowledge related to new materials and new equipment in real time, and expand the fault coverage range.

The application provides a test scheme for checking data retention performance of NOR type Flash memory, focuses on the influence of erase-write cycles on the data retention performance, unifies the erase-write cycle number of the Flash memory test, stipulates clear temperature selection criteria, provides a reference for the Flash memory related test, and comprises the following steps: step one: determining the basic test algorithm of the NOR type Flash memory as the Checkerboard algorithm from the algorithm design complexity and the fault coverage; step two: improving the Checkerboard algorithm process and determining the data retention fault determination step; step three: carrying out a pre-experiment to determine the data retention performance test temperature, erase-write number and sample number of the NOR type Flash memory; step four: determining the erase-write number of the data retention test at normal temperature and the sample number under each erase-write number; step five: determining the test pattern, failure criterion, test duration and test cycle; step six: carrying out the data retention test combined with the erase-write cycle based on the non-replacement timing truncation test; and step seven: test data processing, fitting the average failure time under different erase-write numbers with the erase-write number to obtain the corresponding relationship between the average failure time and the erase-write number.

Safety mechanisms are embedded into a System on a Chip (SoC) and are operable to detect faults present in the logic circuitry in the SoC. Various types of faults in logic circuitry can occur, for example, a bit stuck at 0 or 1, or a transient or temporary fault due to radiation impacting the SoC. SoC devices are required to meet certain automotive safety integrity standards. The most stringent automotive safety integrity level requires that 90% of random latent faults are detected in all relevant logic, including all safety mechanism. Examples disclosed include hardware based checkers and hardware or software based pattern generation methods that achieve high online fault coverage in safety mechanism circuitry used for functional safety. A hardware based safety mechanism monitors the logic circuitry during operation. Any time the safety mechanism detects any faults in the logic circuitry, a fault notification is propagated to upstream logic.

The application discloses a DRAM test method, device, readable storage medium and electronic equipment, through two rounds of tests on the DRAM to be tested, each first preset read-write unit of the DRAM to be tested is traversed based on a preset interval and a preset test unit until all storage units of the DRAM to be tested are traversed, for the target test unit traversed, data read-write operation is performed on the target test unit based on preset test data, the read data is compared with the corresponding written data, the final test result is obtained through the comparison result of the two rounds of tests, the non-continuous access mode with a certain interval can be simulated, the previous test blind area is covered and the chip defects which are difficult to be found in the prior art are detected, the multi-storage unit faults such as bridge faults and coupling faults are excited, the fault coverage is improved, the reliability of the test result is enhanced, and therefore the product yield is improved.

The application provides a new energy vehicle electric drive system fault early warning method, device, equipment and medium, relates to the technical field of fault early warning, and comprises the following steps: based on the current operation condition of the vehicle electric drive system, calling a target efficiency benchmark model matched with the operation condition from a partition adaptive model library to generate a first benchmark efficiency corresponding to the operation condition; based on the real-time operation efficiency of the vehicle electric drive system and the first benchmark efficiency, performing efficiency trend anomaly analysis and component structure anomaly analysis to determine an anomaly confidence; if the anomaly confidence meets a preset fault positioning condition, extracting the efficiency anomaly features corresponding to the vehicle electric drive system, and combining a fault mechanism mapping library to locate the fault components in the vehicle electric drive system and the corresponding fault early warning results. The application can effectively improve the technical problems in the prior art, such as limited fault coverage, delayed early warning response, poor operation condition robustness, weak fault attribution ability, and dependence on manually set fixed thresholds.

The application provides a micro-service architecture-oriented intelligent chaos test method and device, relates to the technical field of software testing, and solves the problems of one-sided fault coverage of traditional tests, rigid strategies, easy triggering of system risks and disconnection with business scenarios. The method comprises the following steps: collecting a service call chain through a distributed tracking technology, and constructing a dynamic dependency graph comprising node importance and link throughput; adopting an LSTM neural network to analyze a business log sequence to identify a business process stage, and establishing a "stage-link-fault" triplet rule; integrating topology features, business stages and real-time operation indexes to construct a state space, and optimizing a fault injection strategy based on a reinforcement learning algorithm and a multi-objective reward function; and limiting the injection intensity and range through a conflict detection and pre-check mechanism. The application is used for reliability verification of a micro-service system, and improves test efficiency and safety.

The application provides a device fault maintenance guidance method and device and a cloud maintenance guidance service platform, relates to the technical field of industrial device fault maintenance, and the device fault maintenance guidance method comprises the following steps: acquiring fault image data of a target device; inputting the fault image data into a visual semantic feature extraction model, performing visual semantic coding processing on the fault image data through the visual semantic feature extraction model, and acquiring a semantic feature vector corresponding to the fault image data; based on the semantic feature vector, performing nearest neighbor retrieval in a preset fault case vector library, and determining at least one candidate fault case vector that satisfies a preset condition in terms of similarity with the semantic feature vector; and generating corresponding candidate fault case information and maintenance guidance information according to the at least one candidate fault case vector. The application can realize end-to-end mapping from a device fault appearance image to maintenance guidance information, and significantly improves the response speed and fault coverage completeness of industrial device fault maintenance.

This invention provides a method, system, device, and storage medium for testing DRAM memory cells. The method includes: writing preset test data into all memory cells of the DRAM to be tested, wherein the memory cells are grouped into memory cell groups according to a preset burst length; creating an access array, accessing the memory cell groups, and obtaining the row and column addresses of the memory cell groups; reading the current test data of the corresponding memory cell group according to the row and column addresses, and comparing it with the preset test data of the memory cell group; if the comparison results are consistent, the memory cell group is determined to have been accessed; obtaining the four adjacent row and column addresses on the diagonal according to the row and column addresses, and determining whether the corresponding adjacent memory cell groups have been accessed according to the adjacent row and column addresses; if all adjacent memory cell groups have been accessed, the test is determined to have passed. This invention can cover test blind spots and detect chip defects that are difficult to find, improve fault coverage, and enhance product quality.

The invention relates to the technical field of pipeline systems, and discloses a pipeline system with an intelligent monitoring function, which comprises a pipeline body, an interface monitoring module, a data relay unit and a remote monitoring terminal, the pipeline body is formed by connecting a plurality of sections of pipe bodies through connectors, and the interface monitoring modules are embedded in grooves in the outer walls of the connectors; the data relay units are arranged at intervals in the length direction of the pipeline body and connected with the interface monitoring module in a wired mode. The remote monitoring terminal is connected with the data relay unit through a wireless communication network, the interface monitoring module comprises a leakage monitoring assembly, a radial displacement monitoring assembly and an axial pull-out monitoring assembly, and the leakage, the radial displacement and the axial pull-out monitoring are integrated through the interface monitoring module for monitoring the leakage, the radial displacement and the axial pull-out and a cooperative structure of the data relay unit and the remote monitoring terminal. Compared with a traditional single fault monitoring scheme, the fault coverage range is remarkably improved, the fault response time is remarkably shortened, and the fault removal precision and efficiency of communication pipeline faults are improved.

The application belongs to the technical field of chip testing, and discloses a chip detection system and method based on ATE and implementation integration. An electrical connection is established between a chip interface unit and a chip to be tested. The chip interface unit comprises an adaptive clamp and a connecting circuit board. A precise contact array is arranged in the adaptive clamp, which is used to reliably connect the chip to be tested and the connecting circuit board. A detection analysis unit executes various types of detection programs of the chip to be tested and collects detection data. A result processing unit receives, integrates and processes the detection data collected by the detection analysis unit, and generates a detection report. In the above manner, the shortcomings of single ATE testing and implementation testing are made up, and the test fault coverage is improved.

The application provides a multifunctional test point allocation method and system based on an adaptive switch matrix, relates to the technical field of electronic testing, and realizes dynamic connection of physical probes and logical test points by acquiring integrated circuit topology information to construct a switch matrix; the same probe is allocated to different test points in different time periods by using time division multiplexing technology, test response signals are collected and deviation values are calculated; a fault point is determined based on the deviation, the influence degree of the fault point on surrounding nodes is analyzed, and a test priority level is obtained; the test timing is dynamically adjusted according to the priority level, high-priority nodes are preferentially tested, the switch state is controlled to realize intelligent allocation of test resources, and the test efficiency and fault coverage are improved.

The application provides an equivalent traversal fault injection method for register error injection single event effect simulation, and is used for solving the technical problem that simulation time consumption and simulation fault coverage exist in contradiction in single event effect simulation of a large-scale integrated circuit register unit. The method is based on a multi-register unit fault injection model, adopts a traversal fault injection file set simulation mode of all register units, maximally discovers a fault condition caused by a single event effect in a to-be-tested circuit, and deletes invalid fault injection files in a fault injection file set corresponding to a register associated group of a non-enabled register unit and an enabled register unit. Space dimension screening is performed on non-working register units in the entire simulation period, and time dimension screening is performed on non-working time of a specified register, so that the time and space costs of simulation are greatly reduced, and the single event fault simulation and evaluation requirements in the design stage of a large-scale space integrated circuit are met.

The utility model discloses an electric wide-body vehicle fault reporting system which comprises a VCU control module, an exterior control module, a power control module, a T-BOX terminal, an instrument and a signal receiving terminal, the whole VCU control module comprises a VCU controller and a controlled assembly which are in signal connection with each other, and the exterior control module comprises an exterior controller and an exterior assembly which are in signal connection with each other. The VCU controller, the external controller and the power control module respectively feed back fault signals to the CAN bus, the T-BOX terminal and the instrument respectively read the fault signals on the CAN bus, the T-BOX terminal feeds back the fault signals to the signal receiving terminal to inform the fault information, and the instrument displays the fault information. According to the utility model, fault coverage and accurate positioning of the whole vehicle are realized, dynamic reliability optimization is carried out, the anti-interference capability is improved, efficient communication is realized, and data collaborative analysis is realized.

The invention provides a sequential circuit fault simulation method, which is used for simulating a sequential circuit fault coverage rate by injecting a fault point into a sequential circuit, and comprises the following steps: S1, obtaining a to-be-simulated circuit netlist, identifying whether a strongly connected component exists in the to-be-simulated circuit netlist, if the to-be-simulated circuit only comprises a simple loop, executing the step S2, and if the to-be-simulated circuit only comprises the simple loop, executing the step S3; if the to-be-simulated circuit contains the complex strong communication component, executing the step S3; s2, simulating a simple loop circuit in a compilation mode, and realizing state updating and fault point injection through an instruction sequence; s3, adopting a preset total in-degree analysis method to calculate the total in-degree of nodes in the circuit containing the complex strongly connected component, and taking the node with the minimum total in-degree as an entrance node so as to hierarchically unfold the circuit; s4, fault points are injected into the circuit containing the complex strong communication components, simulation is carried out, and event scheduling is managed by adopting a preset lazy event propagation strategy in the simulation process; and S5, outputting a simulation report and a fault coverage rate.

The invention relates to the technical field of power transmission equipment, discloses a preparation method of a material compatibility type intelligent early-warning insulated bus, and aims to solve the problems that fault monitoring of an existing insulated bus depends on an external sensor, only a single parameter can be detected, the risk of missing report exists, the insulation aging trend pre-judgment capability is lacked, and the reliability is poor. The technical problem that potential risks cannot be avoided in advance in the prior art is solved, an insulating base material, a functional sensing material, a synergistic dispersant and a functional additive are selected according to a preset ratio, a pre-dispersion liquid is prepared after classification pretreatment, then the pre-dispersion liquid and a pre-molten insulating base material are blended, in-situ dispersion and cross-linking reaction are synchronously executed, an insulating layer is formed by adopting a temperature gradient coating process, and the insulating layer is prepared. And finally, an electrode and an early warning module are integrated, a finished product is obtained through constant-temperature maintenance and performance calibration, the sensing material cooperatively responds to different faults, full-fault coverage is achieved, and the method guarantees stable material compatibility, accurate finished product early warning, rapid response, adaptation to multiple application scenes and remarkable industrial application value.

The invention discloses a digital twinning-based complex product testability scheme heuristic generation method, which comprises the following steps: constructing a digital twinning model of a complex product sensing system, the digital twinning model integrating component fault data and a multi-level signal flow graph; analyzing a fault propagation path based on the multi-level signal flow graph, and determining a candidate test point set; and using an improved genetic algorithm to optimize the candidate test point set according to the component fault data and the fault propagation path, and generating an optimal testability scheme. According to the method, in the testability scheme generation process, the digital twin technology and the heuristic algorithm are combined, and collaborative improvement of the test efficiency, the fault coverage degree and the resource utilization rate is achieved.

The application discloses a DRAM testing method and device, a readable storage medium and an electronic device. Two rounds of tests are performed on a DRAM to be tested. Starting from the first address and the last address of the DRAM to be tested, all storage units of the DRAM to be tested are traversed in a preset test unit until all the storage units of the DRAM to be tested are traversed. For a target test unit traversed, data read-write operations are performed on the target test unit based on preset test data. The read data is compared with the corresponding written data. A final test result is obtained through the comparison result of the two rounds of tests. The ACT-PRE operation of simulating the first activation row, accessing a certain column, and then pre-charging the row can cover the previous test blind area and detect the chip defects that are difficult to be found in the prior art, improve the fault coverage, enhance the reliability of the test result, and thus improve the product yield.

The invention relates to the technical field of function testing, and particularly discloses an automatic testing method based on self-learning and coverage rate evaluation, comprising the following steps: S1, acquiring DUT design parameters and ATE hardware parameters; s2, judging whether the DUT is normal or not, and determining whether normalization processing is carried out or not according to a result; s3, integrating the normalized values into a unified input vector, inputting the unified input vector into a deep reinforcement learning model, and presetting a weight ratio of coverage rate related features; and S4, presetting a current fault coverage rate target, calculating a path prediction value and a time sequence prediction value, adjusting a weight ratio of corresponding features, regenerating a unified input vector, and judging whether iteration is stopped or not. According to the method, redundancy is reduced through parameter matching verification and normalization, cost is reduced, efficiency is improved, coverage rate is predicted based on a reinforcement learning model, yield and reliability are improved, and strategy self-optimization is realized through weight iteration to adapt to various DUTs; testing is promoted to be converted into intelligent driving, and long-term efficiency is improved.

The invention relates to an unmanned aerial vehicle group system reliability calculation method based on an incomplete fault coverage model, and the method comprises the steps: S1, combining multi-stage task features, and listing success probability events meeting function demands in each stage from a subsystem layer; s2, after the earlier stage succeeds, subsystems needing to participate in the subsequent stage and the minimum effective operation quantity of the unmanned aerial vehicle meeting the task success are analyzed; s3, if non-participated subsystems initially exist in a certain stage, the subsystems are irrelevant subsystems, and the reliability of the subsystems in each stage is calculated; and S4, calculating the reliability of the subsequent stage according to S2 and S3, wherein the reliability of the last stage is the reliability of the whole system. According to the method, the situation that the whole system fails due to the fact that part of subsystems are ignored not to participate in a certain stage and uncovered failure is possibly caused is considered, so that the reliability calculation precision is improved, and the method is suitable for multi-stage task systems with high reliability precision requirements such as military, emergency and industrial control.

The present application belongs to the technical field of test vector optimization in electronic information processing discipline, and relates to a kind of adaptive intelligent generation and optimization method of chip test vector, by analyzing the netlist file of the chip to be tested, three types of weights of signal controllability, signal observability and fault sensitivity are given to each signal path, the comprehensive eigenvalue of each node is calculated by forward and backward propagation algorithm, and three-dimensional topological atlas is constructed;Based on the three-dimensional topological atlas, the potential energy function of the candidate test vector is defined, which is dynamically adjusted by the redundancy coefficient, coverage coefficient and entropy weight coefficient according to the optimization progress index;Gradient descent operator, topological tunneling operator and topological homotopy operator are used for collaborative evolution search, and operator selection, population size and termination condition are scheduled through three-layer adaptive mechanism;Using producer-consumer architecture combined with incremental forward fault propagation, the test vector set is efficiently screened, and the fully adaptive and efficient generation of test vector set with high fault coverage and low redundancy is realized.

The invention provides a multifunctional test point distribution method and system based on a self-adaptive switch matrix, and relates to the technical field of electronic testing, and the method comprises the steps: building a switch matrix through obtaining the topological information of an integrated circuit, and achieving the dynamic connection of a physical probe and a logic test point; distributing the same probe to different test points in different time periods by using a time division multiplexing technology, collecting test response signals and calculating a deviation value; determining a fault point based on the deviation, analyzing the influence degree of the fault point on surrounding nodes, and obtaining a test priority level; the test time sequence is dynamically adjusted according to the priority level, high-priority nodes are preferentially tested, the on-off state is controlled to achieve intelligent distribution of test resources, and the test efficiency and the fault coverage rate are improved.

The invention discloses an AI-assisted test vector analysis and optimization method and system, and relates to the technical field of integrated circuit design automation. The method comprises the following steps: a feature extraction step: obtaining a test vector set and extracting multi-dimensional features including fault coverage fingerprints and a scan chain load mode, and constructing a feature matrix; an intelligent clustering step: clustering the test vector set by using an unsupervised clustering algorithm, and dividing vectors with similar functions into the same vector cluster; a representative vector selection step: selecting representative vectors in each vector cluster based on a fault coverage integrity principle to form an optimized vector set; and an iterative optimization step: verifying the optimized vector set, and if a preset condition is not met, dynamically adjusting the clustering parameter and repeating the previous steps. According to the method, deep compression of the test vector is realized through global function similarity analysis, the test time and the test cost can be remarkably reduced, and the method has the advantages of full-automatic post-processing, support of multi-objective optimization and the like.

The invention provides a sequential circuit hybrid fault simulation method, which is used for simulating a sequential circuit fault coverage rate by injecting a fault point into a sequential circuit, and comprises the following steps: S1, obtaining a to-be-simulated circuit netlist, identifying a strong connection component in the to-be-simulated circuit netlist, and marking the strong connection component meeting a preset small-scale strong connection loop constraint condition; s2, performing simulation of multiple periods on the marked circuit netlist to be simulated, and executing in each simulation period: S21, performing code compilation on the marked strong communication components so as to fuse each marked strong communication component into a compilation node, performing compilation type simulation on each compilation node until the state converges, and performing simulation on the compilation node until the state converges; the topology is updated, and the output of each compiling node is used as an event to be transmitted to other areas in the circuit netlist; and S22, taking other areas except the compiling node as event driving nodes, simulating residual circuits in an event scheduling mode, and updating the state of the circuits.

This application discloses a memory testing method, memory testing equipment, and computer program product. The method includes: executing a preset basic fault detection algorithm on multiple consecutive addresses within a memory region under test using at least one preset first test pattern array to detect basic faults in the multiple consecutive addresses; and executing a preset hold fault detection algorithm on the at least one first test pattern array and at least one preset second test pattern array to detect hold faults in the multiple consecutive addresses. Each second test pattern array is a binary sequence repeating every M bits, and each M bit includes at least one logical value with at least three consecutive transitions, where M is a natural number, and 8 ≤ M ≤ the number of bits in the memory cell. This application can significantly improve fault coverage and defect interception rate.

This invention discloses a DRAM testing method, apparatus, computer-readable storage medium, and electronic device. The method involves performing two rounds of testing on the DRAM under test. Preset test data and its inverse are alternately written to the storage array. Based on the written data, each first preset read / write unit is traversed twice, using preset operation units as units. For each target preset operation unit encountered, adjacent preset operation units are determined. Based on the preset test data, data read / write operations are performed on the target preset operation unit and adjacent preset operation units in a preset order. The read data is compared with the corresponding written data. The final test result is obtained through the comparison results of the two rounds of testing. This method achieves proximity access to a chessboard background, covers previous test blind spots, and detects chip defects that are difficult to detect in existing technologies, improving fault coverage, enhancing the reliability of test results, and thus improving product quality.

The invention provides a memory built-in self-test method and device, a test system and electronic equipment. The memory built-in self-test method comprises the following steps: acquiring a test start enable signal based on an I2C communication protocol; generating a plurality of groups of test vectors in response to the test start enable signal; based on a working clock signal of the memory, sequentially writing each group of test vectors into the memory, and reading corresponding output data from the memory; performing consistency comparison on the output data and the expected write-in data to generate memory test information; and outputting the memory test information based on an I2C communication protocol. The method has comprehensive fault detection capability, can realize detection of various types of faults such as fixed faults, partial coupling faults, jump faults, adjacent image sensitive faults and the like, and remarkably improves the fault coverage rate. In addition, the operation process is simple and easy to implement, compatibility is high, work can be carried out without the help of additional testing tools, and the overall testing efficiency is high.

The embodiment of the invention discloses an automatic driving fault simulation method and device, electronic equipment and a storage medium, and relates to the technical field of automatic driving simulation tests.The method comprises the steps that a three-dimensional digital twin map supporting graphic rendering is constructed, and a sensor simulator, a vehicle dynamics model and a traffic flow simulator are integrated; and a digital twinborn simulator and a simulation environment are formed. An automatic driving system is connected to form a closed-loop test system, sensor data is generated in real time, and a simulation vehicle is driven to perform interaction test. Hardware faults such as noise, delay and loss of an injection sensor, bit flipping of calculation hardware and the like are simulated in real time, and the fault-tolerant capability of the system is comprehensively tested. The performance and behavior of the automatic driving system are monitored in real time, and when a failure condition is triggered, scene parameters, fault types and software states are automatically recorded, analyzed and evaluated. According to the invention, the problems of insufficient hardware fault coverage and lack of dynamic fault injection and real-time monitoring capability in the prior art are effectively solved.

Disclosed herein is a self-timed memory circuit with a bypass mode for testing output shadow logic. The circuit is applicable to various memory types, including ROM, HistoRAM, and TCAM. In normal operation, the memory array outputs data through sense amplifiers and latches, controlled by self-timing circuitry. The output then passes through shadow logic for additional processing. The bypass mode allows direct testing of the shadow logic by inputting test patterns (address bits or search keys) that bypass the memory array. These test signals use the same self-timing mechanisms as normal operations, providing for accurate timing representation. This approach enhances fault coverage for shadow logic, enabling detection of transient faults and at-speed errors that might be missed by conventional static testing.